1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2020-2022 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef CPUCP_IF_H 9 #define CPUCP_IF_H 10 11 #include <linux/types.h> 12 #include <linux/if_ether.h> 13 14 #include "hl_boot_if.h" 15 16 #define NUM_HBM_PSEUDO_CH 2 17 #define NUM_HBM_CH_PER_DEV 8 18 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT 0 19 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK 0x00000001 20 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT 1 21 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK 0x00000002 22 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT 2 23 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK 0x00000004 24 #define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT 3 25 #define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK 0x00000008 26 #define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT 4 27 #define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK 0x00000010 28 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT 5 29 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK 0x00000020 30 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT 6 31 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK 0x000007C0 32 33 #define PLL_MAP_MAX_BITS 128 34 #define PLL_MAP_LEN (PLL_MAP_MAX_BITS / 8) 35 36 /* 37 * info of the pkt queue pointers in the first async occurrence 38 */ 39 struct cpucp_pkt_sync_err { 40 __le32 pi; 41 __le32 ci; 42 }; 43 44 struct hl_eq_hbm_ecc_data { 45 /* SERR counter */ 46 __le32 sec_cnt; 47 /* DERR counter */ 48 __le32 dec_cnt; 49 /* Supplemental Information according to the mask bits */ 50 __le32 hbm_ecc_info; 51 /* Address in hbm where the ecc happened */ 52 __le32 first_addr; 53 /* SERR continuous address counter */ 54 __le32 sec_cont_cnt; 55 __le32 pad; 56 }; 57 58 /* 59 * EVENT QUEUE 60 */ 61 62 struct hl_eq_header { 63 __le32 reserved; 64 __le32 ctl; 65 }; 66 67 struct hl_eq_ecc_data { 68 __le64 ecc_address; 69 __le64 ecc_syndrom; 70 __u8 memory_wrapper_idx; 71 __u8 is_critical; 72 __u8 pad[6]; 73 }; 74 75 enum hl_sm_sei_cause { 76 SM_SEI_SO_OVERFLOW, 77 SM_SEI_LBW_4B_UNALIGNED, 78 SM_SEI_AXI_RESPONSE_ERR 79 }; 80 81 struct hl_eq_sm_sei_data { 82 __le32 sei_log; 83 /* enum hl_sm_sei_cause */ 84 __u8 sei_cause; 85 __u8 pad[3]; 86 }; 87 88 enum hl_fw_alive_severity { 89 FW_ALIVE_SEVERITY_MINOR, 90 FW_ALIVE_SEVERITY_CRITICAL 91 }; 92 93 struct hl_eq_fw_alive { 94 __le64 uptime_seconds; 95 __le32 process_id; 96 __le32 thread_id; 97 /* enum hl_fw_alive_severity */ 98 __u8 severity; 99 __u8 pad[7]; 100 }; 101 102 struct hl_eq_intr_cause { 103 __le64 intr_cause_data; 104 }; 105 106 struct hl_eq_pcie_drain_ind_data { 107 struct hl_eq_intr_cause intr_cause; 108 __le64 drain_wr_addr_lbw; 109 __le64 drain_rd_addr_lbw; 110 __le64 drain_wr_addr_hbw; 111 __le64 drain_rd_addr_hbw; 112 }; 113 114 struct hl_eq_razwi_lbw_info_regs { 115 __le32 rr_aw_razwi_reg; 116 __le32 rr_aw_razwi_id_reg; 117 __le32 rr_ar_razwi_reg; 118 __le32 rr_ar_razwi_id_reg; 119 }; 120 121 struct hl_eq_razwi_hbw_info_regs { 122 __le32 rr_aw_razwi_hi_reg; 123 __le32 rr_aw_razwi_lo_reg; 124 __le32 rr_aw_razwi_id_reg; 125 __le32 rr_ar_razwi_hi_reg; 126 __le32 rr_ar_razwi_lo_reg; 127 __le32 rr_ar_razwi_id_reg; 128 }; 129 130 /* razwi_happened masks */ 131 #define RAZWI_HAPPENED_HBW 0x1 132 #define RAZWI_HAPPENED_LBW 0x2 133 #define RAZWI_HAPPENED_AW 0x4 134 #define RAZWI_HAPPENED_AR 0x8 135 136 struct hl_eq_razwi_info { 137 __le32 razwi_happened_mask; 138 union { 139 struct hl_eq_razwi_lbw_info_regs lbw; 140 struct hl_eq_razwi_hbw_info_regs hbw; 141 }; 142 __le32 pad; 143 }; 144 145 struct hl_eq_razwi_with_intr_cause { 146 struct hl_eq_razwi_info razwi_info; 147 struct hl_eq_intr_cause intr_cause; 148 }; 149 150 #define HBM_CA_ERR_CMD_LIFO_LEN 8 151 #define HBM_RD_ERR_DATA_LIFO_LEN 8 152 #define HBM_WR_PAR_CMD_LIFO_LEN 11 153 154 enum hl_hbm_sei_cause { 155 /* Command/address parity error event is split into 2 events due to 156 * size limitation: ODD suffix for odd HBM CK_t cycles and EVEN suffix 157 * for even HBM CK_t cycles 158 */ 159 HBM_SEI_CMD_PARITY_EVEN, 160 HBM_SEI_CMD_PARITY_ODD, 161 /* Read errors can be reflected as a combination of SERR/DERR/parity 162 * errors. Therefore, we define one event for all read error types. 163 * LKD will perform further proccessing. 164 */ 165 HBM_SEI_READ_ERR, 166 HBM_SEI_WRITE_DATA_PARITY_ERR, 167 HBM_SEI_CATTRIP, 168 HBM_SEI_MEM_BIST_FAIL, 169 HBM_SEI_DFI, 170 HBM_SEI_INV_TEMP_READ_OUT, 171 HBM_SEI_BIST_FAIL, 172 }; 173 174 /* Masks for parsing hl_hbm_sei_headr fields */ 175 #define HBM_ECC_SERR_CNTR_MASK 0xFF 176 #define HBM_ECC_DERR_CNTR_MASK 0xFF00 177 #define HBM_RD_PARITY_CNTR_MASK 0xFF0000 178 179 /* HBM index and MC index are known by the event_id */ 180 struct hl_hbm_sei_header { 181 union { 182 /* relevant only in case of HBM read error */ 183 struct { 184 __u8 ecc_serr_cnt; 185 __u8 ecc_derr_cnt; 186 __u8 read_par_cnt; 187 __u8 reserved; 188 }; 189 /* All other cases */ 190 __le32 cnt; 191 }; 192 __u8 sei_cause; /* enum hl_hbm_sei_cause */ 193 __u8 mc_channel; /* range: 0-3 */ 194 __u8 mc_pseudo_channel; /* range: 0-7 */ 195 __u8 is_critical; 196 }; 197 198 #define HBM_RD_ADDR_SID_SHIFT 0 199 #define HBM_RD_ADDR_SID_MASK 0x1 200 #define HBM_RD_ADDR_BG_SHIFT 1 201 #define HBM_RD_ADDR_BG_MASK 0x6 202 #define HBM_RD_ADDR_BA_SHIFT 3 203 #define HBM_RD_ADDR_BA_MASK 0x18 204 #define HBM_RD_ADDR_COL_SHIFT 5 205 #define HBM_RD_ADDR_COL_MASK 0x7E0 206 #define HBM_RD_ADDR_ROW_SHIFT 11 207 #define HBM_RD_ADDR_ROW_MASK 0x3FFF800 208 209 struct hbm_rd_addr { 210 union { 211 /* bit fields are only for FW use */ 212 struct { 213 u32 dbg_rd_err_addr_sid:1; 214 u32 dbg_rd_err_addr_bg:2; 215 u32 dbg_rd_err_addr_ba:2; 216 u32 dbg_rd_err_addr_col:6; 217 u32 dbg_rd_err_addr_row:15; 218 u32 reserved:6; 219 }; 220 __le32 rd_addr_val; 221 }; 222 }; 223 224 #define HBM_RD_ERR_BEAT_SHIFT 2 225 /* dbg_rd_err_misc fields: */ 226 /* Read parity is calculated per DW on every beat */ 227 #define HBM_RD_ERR_PAR_ERR_BEAT0_SHIFT 0 228 #define HBM_RD_ERR_PAR_ERR_BEAT0_MASK 0x3 229 #define HBM_RD_ERR_PAR_DATA_BEAT0_SHIFT 8 230 #define HBM_RD_ERR_PAR_DATA_BEAT0_MASK 0x300 231 /* ECC is calculated per PC on every beat */ 232 #define HBM_RD_ERR_SERR_BEAT0_SHIFT 16 233 #define HBM_RD_ERR_SERR_BEAT0_MASK 0x10000 234 #define HBM_RD_ERR_DERR_BEAT0_SHIFT 24 235 #define HBM_RD_ERR_DERR_BEAT0_MASK 0x100000 236 237 struct hl_eq_hbm_sei_read_err_intr_info { 238 /* DFI_RD_ERR_REP_ADDR */ 239 struct hbm_rd_addr dbg_rd_err_addr; 240 /* DFI_RD_ERR_REP_ERR */ 241 union { 242 struct { 243 /* bit fields are only for FW use */ 244 u32 dbg_rd_err_par:8; 245 u32 dbg_rd_err_par_data:8; 246 u32 dbg_rd_err_serr:4; 247 u32 dbg_rd_err_derr:4; 248 u32 reserved:8; 249 }; 250 __le32 dbg_rd_err_misc; 251 }; 252 /* DFI_RD_ERR_REP_DM */ 253 __le32 dbg_rd_err_dm; 254 /* DFI_RD_ERR_REP_SYNDROME */ 255 __le32 dbg_rd_err_syndrome; 256 /* DFI_RD_ERR_REP_DATA */ 257 __le32 dbg_rd_err_data[HBM_RD_ERR_DATA_LIFO_LEN]; 258 }; 259 260 struct hl_eq_hbm_sei_ca_par_intr_info { 261 /* 14 LSBs */ 262 __le16 dbg_row[HBM_CA_ERR_CMD_LIFO_LEN]; 263 /* 18 LSBs */ 264 __le32 dbg_col[HBM_CA_ERR_CMD_LIFO_LEN]; 265 }; 266 267 #define WR_PAR_LAST_CMD_COL_SHIFT 0 268 #define WR_PAR_LAST_CMD_COL_MASK 0x3F 269 #define WR_PAR_LAST_CMD_BG_SHIFT 6 270 #define WR_PAR_LAST_CMD_BG_MASK 0xC0 271 #define WR_PAR_LAST_CMD_BA_SHIFT 8 272 #define WR_PAR_LAST_CMD_BA_MASK 0x300 273 #define WR_PAR_LAST_CMD_SID_SHIFT 10 274 #define WR_PAR_LAST_CMD_SID_MASK 0x400 275 276 /* Row address isn't latched */ 277 struct hbm_sei_wr_cmd_address { 278 /* DFI_DERR_LAST_CMD */ 279 union { 280 struct { 281 /* bit fields are only for FW use */ 282 u32 col:6; 283 u32 bg:2; 284 u32 ba:2; 285 u32 sid:1; 286 u32 reserved:21; 287 }; 288 __le32 dbg_wr_cmd_addr; 289 }; 290 }; 291 292 struct hl_eq_hbm_sei_wr_par_intr_info { 293 /* entry 0: WR command address from the 1st cycle prior to the error 294 * entry 1: WR command address from the 2nd cycle prior to the error 295 * and so on... 296 */ 297 struct hbm_sei_wr_cmd_address dbg_last_wr_cmds[HBM_WR_PAR_CMD_LIFO_LEN]; 298 /* derr[0:1] - 1st HBM cycle DERR output 299 * derr[2:3] - 2nd HBM cycle DERR output 300 */ 301 __u8 dbg_derr; 302 /* extend to reach 8B */ 303 __u8 pad[3]; 304 }; 305 306 /* 307 * this struct represents the following sei causes: 308 * command parity, ECC double error, ECC single error, dfi error, cattrip, 309 * temperature read-out, read parity error and write parity error. 310 * some only use the header while some have extra data. 311 */ 312 struct hl_eq_hbm_sei_data { 313 struct hl_hbm_sei_header hdr; 314 union { 315 struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_even_info; 316 struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_odd_info; 317 struct hl_eq_hbm_sei_read_err_intr_info read_err_info; 318 struct hl_eq_hbm_sei_wr_par_intr_info wr_parity_info; 319 }; 320 }; 321 322 /* Engine/farm arc interrupt type */ 323 enum hl_engine_arc_interrupt_type { 324 /* Qman/farm ARC DCCM QUEUE FULL interrupt type */ 325 ENGINE_ARC_DCCM_QUEUE_FULL_IRQ = 1 326 }; 327 328 /* Data structure specifies details of payload of DCCM QUEUE FULL interrupt */ 329 struct hl_engine_arc_dccm_queue_full_irq { 330 /* Queue index value which caused DCCM QUEUE FULL */ 331 __le32 queue_index; 332 __le32 pad; 333 }; 334 335 /* Data structure specifies details of QM/FARM ARC interrupt */ 336 struct hl_eq_engine_arc_intr_data { 337 /* ARC engine id e.g. DCORE0_TPC0_QM_ARC, DCORE0_TCP1_QM_ARC */ 338 __le32 engine_id; 339 __le32 intr_type; /* enum hl_engine_arc_interrupt_type */ 340 /* More info related to the interrupt e.g. queue index 341 * incase of DCCM_QUEUE_FULL interrupt. 342 */ 343 __le64 payload; 344 __le64 pad[5]; 345 }; 346 347 struct hl_eq_entry { 348 struct hl_eq_header hdr; 349 union { 350 struct hl_eq_ecc_data ecc_data; 351 struct hl_eq_hbm_ecc_data hbm_ecc_data; /* Gaudi1 HBM */ 352 struct hl_eq_sm_sei_data sm_sei_data; 353 struct cpucp_pkt_sync_err pkt_sync_err; 354 struct hl_eq_fw_alive fw_alive; 355 struct hl_eq_intr_cause intr_cause; 356 struct hl_eq_pcie_drain_ind_data pcie_drain_ind_data; 357 struct hl_eq_razwi_info razwi_info; 358 struct hl_eq_razwi_with_intr_cause razwi_with_intr_cause; 359 struct hl_eq_hbm_sei_data sei_data; /* Gaudi2 HBM */ 360 struct hl_eq_engine_arc_intr_data arc_data; 361 __le64 data[7]; 362 }; 363 }; 364 365 #define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry) 366 367 #define EQ_CTL_READY_SHIFT 31 368 #define EQ_CTL_READY_MASK 0x80000000 369 370 #define EQ_CTL_EVENT_TYPE_SHIFT 16 371 #define EQ_CTL_EVENT_TYPE_MASK 0x0FFF0000 372 373 #define EQ_CTL_INDEX_SHIFT 0 374 #define EQ_CTL_INDEX_MASK 0x0000FFFF 375 376 enum pq_init_status { 377 PQ_INIT_STATUS_NA = 0, 378 PQ_INIT_STATUS_READY_FOR_CP, 379 PQ_INIT_STATUS_READY_FOR_HOST, 380 PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI, 381 PQ_INIT_STATUS_LEN_NOT_POWER_OF_TWO_ERR, 382 PQ_INIT_STATUS_ILLEGAL_Q_ADDR_ERR 383 }; 384 385 /* 386 * CpuCP Primary Queue Packets 387 * 388 * During normal operation, the host's kernel driver needs to send various 389 * messages to CpuCP, usually either to SET some value into a H/W periphery or 390 * to GET the current value of some H/W periphery. For example, SET the 391 * frequency of MME/TPC and GET the value of the thermal sensor. 392 * 393 * These messages can be initiated either by the User application or by the 394 * host's driver itself, e.g. power management code. In either case, the 395 * communication from the host's driver to CpuCP will *always* be in 396 * synchronous mode, meaning that the host will send a single message and poll 397 * until the message was acknowledged and the results are ready (if results are 398 * needed). 399 * 400 * This means that only a single message can be sent at a time and the host's 401 * driver must wait for its result before sending the next message. Having said 402 * that, because these are control messages which are sent in a relatively low 403 * frequency, this limitation seems acceptable. It's important to note that 404 * in case of multiple devices, messages to different devices *can* be sent 405 * at the same time. 406 * 407 * The message, inputs/outputs (if relevant) and fence object will be located 408 * on the device DDR at an address that will be determined by the host's driver. 409 * During device initialization phase, the host will pass to CpuCP that address. 410 * Most of the message types will contain inputs/outputs inside the message 411 * itself. The common part of each message will contain the opcode of the 412 * message (its type) and a field representing a fence object. 413 * 414 * When the host's driver wishes to send a message to CPU CP, it will write the 415 * message contents to the device DDR, clear the fence object and then write to 416 * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU. 417 * 418 * Upon receiving the interrupt (#121), CpuCP will read the message from the 419 * DDR. In case the message is a SET operation, CpuCP will first perform the 420 * operation and then write to the fence object on the device DDR. In case the 421 * message is a GET operation, CpuCP will first fill the results section on the 422 * device DDR and then write to the fence object. If an error occurred, CpuCP 423 * will fill the rc field with the right error code. 424 * 425 * In the meantime, the host's driver will poll on the fence object. Once the 426 * host sees that the fence object is signaled, it will read the results from 427 * the device DDR (if relevant) and resume the code execution in the host's 428 * driver. 429 * 430 * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8 431 * so the value being put by the host's driver matches the value read by CpuCP 432 * 433 * Non-QMAN packets should be limited to values 1 through (2^8 - 1) 434 * 435 * Detailed description: 436 * 437 * CPUCP_PACKET_DISABLE_PCI_ACCESS - 438 * After receiving this packet the embedded CPU must NOT issue PCI 439 * transactions (read/write) towards the Host CPU. This also include 440 * sending MSI-X interrupts. 441 * This packet is usually sent before the device is moved to D3Hot state. 442 * 443 * CPUCP_PACKET_ENABLE_PCI_ACCESS - 444 * After receiving this packet the embedded CPU is allowed to issue PCI 445 * transactions towards the Host CPU, including sending MSI-X interrupts. 446 * This packet is usually send after the device is moved to D0 state. 447 * 448 * CPUCP_PACKET_TEMPERATURE_GET - 449 * Fetch the current temperature / Max / Max Hyst / Critical / 450 * Critical Hyst of a specified thermal sensor. The packet's 451 * arguments specify the desired sensor and the field to get. 452 * 453 * CPUCP_PACKET_VOLTAGE_GET - 454 * Fetch the voltage / Max / Min of a specified sensor. The packet's 455 * arguments specify the sensor and type. 456 * 457 * CPUCP_PACKET_CURRENT_GET - 458 * Fetch the current / Max / Min of a specified sensor. The packet's 459 * arguments specify the sensor and type. 460 * 461 * CPUCP_PACKET_FAN_SPEED_GET - 462 * Fetch the speed / Max / Min of a specified fan. The packet's 463 * arguments specify the sensor and type. 464 * 465 * CPUCP_PACKET_PWM_GET - 466 * Fetch the pwm value / mode of a specified pwm. The packet's 467 * arguments specify the sensor and type. 468 * 469 * CPUCP_PACKET_PWM_SET - 470 * Set the pwm value / mode of a specified pwm. The packet's 471 * arguments specify the sensor, type and value. 472 * 473 * CPUCP_PACKET_FREQUENCY_SET - 474 * Set the frequency of a specified PLL. The packet's arguments specify 475 * the PLL and the desired frequency. The actual frequency in the device 476 * might differ from the requested frequency. 477 * 478 * CPUCP_PACKET_FREQUENCY_GET - 479 * Fetch the frequency of a specified PLL. The packet's arguments specify 480 * the PLL. 481 * 482 * CPUCP_PACKET_LED_SET - 483 * Set the state of a specified led. The packet's arguments 484 * specify the led and the desired state. 485 * 486 * CPUCP_PACKET_I2C_WR - 487 * Write 32-bit value to I2C device. The packet's arguments specify the 488 * I2C bus, address and value. 489 * 490 * CPUCP_PACKET_I2C_RD - 491 * Read 32-bit value from I2C device. The packet's arguments specify the 492 * I2C bus and address. 493 * 494 * CPUCP_PACKET_INFO_GET - 495 * Fetch information from the device as specified in the packet's 496 * structure. The host's driver passes the max size it allows the CpuCP to 497 * write to the structure, to prevent data corruption in case of 498 * mismatched driver/FW versions. 499 * 500 * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed 501 * 502 * CPUCP_PACKET_UNMASK_RAZWI_IRQ - 503 * Unmask the given IRQ. The IRQ number is specified in the value field. 504 * The packet is sent after receiving an interrupt and printing its 505 * relevant information. 506 * 507 * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY - 508 * Unmask the given IRQs. The IRQs numbers are specified in an array right 509 * after the cpucp_packet structure, where its first element is the array 510 * length. The packet is sent after a soft reset was done in order to 511 * handle any interrupts that were sent during the reset process. 512 * 513 * CPUCP_PACKET_TEST - 514 * Test packet for CpuCP connectivity. The CPU will put the fence value 515 * in the result field. 516 * 517 * CPUCP_PACKET_FREQUENCY_CURR_GET - 518 * Fetch the current frequency of a specified PLL. The packet's arguments 519 * specify the PLL. 520 * 521 * CPUCP_PACKET_MAX_POWER_GET - 522 * Fetch the maximal power of the device. 523 * 524 * CPUCP_PACKET_MAX_POWER_SET - 525 * Set the maximal power of the device. The packet's arguments specify 526 * the power. 527 * 528 * CPUCP_PACKET_EEPROM_DATA_GET - 529 * Get EEPROM data from the CpuCP kernel. The buffer is specified in the 530 * addr field. The CPU will put the returned data size in the result 531 * field. In addition, the host's driver passes the max size it allows the 532 * CpuCP to write to the structure, to prevent data corruption in case of 533 * mismatched driver/FW versions. 534 * 535 * CPUCP_PACKET_NIC_INFO_GET - 536 * Fetch information from the device regarding the NIC. the host's driver 537 * passes the max size it allows the CpuCP to write to the structure, to 538 * prevent data corruption in case of mismatched driver/FW versions. 539 * 540 * CPUCP_PACKET_TEMPERATURE_SET - 541 * Set the value of the offset property of a specified thermal sensor. 542 * The packet's arguments specify the desired sensor and the field to 543 * set. 544 * 545 * CPUCP_PACKET_VOLTAGE_SET - 546 * Trigger the reset_history property of a specified voltage sensor. 547 * The packet's arguments specify the desired sensor and the field to 548 * set. 549 * 550 * CPUCP_PACKET_CURRENT_SET - 551 * Trigger the reset_history property of a specified current sensor. 552 * The packet's arguments specify the desired sensor and the field to 553 * set. 554 * 555 * CPUCP_PACKET_PCIE_THROUGHPUT_GET - 556 * Get throughput of PCIe. 557 * The packet's arguments specify the transaction direction (TX/RX). 558 * The window measurement is 10[msec], and the return value is in KB/sec. 559 * 560 * CPUCP_PACKET_PCIE_REPLAY_CNT_GET 561 * Replay count measures number of "replay" events, which is basicly 562 * number of retries done by PCIe. 563 * 564 * CPUCP_PACKET_TOTAL_ENERGY_GET - 565 * Total Energy is measurement of energy from the time FW Linux 566 * is loaded. It is calculated by multiplying the average power 567 * by time (passed from armcp start). The units are in MilliJouls. 568 * 569 * CPUCP_PACKET_PLL_INFO_GET - 570 * Fetch frequencies of PLL from the required PLL IP. 571 * The packet's arguments specify the device PLL type 572 * Pll type is the PLL from device pll_index enum. 573 * The result is composed of 4 outputs, each is 16-bit 574 * frequency in MHz. 575 * 576 * CPUCP_PACKET_POWER_GET - 577 * Fetch the present power consumption of the device (Current * Voltage). 578 * 579 * CPUCP_PACKET_NIC_PFC_SET - 580 * Enable/Disable the NIC PFC feature. The packet's arguments specify the 581 * NIC port, relevant lanes to configure and one bit indication for 582 * enable/disable. 583 * 584 * CPUCP_PACKET_NIC_FAULT_GET - 585 * Fetch the current indication for local/remote faults from the NIC MAC. 586 * The result is 32-bit value of the relevant register. 587 * 588 * CPUCP_PACKET_NIC_LPBK_SET - 589 * Enable/Disable the MAC loopback feature. The packet's arguments specify 590 * the NIC port, relevant lanes to configure and one bit indication for 591 * enable/disable. 592 * 593 * CPUCP_PACKET_NIC_MAC_INIT - 594 * Configure the NIC MAC channels. The packet's arguments specify the 595 * NIC port and the speed. 596 * 597 * CPUCP_PACKET_MSI_INFO_SET - 598 * set the index number for each supported msi type going from 599 * host to device 600 * 601 * CPUCP_PACKET_NIC_XPCS91_REGS_GET - 602 * Fetch the un/correctable counters values from the NIC MAC. 603 * 604 * CPUCP_PACKET_NIC_STAT_REGS_GET - 605 * Fetch various NIC MAC counters from the NIC STAT. 606 * 607 * CPUCP_PACKET_NIC_STAT_REGS_CLR - 608 * Clear the various NIC MAC counters in the NIC STAT. 609 * 610 * CPUCP_PACKET_NIC_STAT_REGS_ALL_GET - 611 * Fetch all NIC MAC counters from the NIC STAT. 612 * 613 * CPUCP_PACKET_IS_IDLE_CHECK - 614 * Check if the device is IDLE in regard to the DMA/compute engines 615 * and QMANs. The f/w will return a bitmask where each bit represents 616 * a different engine or QMAN according to enum cpucp_idle_mask. 617 * The bit will be 1 if the engine is NOT idle. 618 * 619 * CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET - 620 * Fetch all HBM replaced-rows and prending to be replaced rows data. 621 * 622 * CPUCP_PACKET_HBM_PENDING_ROWS_STATUS - 623 * Fetch status of HBM rows pending replacement and need a reboot to 624 * be replaced. 625 * 626 * CPUCP_PACKET_POWER_SET - 627 * Resets power history of device to 0 628 * 629 * CPUCP_PACKET_ENGINE_CORE_ASID_SET - 630 * Packet to perform engine core ASID configuration 631 * 632 * CPUCP_PACKET_SEC_ATTEST_GET - 633 * Get the attestaion data that is collected during various stages of the 634 * boot sequence. the attestation data is also hashed with some unique 635 * number (nonce) provided by the host to prevent replay attacks. 636 * public key and certificate also provided as part of the FW response. 637 * 638 * CPUCP_PACKET_MONITOR_DUMP_GET - 639 * Get monitors registers dump from the CpuCP kernel. 640 * The CPU will put the registers dump in the a buffer allocated by the driver 641 * which address is passed via the CpuCp packet. In addition, the host's driver 642 * passes the max size it allows the CpuCP to write to the structure, to prevent 643 * data corruption in case of mismatched driver/FW versions. 644 * Relevant only to Gaudi. 645 * 646 * CPUCP_PACKET_ACTIVE_STATUS_SET - 647 * LKD sends FW indication whether device is free or in use, this indication is reported 648 * also to the BMC. 649 */ 650 651 enum cpucp_packet_id { 652 CPUCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */ 653 CPUCP_PACKET_ENABLE_PCI_ACCESS, /* internal */ 654 CPUCP_PACKET_TEMPERATURE_GET, /* sysfs */ 655 CPUCP_PACKET_VOLTAGE_GET, /* sysfs */ 656 CPUCP_PACKET_CURRENT_GET, /* sysfs */ 657 CPUCP_PACKET_FAN_SPEED_GET, /* sysfs */ 658 CPUCP_PACKET_PWM_GET, /* sysfs */ 659 CPUCP_PACKET_PWM_SET, /* sysfs */ 660 CPUCP_PACKET_FREQUENCY_SET, /* sysfs */ 661 CPUCP_PACKET_FREQUENCY_GET, /* sysfs */ 662 CPUCP_PACKET_LED_SET, /* debugfs */ 663 CPUCP_PACKET_I2C_WR, /* debugfs */ 664 CPUCP_PACKET_I2C_RD, /* debugfs */ 665 CPUCP_PACKET_INFO_GET, /* IOCTL */ 666 CPUCP_PACKET_FLASH_PROGRAM_REMOVED, 667 CPUCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */ 668 CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */ 669 CPUCP_PACKET_TEST, /* internal */ 670 CPUCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */ 671 CPUCP_PACKET_MAX_POWER_GET, /* sysfs */ 672 CPUCP_PACKET_MAX_POWER_SET, /* sysfs */ 673 CPUCP_PACKET_EEPROM_DATA_GET, /* sysfs */ 674 CPUCP_PACKET_NIC_INFO_GET, /* internal */ 675 CPUCP_PACKET_TEMPERATURE_SET, /* sysfs */ 676 CPUCP_PACKET_VOLTAGE_SET, /* sysfs */ 677 CPUCP_PACKET_CURRENT_SET, /* sysfs */ 678 CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ 679 CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ 680 CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */ 681 CPUCP_PACKET_PLL_INFO_GET, /* internal */ 682 CPUCP_PACKET_NIC_STATUS, /* internal */ 683 CPUCP_PACKET_POWER_GET, /* internal */ 684 CPUCP_PACKET_NIC_PFC_SET, /* internal */ 685 CPUCP_PACKET_NIC_FAULT_GET, /* internal */ 686 CPUCP_PACKET_NIC_LPBK_SET, /* internal */ 687 CPUCP_PACKET_NIC_MAC_CFG, /* internal */ 688 CPUCP_PACKET_MSI_INFO_SET, /* internal */ 689 CPUCP_PACKET_NIC_XPCS91_REGS_GET, /* internal */ 690 CPUCP_PACKET_NIC_STAT_REGS_GET, /* internal */ 691 CPUCP_PACKET_NIC_STAT_REGS_CLR, /* internal */ 692 CPUCP_PACKET_NIC_STAT_REGS_ALL_GET, /* internal */ 693 CPUCP_PACKET_IS_IDLE_CHECK, /* internal */ 694 CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET,/* internal */ 695 CPUCP_PACKET_HBM_PENDING_ROWS_STATUS, /* internal */ 696 CPUCP_PACKET_POWER_SET, /* internal */ 697 CPUCP_PACKET_RESERVED, /* not used */ 698 CPUCP_PACKET_ENGINE_CORE_ASID_SET, /* internal */ 699 CPUCP_PACKET_RESERVED2, /* not used */ 700 CPUCP_PACKET_SEC_ATTEST_GET, /* internal */ 701 CPUCP_PACKET_RESERVED3, /* not used */ 702 CPUCP_PACKET_RESERVED4, /* not used */ 703 CPUCP_PACKET_MONITOR_DUMP_GET, /* debugfs */ 704 CPUCP_PACKET_RESERVED5, /* not used */ 705 CPUCP_PACKET_RESERVED6, /* not used */ 706 CPUCP_PACKET_RESERVED7, /* not used */ 707 CPUCP_PACKET_RESERVED8, /* not used */ 708 CPUCP_PACKET_RESERVED9, /* not used */ 709 CPUCP_PACKET_ACTIVE_STATUS_SET, /* internal */ 710 CPUCP_PACKET_ID_MAX /* must be last */ 711 }; 712 713 #define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5 714 715 #define CPUCP_PKT_CTL_RC_SHIFT 12 716 #define CPUCP_PKT_CTL_RC_MASK 0x0000F000 717 718 #define CPUCP_PKT_CTL_OPCODE_SHIFT 16 719 #define CPUCP_PKT_CTL_OPCODE_MASK 0x1FFF0000 720 721 #define CPUCP_PKT_RES_PLL_OUT0_SHIFT 0 722 #define CPUCP_PKT_RES_PLL_OUT0_MASK 0x000000000000FFFFull 723 #define CPUCP_PKT_RES_PLL_OUT1_SHIFT 16 724 #define CPUCP_PKT_RES_PLL_OUT1_MASK 0x00000000FFFF0000ull 725 #define CPUCP_PKT_RES_PLL_OUT2_SHIFT 32 726 #define CPUCP_PKT_RES_PLL_OUT2_MASK 0x0000FFFF00000000ull 727 #define CPUCP_PKT_RES_PLL_OUT3_SHIFT 48 728 #define CPUCP_PKT_RES_PLL_OUT3_MASK 0xFFFF000000000000ull 729 730 #define CPUCP_PKT_VAL_PFC_IN1_SHIFT 0 731 #define CPUCP_PKT_VAL_PFC_IN1_MASK 0x0000000000000001ull 732 #define CPUCP_PKT_VAL_PFC_IN2_SHIFT 1 733 #define CPUCP_PKT_VAL_PFC_IN2_MASK 0x000000000000001Eull 734 735 #define CPUCP_PKT_VAL_LPBK_IN1_SHIFT 0 736 #define CPUCP_PKT_VAL_LPBK_IN1_MASK 0x0000000000000001ull 737 #define CPUCP_PKT_VAL_LPBK_IN2_SHIFT 1 738 #define CPUCP_PKT_VAL_LPBK_IN2_MASK 0x000000000000001Eull 739 740 #define CPUCP_PKT_VAL_MAC_CNT_IN1_SHIFT 0 741 #define CPUCP_PKT_VAL_MAC_CNT_IN1_MASK 0x0000000000000001ull 742 #define CPUCP_PKT_VAL_MAC_CNT_IN2_SHIFT 1 743 #define CPUCP_PKT_VAL_MAC_CNT_IN2_MASK 0x00000000FFFFFFFEull 744 745 /* heartbeat status bits */ 746 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_SHIFT 0 747 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_MASK 0x00000001 748 749 struct cpucp_packet { 750 union { 751 __le64 value; /* For SET packets */ 752 __le64 result; /* For GET packets */ 753 __le64 addr; /* For PQ */ 754 }; 755 756 __le32 ctl; 757 758 __le32 fence; /* Signal to host that message is completed */ 759 760 union { 761 struct {/* For temperature/current/voltage/fan/pwm get/set */ 762 __le16 sensor_index; 763 __le16 type; 764 }; 765 766 struct { /* For I2C read/write */ 767 __u8 i2c_bus; 768 __u8 i2c_addr; 769 __u8 i2c_reg; 770 /* 771 * In legacy implemetations, i2c_len was not present, 772 * was unused and just added as pad. 773 * So if i2c_len is 0, it is treated as legacy 774 * and r/w 1 Byte, else if i2c_len is specified, 775 * its treated as new multibyte r/w support. 776 */ 777 __u8 i2c_len; 778 }; 779 780 struct {/* For PLL info fetch */ 781 __le16 pll_type; 782 /* TODO pll_reg is kept temporary before removal */ 783 __le16 pll_reg; 784 }; 785 786 /* For any general request */ 787 __le32 index; 788 789 /* For frequency get/set */ 790 __le32 pll_index; 791 792 /* For led set */ 793 __le32 led_index; 794 795 /* For get CpuCP info/EEPROM data/NIC info */ 796 __le32 data_max_size; 797 798 /* 799 * For any general status bitmask. Shall be used whenever the 800 * result cannot be used to hold general purpose data. 801 */ 802 __le32 status_mask; 803 804 /* random, used once number, for security packets */ 805 __le32 nonce; 806 }; 807 808 /* For NIC requests */ 809 __le32 port_index; 810 }; 811 812 struct cpucp_unmask_irq_arr_packet { 813 struct cpucp_packet cpucp_pkt; 814 __le32 length; 815 __le32 irqs[]; 816 }; 817 818 struct cpucp_nic_status_packet { 819 struct cpucp_packet cpucp_pkt; 820 __le32 length; 821 __le32 data[]; 822 }; 823 824 struct cpucp_array_data_packet { 825 struct cpucp_packet cpucp_pkt; 826 __le32 length; 827 __le32 data[]; 828 }; 829 830 enum cpucp_led_index { 831 CPUCP_LED0_INDEX = 0, 832 CPUCP_LED1_INDEX, 833 CPUCP_LED2_INDEX 834 }; 835 836 /* 837 * enum cpucp_packet_rc - Error return code 838 * @cpucp_packet_success -> in case of success. 839 * @cpucp_packet_invalid -> this is to support Goya and Gaudi platform. 840 * @cpucp_packet_fault -> in case of processing error like failing to 841 * get device binding or semaphore etc. 842 * @cpucp_packet_invalid_pkt -> when cpucp packet is un-supported. This is 843 * supported Greco onwards. 844 * @cpucp_packet_invalid_params -> when checking parameter like length of buffer 845 * or attribute value etc. Supported Greco onwards. 846 * @cpucp_packet_rc_max -> It indicates size of enum so should be at last. 847 */ 848 enum cpucp_packet_rc { 849 cpucp_packet_success, 850 cpucp_packet_invalid, 851 cpucp_packet_fault, 852 cpucp_packet_invalid_pkt, 853 cpucp_packet_invalid_params, 854 cpucp_packet_rc_max 855 }; 856 857 /* 858 * cpucp_temp_type should adhere to hwmon_temp_attributes 859 * defined in Linux kernel hwmon.h file 860 */ 861 enum cpucp_temp_type { 862 cpucp_temp_input, 863 cpucp_temp_min = 4, 864 cpucp_temp_min_hyst, 865 cpucp_temp_max = 6, 866 cpucp_temp_max_hyst, 867 cpucp_temp_crit, 868 cpucp_temp_crit_hyst, 869 cpucp_temp_offset = 19, 870 cpucp_temp_lowest = 21, 871 cpucp_temp_highest = 22, 872 cpucp_temp_reset_history = 23, 873 cpucp_temp_warn = 24, 874 cpucp_temp_max_crit = 25, 875 cpucp_temp_max_warn = 26, 876 }; 877 878 enum cpucp_in_attributes { 879 cpucp_in_input, 880 cpucp_in_min, 881 cpucp_in_max, 882 cpucp_in_lowest = 6, 883 cpucp_in_highest = 7, 884 cpucp_in_reset_history 885 }; 886 887 enum cpucp_curr_attributes { 888 cpucp_curr_input, 889 cpucp_curr_min, 890 cpucp_curr_max, 891 cpucp_curr_lowest = 6, 892 cpucp_curr_highest = 7, 893 cpucp_curr_reset_history 894 }; 895 896 enum cpucp_fan_attributes { 897 cpucp_fan_input, 898 cpucp_fan_min = 2, 899 cpucp_fan_max 900 }; 901 902 enum cpucp_pwm_attributes { 903 cpucp_pwm_input, 904 cpucp_pwm_enable 905 }; 906 907 enum cpucp_pcie_throughput_attributes { 908 cpucp_pcie_throughput_tx, 909 cpucp_pcie_throughput_rx 910 }; 911 912 /* TODO temporary kept before removal */ 913 enum cpucp_pll_reg_attributes { 914 cpucp_pll_nr_reg, 915 cpucp_pll_nf_reg, 916 cpucp_pll_od_reg, 917 cpucp_pll_div_factor_reg, 918 cpucp_pll_div_sel_reg 919 }; 920 921 /* TODO temporary kept before removal */ 922 enum cpucp_pll_type_attributes { 923 cpucp_pll_cpu, 924 cpucp_pll_pci, 925 }; 926 927 /* 928 * cpucp_power_type aligns with hwmon_power_attributes 929 * defined in Linux kernel hwmon.h file 930 */ 931 enum cpucp_power_type { 932 CPUCP_POWER_INPUT = 8, 933 CPUCP_POWER_INPUT_HIGHEST = 9, 934 CPUCP_POWER_RESET_INPUT_HISTORY = 11 935 }; 936 937 /* 938 * MSI type enumeration table for all ASICs and future SW versions. 939 * For future ASIC-LKD compatibility, we can only add new enumerations. 940 * at the end of the table (before CPUCP_NUM_OF_MSI_TYPES). 941 * Changing the order of entries or removing entries is not allowed. 942 */ 943 enum cpucp_msi_type { 944 CPUCP_EVENT_QUEUE_MSI_TYPE, 945 CPUCP_NIC_PORT1_MSI_TYPE, 946 CPUCP_NIC_PORT3_MSI_TYPE, 947 CPUCP_NIC_PORT5_MSI_TYPE, 948 CPUCP_NIC_PORT7_MSI_TYPE, 949 CPUCP_NIC_PORT9_MSI_TYPE, 950 CPUCP_NUM_OF_MSI_TYPES 951 }; 952 953 /* 954 * PLL enumeration table used for all ASICs and future SW versions. 955 * For future ASIC-LKD compatibility, we can only add new enumerations. 956 * at the end of the table. 957 * Changing the order of entries or removing entries is not allowed. 958 */ 959 enum pll_index { 960 CPU_PLL = 0, 961 PCI_PLL = 1, 962 NIC_PLL = 2, 963 DMA_PLL = 3, 964 MESH_PLL = 4, 965 MME_PLL = 5, 966 TPC_PLL = 6, 967 IF_PLL = 7, 968 SRAM_PLL = 8, 969 NS_PLL = 9, 970 HBM_PLL = 10, 971 MSS_PLL = 11, 972 DDR_PLL = 12, 973 VID_PLL = 13, 974 BANK_PLL = 14, 975 MMU_PLL = 15, 976 IC_PLL = 16, 977 MC_PLL = 17, 978 EMMC_PLL = 18, 979 PLL_MAX 980 }; 981 982 enum rl_index { 983 TPC_RL = 0, 984 MME_RL, 985 EDMA_RL, 986 }; 987 988 enum pvt_index { 989 PVT_SW, 990 PVT_SE, 991 PVT_NW, 992 PVT_NE 993 }; 994 995 /* Event Queue Packets */ 996 997 struct eq_generic_event { 998 __le64 data[7]; 999 }; 1000 1001 /* 1002 * CpuCP info 1003 */ 1004 1005 #define CARD_NAME_MAX_LEN 16 1006 #define CPUCP_MAX_SENSORS 128 1007 #define CPUCP_MAX_NICS 128 1008 #define CPUCP_LANES_PER_NIC 4 1009 #define CPUCP_NIC_QSFP_EEPROM_MAX_LEN 1024 1010 #define CPUCP_MAX_NIC_LANES (CPUCP_MAX_NICS * CPUCP_LANES_PER_NIC) 1011 #define CPUCP_NIC_MASK_ARR_LEN ((CPUCP_MAX_NICS + 63) / 64) 1012 #define CPUCP_NIC_POLARITY_ARR_LEN ((CPUCP_MAX_NIC_LANES + 63) / 64) 1013 #define CPUCP_HBM_ROW_REPLACE_MAX 32 1014 1015 struct cpucp_sensor { 1016 __le32 type; 1017 __le32 flags; 1018 }; 1019 1020 /** 1021 * struct cpucp_card_types - ASIC card type. 1022 * @cpucp_card_type_pci: PCI card. 1023 * @cpucp_card_type_pmc: PCI Mezzanine Card. 1024 */ 1025 enum cpucp_card_types { 1026 cpucp_card_type_pci, 1027 cpucp_card_type_pmc 1028 }; 1029 1030 #define CPUCP_SEC_CONF_ENABLED_SHIFT 0 1031 #define CPUCP_SEC_CONF_ENABLED_MASK 0x00000001 1032 1033 #define CPUCP_SEC_CONF_FLASH_WP_SHIFT 1 1034 #define CPUCP_SEC_CONF_FLASH_WP_MASK 0x00000002 1035 1036 #define CPUCP_SEC_CONF_EEPROM_WP_SHIFT 2 1037 #define CPUCP_SEC_CONF_EEPROM_WP_MASK 0x00000004 1038 1039 /** 1040 * struct cpucp_security_info - Security information. 1041 * @config: configuration bit field 1042 * @keys_num: number of stored keys 1043 * @revoked_keys: revoked keys bit field 1044 * @min_svn: minimal security version 1045 */ 1046 struct cpucp_security_info { 1047 __u8 config; 1048 __u8 keys_num; 1049 __u8 revoked_keys; 1050 __u8 min_svn; 1051 }; 1052 1053 /** 1054 * struct cpucp_info - Info from CpuCP that is necessary to the host's driver 1055 * @sensors: available sensors description. 1056 * @kernel_version: CpuCP linux kernel version. 1057 * @reserved: reserved field. 1058 * @card_type: card configuration type. 1059 * @card_location: in a server, each card has different connections topology 1060 * depending on its location (relevant for PMC card type) 1061 * @cpld_version: CPLD programmed F/W version. 1062 * @infineon_version: Infineon main DC-DC version. 1063 * @fuse_version: silicon production FUSE information. 1064 * @thermal_version: thermald S/W version. 1065 * @cpucp_version: CpuCP S/W version. 1066 * @infineon_second_stage_version: Infineon 2nd stage DC-DC version. 1067 * @dram_size: available DRAM size. 1068 * @card_name: card name that will be displayed in HWMON subsystem on the host 1069 * @tpc_binning_mask: TPC binning mask, 1 bit per TPC instance 1070 * (0 = functional, 1 = binned) 1071 * @decoder_binning_mask: Decoder binning mask, 1 bit per decoder instance 1072 * (0 = functional, 1 = binned), maximum 1 per dcore 1073 * @sram_binning: Categorize SRAM functionality 1074 * (0 = fully functional, 1 = lower-half is not functional, 1075 * 2 = upper-half is not functional) 1076 * @sec_info: security information 1077 * @pll_map: Bit map of supported PLLs for current ASIC version. 1078 * @mme_binning_mask: MME binning mask, 1079 * bits [0:6] <==> dcore0 mme fma 1080 * bits [7:13] <==> dcore1 mme fma 1081 * bits [14:20] <==> dcore0 mme ima 1082 * bits [21:27] <==> dcore1 mme ima 1083 * For each group, if the 6th bit is set then first 5 bits 1084 * represent the col's idx [0-31], otherwise these bits are 1085 * ignored, and col idx 32 is binned. 7th bit is don't care. 1086 * @dram_binning_mask: DRAM binning mask, 1 bit per dram instance 1087 * (0 = functional 1 = binned) 1088 * @memory_repair_flag: eFuse flag indicating memory repair 1089 * @edma_binning_mask: EDMA binning mask, 1 bit per EDMA instance 1090 * (0 = functional 1 = binned) 1091 * @xbar_binning_mask: Xbar binning mask, 1 bit per Xbar instance 1092 * (0 = functional 1 = binned) 1093 * @interposer_version: Interposer version programmed in eFuse 1094 * @substrate_version: Substrate version programmed in eFuse 1095 * @fw_os_version: Firmware OS Version 1096 */ 1097 struct cpucp_info { 1098 struct cpucp_sensor sensors[CPUCP_MAX_SENSORS]; 1099 __u8 kernel_version[VERSION_MAX_LEN]; 1100 __le32 reserved; 1101 __le32 card_type; 1102 __le32 card_location; 1103 __le32 cpld_version; 1104 __le32 infineon_version; 1105 __u8 fuse_version[VERSION_MAX_LEN]; 1106 __u8 thermal_version[VERSION_MAX_LEN]; 1107 __u8 cpucp_version[VERSION_MAX_LEN]; 1108 __le32 infineon_second_stage_version; 1109 __le64 dram_size; 1110 char card_name[CARD_NAME_MAX_LEN]; 1111 __le64 tpc_binning_mask; 1112 __le64 decoder_binning_mask; 1113 __u8 sram_binning; 1114 __u8 dram_binning_mask; 1115 __u8 memory_repair_flag; 1116 __u8 edma_binning_mask; 1117 __u8 xbar_binning_mask; 1118 __u8 interposer_version; 1119 __u8 substrate_version; 1120 __u8 reserved2; 1121 struct cpucp_security_info sec_info; 1122 __le32 reserved3; 1123 __u8 pll_map[PLL_MAP_LEN]; 1124 __le64 mme_binning_mask; 1125 __u8 fw_os_version[VERSION_MAX_LEN]; 1126 }; 1127 1128 struct cpucp_mac_addr { 1129 __u8 mac_addr[ETH_ALEN]; 1130 }; 1131 1132 enum cpucp_serdes_type { 1133 TYPE_1_SERDES_TYPE, 1134 TYPE_2_SERDES_TYPE, 1135 HLS1_SERDES_TYPE, 1136 HLS1H_SERDES_TYPE, 1137 HLS2_SERDES_TYPE, 1138 UNKNOWN_SERDES_TYPE, 1139 MAX_NUM_SERDES_TYPE = UNKNOWN_SERDES_TYPE 1140 }; 1141 1142 struct cpucp_nic_info { 1143 struct cpucp_mac_addr mac_addrs[CPUCP_MAX_NICS]; 1144 __le64 link_mask[CPUCP_NIC_MASK_ARR_LEN]; 1145 __le64 pol_tx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; 1146 __le64 pol_rx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; 1147 __le64 link_ext_mask[CPUCP_NIC_MASK_ARR_LEN]; 1148 __u8 qsfp_eeprom[CPUCP_NIC_QSFP_EEPROM_MAX_LEN]; 1149 __le64 auto_neg_mask[CPUCP_NIC_MASK_ARR_LEN]; 1150 __le16 serdes_type; /* enum cpucp_serdes_type */ 1151 __le16 tx_swap_map[CPUCP_MAX_NICS]; 1152 __u8 reserved[6]; 1153 }; 1154 1155 #define PAGE_DISCARD_MAX 64 1156 1157 struct page_discard_info { 1158 __u8 num_entries; 1159 __u8 reserved[7]; 1160 __le32 mmu_page_idx[PAGE_DISCARD_MAX]; 1161 }; 1162 1163 /* 1164 * struct ser_val - the SER (symbol error rate) value is represented by "integer * 10 ^ -exp". 1165 * @integer: the integer part of the SER value; 1166 * @exp: the exponent part of the SER value. 1167 */ 1168 struct ser_val { 1169 __le16 integer; 1170 __le16 exp; 1171 }; 1172 1173 /* 1174 * struct cpucp_nic_status - describes the status of a NIC port. 1175 * @port: NIC port index. 1176 * @bad_format_cnt: e.g. CRC. 1177 * @responder_out_of_sequence_psn_cnt: e.g NAK. 1178 * @high_ber_reinit_cnt: link reinit due to high BER. 1179 * @correctable_err_cnt: e.g. bit-flip. 1180 * @uncorrectable_err_cnt: e.g. MAC errors. 1181 * @retraining_cnt: re-training counter. 1182 * @up: is port up. 1183 * @pcs_link: has PCS link. 1184 * @phy_ready: is PHY ready. 1185 * @auto_neg: is Autoneg enabled. 1186 * @timeout_retransmission_cnt: timeout retransmission events 1187 * @high_ber_cnt: high ber events 1188 */ 1189 struct cpucp_nic_status { 1190 __le32 port; 1191 __le32 bad_format_cnt; 1192 __le32 responder_out_of_sequence_psn_cnt; 1193 __le32 high_ber_reinit; 1194 __le32 correctable_err_cnt; 1195 __le32 uncorrectable_err_cnt; 1196 __le32 retraining_cnt; 1197 __u8 up; 1198 __u8 pcs_link; 1199 __u8 phy_ready; 1200 __u8 auto_neg; 1201 __le32 timeout_retransmission_cnt; 1202 __le32 high_ber_cnt; 1203 }; 1204 1205 enum cpucp_hbm_row_replace_cause { 1206 REPLACE_CAUSE_DOUBLE_ECC_ERR, 1207 REPLACE_CAUSE_MULTI_SINGLE_ECC_ERR, 1208 }; 1209 1210 struct cpucp_hbm_row_info { 1211 __u8 hbm_idx; 1212 __u8 pc; 1213 __u8 sid; 1214 __u8 bank_idx; 1215 __le16 row_addr; 1216 __u8 replaced_row_cause; /* enum cpucp_hbm_row_replace_cause */ 1217 __u8 pad; 1218 }; 1219 1220 struct cpucp_hbm_row_replaced_rows_info { 1221 __le16 num_replaced_rows; 1222 __u8 pad[6]; 1223 struct cpucp_hbm_row_info replaced_rows[CPUCP_HBM_ROW_REPLACE_MAX]; 1224 }; 1225 1226 enum cpu_reset_status { 1227 CPU_RST_STATUS_NA = 0, 1228 CPU_RST_STATUS_SOFT_RST_DONE = 1, 1229 }; 1230 1231 #define SEC_PCR_DATA_BUF_SZ 256 1232 #define SEC_PCR_QUOTE_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ 1233 #define SEC_SIGNATURE_BUF_SZ 255 /* (256 - 1) 1 byte used for size */ 1234 #define SEC_PUB_DATA_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ 1235 #define SEC_CERTIFICATE_BUF_SZ 2046 /* (2048 - 2) 2 bytes used for size */ 1236 1237 /* 1238 * struct cpucp_sec_attest_info - attestation report of the boot 1239 * @pcr_data: raw values of the PCR registers 1240 * @pcr_num_reg: number of PCR registers in the pcr_data array 1241 * @pcr_reg_len: length of each PCR register in the pcr_data array (bytes) 1242 * @nonce: number only used once. random number provided by host. this also 1243 * passed to the quote command as a qualifying data. 1244 * @pcr_quote_len: length of the attestation quote data (bytes) 1245 * @pcr_quote: attestation report data structure 1246 * @quote_sig_len: length of the attestation report signature (bytes) 1247 * @quote_sig: signature structure of the attestation report 1248 * @pub_data_len: length of the public data (bytes) 1249 * @public_data: public key for the signed attestation 1250 * (outPublic + name + qualifiedName) 1251 * @certificate_len: length of the certificate (bytes) 1252 * @certificate: certificate for the attestation signing key 1253 */ 1254 struct cpucp_sec_attest_info { 1255 __u8 pcr_data[SEC_PCR_DATA_BUF_SZ]; 1256 __u8 pcr_num_reg; 1257 __u8 pcr_reg_len; 1258 __le16 pad0; 1259 __le32 nonce; 1260 __le16 pcr_quote_len; 1261 __u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ]; 1262 __u8 quote_sig_len; 1263 __u8 quote_sig[SEC_SIGNATURE_BUF_SZ]; 1264 __le16 pub_data_len; 1265 __u8 public_data[SEC_PUB_DATA_BUF_SZ]; 1266 __le16 certificate_len; 1267 __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; 1268 }; 1269 1270 /* 1271 * struct cpucp_dev_info_signed - device information signed by a secured device 1272 * @info: device information structure as defined above 1273 * @nonce: number only used once. random number provided by host. this number is 1274 * hashed and signed along with the device information. 1275 * @info_sig_len: length of the attestation signature (bytes) 1276 * @info_sig: signature of the info + nonce data. 1277 * @pub_data_len: length of the public data (bytes) 1278 * @public_data: public key info signed info data 1279 * (outPublic + name + qualifiedName) 1280 * @certificate_len: length of the certificate (bytes) 1281 * @certificate: certificate for the signing key 1282 */ 1283 struct cpucp_dev_info_signed { 1284 struct cpucp_info info; /* assumed to be 64bit aligned */ 1285 __le32 nonce; 1286 __le32 pad0; 1287 __u8 info_sig_len; 1288 __u8 info_sig[SEC_SIGNATURE_BUF_SZ]; 1289 __le16 pub_data_len; 1290 __u8 public_data[SEC_PUB_DATA_BUF_SZ]; 1291 __le16 certificate_len; 1292 __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; 1293 }; 1294 1295 /* 1296 * struct dcore_monitor_regs_data - DCORE monitor regs data. 1297 * the structure follows sync manager block layout. relevant only to Gaudi. 1298 * @mon_pay_addrl: array of payload address low bits. 1299 * @mon_pay_addrh: array of payload address high bits. 1300 * @mon_pay_data: array of payload data. 1301 * @mon_arm: array of monitor arm. 1302 * @mon_status: array of monitor status. 1303 */ 1304 struct dcore_monitor_regs_data { 1305 __le32 mon_pay_addrl[512]; 1306 __le32 mon_pay_addrh[512]; 1307 __le32 mon_pay_data[512]; 1308 __le32 mon_arm[512]; 1309 __le32 mon_status[512]; 1310 }; 1311 1312 /* contains SM data for each SYNC_MNGR (relevant only to Gaudi) */ 1313 struct cpucp_monitor_dump { 1314 struct dcore_monitor_regs_data sync_mngr_w_s; 1315 struct dcore_monitor_regs_data sync_mngr_e_s; 1316 struct dcore_monitor_regs_data sync_mngr_w_n; 1317 struct dcore_monitor_regs_data sync_mngr_e_n; 1318 }; 1319 1320 #endif /* CPUCP_IF_H */ 1321