| /drivers/soc/samsung/ |
| D | s3c-pm-check.c | 37 static u32 *crcs; /* allocated over suspend/resume */ variable
99 crcs = kmalloc(crc_size+4, GFP_KERNEL); in s3c_pm_check_prepare()
100 if (crcs == NULL) in s3c_pm_check_prepare()
130 if (crcs != NULL) in s3c_pm_check_store()
131 s3c_pm_run_sysram(s3c_pm_makecheck, crcs); in s3c_pm_check_store()
185 if (in_region(ptr, left, crcs, crc_size)) { in s3c_pm_runcheck()
216 if (crcs != NULL) in s3c_pm_check_restore()
217 s3c_pm_run_sysram(s3c_pm_runcheck, crcs); in s3c_pm_check_restore()
230 kfree(crcs); in s3c_pm_check_cleanup()
231 crcs = NULL; in s3c_pm_check_cleanup()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_display_trace.h | 75 TP_PROTO(struct intel_crtc *crtc, const u32 *crcs),
76 TP_ARGS(crtc, crcs),
82 __array(u32, crcs, 5)
89 memcpy(__entry->crcs, crcs, sizeof(__entry->crcs));
94 __entry->crcs[0], __entry->crcs[1], __entry->crcs[2],
95 __entry->crcs[3], __entry->crcs[4])
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| /drivers/gpu/drm/ |
| D | drm_debugfs_crc.c | 335 sprintf(buf + 10 + i * 11, " 0x%08x", entry->crcs[i]); in crtc_crc_read()
394 uint32_t frame, uint32_t *crcs) in drm_crtc_add_crc_entry() argument
427 memcpy(&entry->crcs, crcs, sizeof(*crcs) * crc->values_cnt); in drm_crtc_add_crc_entry()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_crc.c | 394 uint32_t crcs[3]; in amdgpu_dm_crtc_handle_crc_irq() local
426 &crcs[0], &crcs[1], &crcs[2])) in amdgpu_dm_crtc_handle_crc_irq()
430 drm_crtc_accurate_vblank_count(crtc), crcs); in amdgpu_dm_crtc_handle_crc_irq()
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| /drivers/infiniband/hw/qib/ |
| D | qib_driver.c | 451 u32 eflags, etype, tlen, i = 0, updegr = 0, crcs = 0; in qib_kreceive() local
509 crcs += qib_rcv_hdrerr(rcd, ppd, rcd->ctxt, eflags, l, in qib_kreceive()
513 if (crcs) in qib_kreceive()
514 crcs--; in qib_kreceive()
584 return crcs; in qib_kreceive()
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| D | qib_iba6120.c | 1590 u32 istat, ctxtrbits, rmask, crcs = 0; in qib_6120intr() local
1645 crcs += qib_kreceive(dd->rcd[i], in qib_6120intr()
1651 if (crcs) { in qib_6120intr()
1654 cntr += crcs; in qib_6120intr()
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_crtc.c | 213 u32 crcs[CRTC_DUAL_MIXERS]; in dpu_crtc_get_lm_crc() local
218 BUILD_BUG_ON(ARRAY_SIZE(crcs) != ARRAY_SIZE(crtc_state->mixers)); in dpu_crtc_get_lm_crc()
227 rc = m->hw_lm->ops.collect_misr(m->hw_lm, &crcs[i]); in dpu_crtc_get_lm_crc()
237 drm_crtc_accurate_vblank_count(crtc), crcs); in dpu_crtc_get_lm_crc()
244 u32 crcs[INTF_MAX]; in dpu_crtc_get_encoder_crc() local
247 rc = dpu_encoder_get_crc(drm_enc, crcs, pos); in dpu_crtc_get_encoder_crc()
259 drm_crtc_accurate_vblank_count(crtc), crcs); in dpu_crtc_get_encoder_crc()
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| D | dpu_encoder.h | 197 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos);
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| D | dpu_encoder.c | 267 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos) in dpu_encoder_get_crc() argument
286 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]); in dpu_encoder_get_crc()
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| /drivers/gpu/drm/display/ |
| D | drm_dp_helper.c | 1988 uint32_t crcs[3]; in drm_dp_aux_crc_work() local
2015 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8; in drm_dp_aux_crc_work()
2016 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8; in drm_dp_aux_crc_work()
2017 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8; in drm_dp_aux_crc_work()
2018 drm_crtc_add_crc_entry(crtc, false, 0, crcs); in drm_dp_aux_crc_work()
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| /drivers/gpu/drm/i915/ |
| D | i915_irq.c | 1324 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 }; in display_pipe_crc_irq_handler() local
1326 trace_intel_pipe_crc(crtc, crcs); in display_pipe_crc_irq_handler()
1347 crcs); in display_pipe_crc_irq_handler()
|