Searched refs:ctrl_offset (Results 1 – 8 of 8) sorted by relevance
| /drivers/thermal/ |
| D | k3_bandgap.c | 89 u32 ctrl_offset; member
204 data[id].ctrl_offset = K3_VTM_TMPSENS0_CTRL_OFFSET + in k3_bandgap_probe()
206 data[id].stat_offset = data[id].ctrl_offset + 0x8; in k3_bandgap_probe()
208 val = readl(data[id].bgp->base + data[id].ctrl_offset); in k3_bandgap_probe()
213 writel(val, data[id].bgp->base + data[id].ctrl_offset); in k3_bandgap_probe()
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| D | k3_j72xx_bandgap.c | 187 u32 ctrl_offset; member
452 data[id].ctrl_offset = K3_VTM_TMPSENS0_CTRL_OFFSET + id * 0x20; in k3_j72xx_bandgap_probe()
453 data[id].stat_offset = data[id].ctrl_offset + in k3_j72xx_bandgap_probe()
470 val = readl(data[id].bgp->cfg2_base + data[id].ctrl_offset); in k3_j72xx_bandgap_probe()
474 writel(val, data[id].bgp->cfg2_base + data[id].ctrl_offset); in k3_j72xx_bandgap_probe()
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| /drivers/reset/ |
| D | reset-lpc18xx.c | 71 u32 ctrl_offset = LPC18XX_RGU_CTRL0; in lpc18xx_rgu_setclear_reset() local
76 ctrl_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32); in lpc18xx_rgu_setclear_reset()
82 writel(stat | rst_bit, rc->base + ctrl_offset); in lpc18xx_rgu_setclear_reset()
84 writel(stat & ~rst_bit, rc->base + ctrl_offset); in lpc18xx_rgu_setclear_reset()
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| D | reset-npcm.c | 117 unsigned int ctrl_offset = id >> 8; in npcm_rc_setclear_reset() local
122 stat = readl(rc->base + ctrl_offset); in npcm_rc_setclear_reset()
124 writel(stat | rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
126 writel(stat & ~rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
148 unsigned int ctrl_offset = id >> 8; in npcm_rc_status() local
150 return (readl(rc->base + ctrl_offset) & rst_bit); in npcm_rc_status()
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| /drivers/pinctrl/mediatek/ |
| D | mtk-eint.c | 323 unsigned int rst, ctrl_offset; in mtk_eint_debounce_process() local
326 ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl; in mtk_eint_debounce_process()
327 dbnc = readl(eint->base + ctrl_offset); in mtk_eint_debounce_process()
330 ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set; in mtk_eint_debounce_process()
332 writel(rst, eint->base + ctrl_offset); in mtk_eint_debounce_process()
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| /drivers/dma/xilinx/ |
| D | xilinx_dma.c | 416 u32 ctrl_offset; member
522 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
544 return dma_read(chan, chan->ctrl_offset + reg); in dma_ctrl_read()
550 dma_write(chan, chan->ctrl_offset + reg, value); in dma_ctrl_write()
588 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg); in dma_writeq()
2820 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; in xilinx_dma_chan_probe()
2845 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET; in xilinx_dma_chan_probe()
2847 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; in xilinx_dma_chan_probe()
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| /drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| D | dma.c | 383 static bool _dma64_addrext(struct dma_info *di, uint ctrl_offset) in _dma64_addrext() argument
386 bcma_set32(di->core, ctrl_offset, D64_XC_AE); in _dma64_addrext()
387 w = bcma_read32(di->core, ctrl_offset); in _dma64_addrext()
388 bcma_mask32(di->core, ctrl_offset, ~D64_XC_AE); in _dma64_addrext()
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| /drivers/net/ethernet/netronome/nfp/ |
| D | nfp_net_common.c | 553 nfp_net_aux_irq_request(struct nfp_net *nn, u32 ctrl_offset, in nfp_net_aux_irq_request() argument
569 nn_writeb(nn, ctrl_offset, entry->entry); in nfp_net_aux_irq_request()
581 static void nfp_net_aux_irq_free(struct nfp_net *nn, u32 ctrl_offset, in nfp_net_aux_irq_free() argument
584 nn_writeb(nn, ctrl_offset, 0xff); in nfp_net_aux_irq_free()
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