| /drivers/gpu/drm/i915/display/ |
| D | intel_bw.c | 658 unsigned int data_rate = 0; in intel_bw_crtc_data_rate() local
669 data_rate += crtc_state->data_rate[plane_id]; in intel_bw_crtc_data_rate()
672 data_rate += crtc_state->data_rate_y[plane_id]; in intel_bw_crtc_data_rate()
675 return data_rate; in intel_bw_crtc_data_rate()
696 bw_state->data_rate[crtc->pipe] = in intel_bw_crtc_update()
703 bw_state->data_rate[crtc->pipe], in intel_bw_crtc_update()
722 unsigned int data_rate = 0; in intel_bw_data_rate() local
726 data_rate += bw_state->data_rate[pipe]; in intel_bw_data_rate()
729 data_rate = DIV_ROUND_UP(data_rate * 105, 100); in intel_bw_data_rate()
731 return data_rate; in intel_bw_data_rate()
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| D | intel_bw.h | 45 unsigned int data_rate[I915_MAX_PIPES]; member
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| D | skl_watermark.c | 1341 u64 data_rate = 0; in skl_total_relative_data_rate() local
1347 data_rate += crtc_state->rel_data_rate[plane_id]; in skl_total_relative_data_rate()
1350 data_rate += crtc_state->rel_data_rate_y[plane_id]; in skl_total_relative_data_rate()
1353 return data_rate; in skl_total_relative_data_rate()
1424 u64 data_rate; member
1432 u64 data_rate) in skl_allocate_plane_ddb() argument
1436 if (data_rate) { in skl_allocate_plane_ddb()
1438 DIV64_U64_ROUND_UP(iter->size * data_rate, in skl_allocate_plane_ddb()
1439 iter->data_rate)); in skl_allocate_plane_ddb()
1441 iter->data_rate -= data_rate; in skl_allocate_plane_ddb()
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| /drivers/iio/adc/ |
| D | ti-ads1015.c | 83 const int *data_rate; member
235 unsigned int data_rate; member
398 const int *data_rate = data->chip->data_rate; in ads1015_get_adc_result() local
410 dr = data->channel_data[chan].data_rate; in ads1015_get_adc_result()
433 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr_old]); in ads1015_get_adc_result()
434 conv_time += DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr]); in ads1015_get_adc_result()
501 if (data->chip->data_rate[i] == rate) { in ads1015_set_data_rate()
502 data->channel_data[chan].data_rate = i; in ads1015_set_data_rate()
528 *vals = data->chip->data_rate; in ads1015_read_avail()
584 idx = data->channel_data[chan->address].data_rate; in ads1015_read_raw()
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| D | ti-ads131e08.c | 97 unsigned int data_rate; member
249 static int ads131e08_set_data_rate(struct ads131e08_state *st, int data_rate) in ads131e08_set_data_rate() argument
254 if (ads131e08_data_rate_tbl[i].rate == data_rate) in ads131e08_set_data_rate()
275 st->data_rate = data_rate; in ads131e08_set_data_rate()
277 ADS131E08_NUM_DATA_BYTES(st->data_rate) * in ads131e08_set_data_rate()
491 channel->channel * ADS131E08_NUM_DATA_BYTES(st->data_rate); in ads131e08_read_direct()
493 num_bits = ADS131E08_NUM_DATA_BITS(st->data_rate); in ads131e08_read_direct()
531 *value2 = ADS131E08_NUM_DATA_BITS(st->data_rate) - 1; in ads131e08_read_raw()
536 *value = st->data_rate; in ads131e08_read_raw()
629 unsigned int num_bytes = ADS131E08_NUM_DATA_BYTES(st->data_rate); in ads131e08_trigger_handler()
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| /drivers/phy/mediatek/ |
| D | phy-mtk-mipi-dsi-mt8183.c | 54 dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate); in mtk_mipi_tx_pll_enable()
56 if (mipi_tx->data_rate >= 2000000000) { in mtk_mipi_tx_pll_enable()
59 } else if (mipi_tx->data_rate >= 1000000000) { in mtk_mipi_tx_pll_enable()
62 } else if (mipi_tx->data_rate >= 500000000) { in mtk_mipi_tx_pll_enable()
65 } else if (mipi_tx->data_rate > 250000000) { in mtk_mipi_tx_pll_enable()
68 } else if (mipi_tx->data_rate >= 125000000) { in mtk_mipi_tx_pll_enable()
81 pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000); in mtk_mipi_tx_pll_enable()
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| D | phy-mtk-mipi-dsi-mt8173.c | 129 dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate); in mtk_mipi_tx_pll_prepare()
131 if (mipi_tx->data_rate >= 500000000) { in mtk_mipi_tx_pll_prepare()
135 } else if (mipi_tx->data_rate >= 250000000) { in mtk_mipi_tx_pll_prepare()
139 } else if (mipi_tx->data_rate >= 125000000) { in mtk_mipi_tx_pll_prepare()
143 } else if (mipi_tx->data_rate > 62000000) { in mtk_mipi_tx_pll_prepare()
147 } else if (mipi_tx->data_rate >= 50000000) { in mtk_mipi_tx_pll_prepare()
196 pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, 26000000); in mtk_mipi_tx_pll_prepare()
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| D | phy-mtk-mipi-dsi.c | 20 mipi_tx->data_rate = rate; in mtk_mipi_tx_pll_set_rate()
30 return mipi_tx->data_rate; in mtk_mipi_tx_pll_recalc_rate()
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| D | phy-mtk-mipi-dsi.h | 30 u32 data_rate; member
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| /drivers/media/dvb-frontends/ |
| D | si21xx.c | 352 u32 sym_rate, data_rate; in si21xx_set_symbolrate() local
361 data_rate = srate; in si21xx_set_symbolrate()
366 sym_rate = sym_rate + ((data_rate % 100) * 0x800000) / in si21xx_set_symbolrate()
368 data_rate /= 100; in si21xx_set_symbolrate()
727 int data_rate; in si21xx_set_frontend() local
748 data_rate = c->symbol_rate / 100; in si21xx_set_frontend()
751 + (data_rate * 135)) / 200; in si21xx_set_frontend()
754 + (data_rate * 135)) / 200; in si21xx_set_frontend()
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| /drivers/char/hw_random/ |
| D | optee-rng.c | 65 u32 data_rate; member
131 if (wait && pvt_data->data_rate) { in optee_rng_read()
134 msleep((1000 * (max - read)) / pvt_data->data_rate); in optee_rng_read()
200 pvt_data.data_rate = param[0].u.value.a; in get_optee_rng_info()
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| /drivers/staging/rtl8192e/ |
| D | rtllib_tx.c | 344 if (tcb_desc->data_rate == 2) in rtllib_query_ShortPreambleMode()
385 if ((tcb_desc->data_rate & 0x80) == 0) in rtllib_query_BandwidthMode()
890 tcb_desc->data_rate = in rtllib_xmit_inter()
894 tcb_desc->data_rate = ieee->basic_rate; in rtllib_xmit_inter()
908 tcb_desc->data_rate = ieee->basic_rate; in rtllib_xmit_inter()
910 tcb_desc->data_rate = rtllib_current_rate(ieee); in rtllib_xmit_inter()
915 tcb_desc->data_rate = in rtllib_xmit_inter()
919 tcb_desc->data_rate = MGN_1M; in rtllib_xmit_inter()
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| /drivers/gpu/drm/radeon/ |
| D | rv740_dpm.c | 97 u16 data_rate; in rv740_get_dll_speed() local
104 data_rate = (u16)(memory_clock * factor / 1000); in rv740_get_dll_speed()
106 if (data_rate < dll_speed_table[0].max) { in rv740_get_dll_speed()
108 if (data_rate > dll_speed_table[i].min && in rv740_get_dll_speed()
109 data_rate <= dll_speed_table[i].max) in rv740_get_dll_speed()
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| /drivers/net/wireless/marvell/mwifiex/ |
| D | join.c | 161 priv->data_rate); in mwifiex_get_common_rates()
165 if ((*ptr & 0x7f) == priv->data_rate) { in mwifiex_get_common_rates()
174 priv->data_rate); in mwifiex_get_common_rates()
955 memset(adhoc_start->data_rate, 0, sizeof(adhoc_start->data_rate)); in mwifiex_cmd_802_11_ad_hoc_start()
956 mwifiex_get_active_data_rates(priv, adhoc_start->data_rate); in mwifiex_cmd_802_11_ad_hoc_start()
968 for (i = 0; i < sizeof(adhoc_start->data_rate); i++) in mwifiex_cmd_802_11_ad_hoc_start()
969 if (!adhoc_start->data_rate[i]) in mwifiex_cmd_802_11_ad_hoc_start()
976 &adhoc_start->data_rate, priv->curr_bss_params.num_of_rates); in mwifiex_cmd_802_11_ad_hoc_start()
979 adhoc_start->data_rate); in mwifiex_cmd_802_11_ad_hoc_start()
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| /drivers/net/wireless/realtek/rtw89/ |
| D | core.c | 537 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req); in rtw89_core_tx_update_mgmt_info()
541 desc_info->data_rate, chan->channel, chan->band_type, in rtw89_core_tx_update_mgmt_info()
991 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); in rtw89_build_txwd_body7_v1()
999 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | in rtw89_build_txwd_info0()
1312 u16 data_rate; in rtw89_core_rx_ppdu_match() local
1315 data_rate = desc_info->data_rate; in rtw89_core_rx_ppdu_match()
1316 data_rate_mode = GET_DATA_RATE_MODE(data_rate); in rtw89_core_rx_ppdu_match()
1318 rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); in rtw89_core_rx_ppdu_match()
1321 rate_idx = GET_DATA_RATE_HT_IDX(data_rate); in rtw89_core_rx_ppdu_match()
1323 rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); in rtw89_core_rx_ppdu_match()
[all …]
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| /drivers/staging/rtl8723bs/hal/ |
| D | rtl8723bs_recv.c | 64 pattrib->data_rate = (u8)prxreport->rx_rate; in update_recvframe_attrib()
92 .data_rate = 0x00, in update_recvframe_phyinfo()
127 pkt_info.data_rate = pattrib->data_rate; in update_recvframe_phyinfo()
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| D | odm_HWConfig.c | 115 is_cck_rate = pkt_info->data_rate <= DESC_RATE11M; in odm_rx_phy_status_parsing()
276 isCCKrate = ((pPktinfo->data_rate <= DESC_RATE11M)) ? true : false; in odm_Process_RSSIForDM()
277 pDM_Odm->RxRate = pPktinfo->data_rate; in odm_Process_RSSIForDM()
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| D | hal_com.c | 985 HDATA_RATE(psample_pkt_rssi->data_rate), in rtw_get_raw_rssi_info()
988 isCCKrate = psample_pkt_rssi->data_rate <= DESC_RATE11M; in rtw_get_raw_rssi_info()
1015 isCCKrate = psample_pkt_rssi->data_rate <= DESC_RATE11M; in rtw_dump_raw_rssi_info()
1039 psample_pkt_rssi->data_rate = pattrib->data_rate; in rtw_store_phy_info()
1040 isCCKrate = pattrib->data_rate <= DESC_RATE11M; in rtw_store_phy_info()
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| /drivers/staging/rtl8192u/ieee80211/ |
| D | ieee80211_tx.c | 353 if (tcb_desc->data_rate == 2) {//// 1M can only use Long Preamble. 11B spec in ieee80211_qurey_ShortPreambleMode()
394 if ((tcb_desc->data_rate & 0x80) == 0) // If using legacy rate, it shall use 20MHz channel. in ieee80211_query_BandwidthMode()
806 tcb_desc->data_rate = ieee->basic_rate; in ieee80211_xmit()
808 tcb_desc->data_rate = CURRENT_RATE(ieee->mode, ieee->rate, ieee->HTCurrentOperaRate); in ieee80211_xmit()
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| /drivers/input/misc/ |
| D | adxl34x.c | 224 .data_rate = 8,
535 return sprintf(buf, "%u\n", RATE(ac->pdata.data_rate)); in adxl34x_rate_show()
552 ac->pdata.data_rate = RATE(val); in adxl34x_rate_store()
554 ac->pdata.data_rate | in adxl34x_rate_store()
845 AC_WRITE(ac, BW_RATE, RATE(ac->pdata.data_rate) | in adxl34x_probe()
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| /drivers/gpu/drm/kmb/ |
| D | kmb_dsi.c | 1358 u64 data_rate; in kmb_dsi_mode_set() local
1381 data_rate = ((((u32)mode->crtc_vtotal * (u32)mode->crtc_htotal) * in kmb_dsi_mode_set()
1386 (u32)data_rate, mipi_tx_init_cfg.active_lanes); in kmb_dsi_mode_set()
1391 if (data_rate < 800) { in kmb_dsi_mode_set()
1393 mipi_tx_init_cfg.lane_rate_mbps = data_rate * 2; in kmb_dsi_mode_set()
1395 mipi_tx_init_cfg.lane_rate_mbps = data_rate; in kmb_dsi_mode_set()
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| /drivers/staging/rtl8723bs/include/ |
| D | rtw_recv.h | 106 u8 data_rate; member
155 u8 data_rate; member
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| /drivers/tty/ |
| D | synclink_gt.c | 337 .data_rate = 9600,
440 static void set_rate(struct slgt_info *info, u32 data_rate);
844 if (info->params.data_rate) { in wait_until_sent()
1080 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate; in get_params32()
1110 info->params.data_rate = tmp_params.data_rate; in set_params32()
2475 info->params.data_rate = tty_get_baud_rate(info->port.tty); in change_params()
2477 if (info->params.data_rate) { in change_params()
2479 info->params.data_rate; in change_params()
4140 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && in async_mode()
4141 ((info->base_clock < (info->params.data_rate * 16)) || in async_mode()
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| /drivers/staging/r8188eu/hal/ |
| D | rtl8188eu_xmit.c | 154 u8 data_rate, pwr_status, offset; in update_txdesc() local
229 data_rate = ODM_RA_GetDecisionRate_8188E(&haldata->odmpriv, pattrib->mac_id); in update_txdesc()
230 ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F); in update_txdesc()
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| /drivers/phy/freescale/ |
| D | phy-fsl-imx8-mipi-dphy.c | 386 unsigned long data_rate; in mixel_dphy_configure_lvds_phy() local
416 data_rate = 7 * lvds_opts->differential_clk_rate; in mixel_dphy_configure_lvds_phy()
418 fvco = data_rate * co; in mixel_dphy_configure_lvds_phy()
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