| /drivers/gpu/drm/amd/display/include/ |
| D | logger_interface.h | 83 (void)(dc_ctx); \
89 (void)(dc_ctx); \
128 dm_dtn_log_begin(dc_ctx, log_ctx)
131 dm_dtn_log_append_v(dc_ctx, log_ctx, msg, ##__VA_ARGS__)
134 dm_dtn_log_end(dc_ctx, log_ctx)
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 864 struct dc_context *dc_ctx; in dc_construct_ctx() local
867 dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL); in dc_construct_ctx()
868 if (!dc_ctx) in dc_construct_ctx()
871 dc_ctx->cgs_device = init_params->cgs_device; in dc_construct_ctx()
872 dc_ctx->driver_context = init_params->driver; in dc_construct_ctx()
873 dc_ctx->dc = dc; in dc_construct_ctx()
874 dc_ctx->asic_id = init_params->asic_id; in dc_construct_ctx()
875 dc_ctx->dc_sink_id_count = 0; in dc_construct_ctx()
876 dc_ctx->dc_stream_id_count = 0; in dc_construct_ctx()
877 dc_ctx->dce_environment = init_params->dce_environment; in dc_construct_ctx()
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| D | dc_link.c | 1013 struct dc_context *dc_ctx = link->ctx; in detect_link_and_local_sink() local
1014 struct dc *dc = dc_ctx->dc; in detect_link_and_local_sink()
1097 dc_ctx->dce_version == DCN_VERSION_3_01 && in detect_link_and_local_sink()
1319 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults) in detect_link_and_local_sink()
1320 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config); in detect_link_and_local_sink()
1322 dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink); in detect_link_and_local_sink()
1324 dm_helpers_override_panel_settings(dc_ctx, &link->panel_config); in detect_link_and_local_sink()
1549 struct dc_context *dc_ctx = init_params->ctx; in dc_link_construct_legacy() local
1557 DC_LOGGER_INIT(dc_ctx->logger); in dc_link_construct_legacy()
1569 link->ctx = dc_ctx; in dc_link_construct_legacy()
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| D | dc_resource.c | 2209 struct dc_context *dc_ctx = dc->ctx; in dc_remove_stream_from_ctx() local
2482 struct dc_context *dc_ctx = dc->ctx; in resource_map_pool_resources() local
2552 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version); in resource_map_pool_resources()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_dmub_srv.c | 72 struct dc_context *dc_ctx = dc_dmub_srv->ctx; in dc_dmub_srv_cmd_queue() local
99 struct dc_context *dc_ctx = dc_dmub_srv->ctx; in dc_dmub_srv_cmd_execute() local
112 struct dc_context *dc_ctx = dc_dmub_srv->ctx; in dc_dmub_srv_wait_idle() local
125 struct dc_context *dc_ctx = dmub_srv->ctx; in dc_dmub_srv_clear_inbox0_ack() local
138 struct dc_context *dc_ctx = dmub_srv->ctx; in dc_dmub_srv_wait_for_inbox0_ack() local
152 struct dc_context *dc_ctx = dmub_srv->ctx; in dc_dmub_srv_send_inbox0_cmd() local
184 struct dc_context *dc_ctx = dc_dmub_srv->ctx; in dc_dmub_srv_wait_phy_init() local
227 struct dc_context *dc_ctx; in dc_dmub_srv_is_restore_required() local
235 dc_ctx = dc_dmub_srv->ctx; in dc_dmub_srv_is_restore_required()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer_debug.c | 73 struct dc_context *dc_ctx = dc->ctx; in dcn10_get_hubbub_state() local
80 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubbub_state()
111 struct dc_context *dc_ctx = dc->ctx; in dcn10_get_hubp_states() local
118 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubp_states()
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| D | dcn10_hw_sequencer.c | 75 print_microsec(dc_ctx, log_ctx, ref_cycle)
82 static void print_microsec(struct dc_context *dc_ctx, in print_microsec() argument
86 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
127 struct dc_context *dc_ctx = dc->ctx; in log_mpc_crc() local
141 struct dc_context *dc_ctx = dc->ctx; in dcn10_log_hubbub_state() local
169 struct dc_context *dc_ctx = dc->ctx; in dcn10_log_hubp_states() local
284 struct dc_context *dc_ctx = dc->ctx; in dcn10_log_hw_state() local
2006 struct dc_context *dc_ctx, in wait_for_reset_trigger_to_occur() argument
2125 struct dc_context *dc_ctx = dc->ctx; in dcn10_align_pixel_clocks() local
2216 struct dc_context *dc_ctx = dc->ctx; in dcn10_enable_vblanks_synchronization() local
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.h | 162 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_s…
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| D | dcn20_resource.c | 1375 struct dc_state *dc_ctx, in dcn20_add_dsc_to_stream_resource() argument
1383 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; in dcn20_add_dsc_to_stream_resource()
1391 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i); in dcn20_add_dsc_to_stream_resource()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_dio_link_encoder.c | 424 static bool link_dpia_control(struct dc_context *dc_ctx, in link_dpia_control() argument
428 struct dc_dmub_srv *dmub = dc_ctx->dmub_srv; in link_dpia_control()
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| /drivers/gpu/drm/amd/display/dc/irq/dce110/ |
| D | irq_service_dce110.c | 206 struct dc_context *dc_ctx = irq_service->ctx; in dce110_vblank_set() local
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 2463 struct dc_context *dc_ctx, in wait_for_reset_trigger_to_occur() argument
2506 struct dc_context *dc_ctx = dc->ctx; in dce110_enable_timing_synchronization() local
2532 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); in dce110_enable_timing_synchronization()
2551 struct dc_context *dc_ctx = dc->ctx; in dce110_enable_per_frame_crtc_position_reset() local
2572 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); in dce110_enable_per_frame_crtc_position_reset()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm.c | 2688 struct dc_context *dc_ctx = link->ctx; in emulated_link_detect() local
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