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Searched refs:dct (Results 1 – 11 of 11) sorted by relevance

/drivers/infiniband/hw/mlx5/
Dqpc.c13 struct mlx5_core_dct *dct);
96 struct mlx5_core_dct *dct; in rsc_event_notifier() local
105 rsn = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff; in rsc_event_notifier()
140 dct = (struct mlx5_core_dct *)common; in rsc_event_notifier()
142 complete(&dct->drained); in rsc_event_notifier()
190 struct mlx5_core_dct *dct, bool need_cleanup) in _mlx5_core_destroy_dct() argument
193 struct mlx5_core_qp *qp = &dct->mqp; in _mlx5_core_destroy_dct()
196 err = mlx5_core_drain_dct(dev, dct); in _mlx5_core_destroy_dct()
203 wait_for_completion(&dct->drained); in _mlx5_core_destroy_dct()
206 destroy_resource_common(dev, &dct->mqp); in _mlx5_core_destroy_dct()
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Dqp.h21 int mlx5_core_destroy_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct);
24 int mlx5_core_dct_query(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct,
Dqp.c2656 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); in create_dct()
2657 if (!qp->dct.in) in create_dct()
2660 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); in create_dct()
2661 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); in create_dct()
2684 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) in check_qp_type()
3110 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); in mlx5_ib_destroy_dct()
3117 kfree(mqp->dct.in); in mlx5_ib_destroy_dct()
4423 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); in mlx5_ib_modify_dct()
4496 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, in mlx5_ib_modify_dct()
4499 err = mlx5_cmd_check(dev->mdev, err, qp->dct.in, out); in mlx5_ib_modify_dct()
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Ddevx.c653 qp->dct.mdct.mqp.qpn) == obj_id; in devx_is_valid_obj_id()
2437 obj_id = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff; in devx_get_obj_id_from_event()
Dmlx5_ib.h494 struct mlx5_ib_dct dct; member
/drivers/edac/
Damd64_edac.c104 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument
110 reg |= dct; in f15h_select_dct()
128 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument
133 if (dct || offset >= 0x100) in amd64_read_dct_pci_cfg()
138 if (dct) { in amd64_read_dct_pci_cfg()
156 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
157 f15h_select_dct(pvt, dct); in amd64_read_dct_pci_cfg()
161 if (dct) in amd64_read_dct_pci_cfg()
400 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, in get_cs_base_and_mask() argument
407 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
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Damd64_edac.h182 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) argument
183 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE) argument
490 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct,
/drivers/soc/fsl/dpio/
Dqbman-portal.h215 enum qbman_pull_type_e dct);
217 enum qbman_pull_type_e dct);
Dqbman-portal.c1068 enum qbman_pull_type_e dct) in qbman_pull_desc_set_wq() argument
1070 d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT; in qbman_pull_desc_set_wq()
1083 enum qbman_pull_type_e dct) in qbman_pull_desc_set_channel() argument
1085 d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT; in qbman_pull_desc_set_channel()
/drivers/net/ethernet/mellanox/mlx5/core/
Dmain.c593 if (MLX5_CAP_GEN_MAX(dev, dct)) in handle_hca_cap()
594 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); in handle_hca_cap()
Deq.c559 if (MLX5_CAP_GEN_MAX(dev, dct)) in gather_async_events_mask()