| /drivers/clk/ |
| D | clk-vt8500.c | 456 int div1, div2; in wm8750_find_pll_bits() local
463 for (div2 = 7; div2 >= 0; div2--) in wm8750_find_pll_bits()
465 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); in wm8750_find_pll_bits()
474 *divisor2 = div2; in wm8750_find_pll_bits()
482 *divisor2 = div2; in wm8750_find_pll_bits()
504 int div1, div2; in wm8850_find_pll_bits() local
511 for (div2 = 3; div2 >= 0; div2--) in wm8850_find_pll_bits()
514 ((div1 + 1) * (1 << div2)); in wm8850_find_pll_bits()
522 *divisor2 = div2; in wm8850_find_pll_bits()
530 *divisor2 = div2; in wm8850_find_pll_bits()
[all …]
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| /drivers/clk/uniphier/ |
| D | clk-uniphier.h | 114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \ argument
116 UNIPHIER_CLK_DIV(parent, div2)
118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ argument
120 UNIPHIER_CLK_DIV2(parent, div2, div3)
122 #define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \ argument
123 UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3), \
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| /drivers/clk/tegra/ |
| D | clk-tegra-super-cclk.c | 54 unsigned int div2; in cclk_super_recalc_rate() local
58 div2 = 1; in cclk_super_recalc_rate()
60 div2 = 0; in cclk_super_recalc_rate()
63 return parent_rate >> div2; in cclk_super_recalc_rate()
65 return tegra_clk_super_ops.recalc_rate(hw, parent_rate) >> div2; in cclk_super_recalc_rate()
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| /drivers/clk/imx/ |
| D | clk-composite-8m.c | 54 int div1, div2; in imx8m_clk_composite_compute_dividers() local
62 for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) { in imx8m_clk_composite_compute_dividers()
63 int new_error = ((parent_rate / div1) / div2) - rate; in imx8m_clk_composite_compute_dividers()
67 *postdiv = div2; in imx8m_clk_composite_compute_dividers()
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | ga102.c | 88 u32 div2 = 0; in ga102_sor_clock() local
92 div2 = 1; in ga102_sor_clock()
96 nvkm_wr32(device, 0x00ec04 + (sor->id * 0x10), div2); in ga102_sor_clock()
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| D | gf119.c | 268 u32 div2 = sor->asy.link == 3; in gf119_sor_clock() local
274 div2 = 1; in gf119_sor_clock()
277 nvkm_mask(device, 0x612300 + soff, 0x00000707, (div2 << 8) | div1); in gf119_sor_clock()
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| /drivers/media/tuners/ |
| D | mt2131.c | 89 u32 div1, num1, div2, num2; in mt2131_set_params() local
111 div2 = num2 / 8192; in mt2131_set_params()
140 b[6] = div2; in mt2131_set_params()
146 (int)div1, (int)num1, (int)div2, (int)num2); in mt2131_set_params()
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| D | mt2060.c | 196 u32 div1,num1,div2,num2; in mt2060_set_params() local
233 div2 = num2 / 8192; in mt2060_set_params()
252 b[5] = ((num2 >>12) & 1) | (div2 << 1); in mt2060_set_params()
256 dprintk("PLL div1=%d num1=%d div2=%d num2=%d",(int)div1,(int)num1,(int)div2,(int)num2); in mt2060_set_params()
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| /drivers/spi/ |
| D | spi-omap-uwire.c | 315 int div2; in uwire_setup_transfer() local
372 div2 = (rate / div1 + hz - 1) / hz; in uwire_setup_transfer()
373 if (div2 <= 8) in uwire_setup_transfer()
391 switch (div2) { in uwire_setup_transfer()
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| /drivers/comedi/drivers/ |
| D | adl_pci9118.c | 532 unsigned int *div1, unsigned int *div2, in pci9118_calc_divisors() argument
539 *div2 = *tim1 / pacer->osc_base; /* scan timer */ in pci9118_calc_divisors()
540 *div2 = *div2 / *div1; /* major timer is c1*c2 */ in pci9118_calc_divisors()
541 if (*div2 < chans) in pci9118_calc_divisors()
542 *div2 = chans; in pci9118_calc_divisors()
548 if (*div2 < (chans + 2)) in pci9118_calc_divisors()
549 *div2 = chans + 2; in pci9118_calc_divisors()
552 *tim1 = *div1 * *div2 * pacer->osc_base; in pci9118_calc_divisors()
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| /drivers/video/fbdev/ |
| D | cyber2000fb.c | 666 u_int div2, t_div1, best_div1, best_mult; in cyber2000fb_decode_clock() local
675 for (div2 = 0; div2 < 4; div2++) { in cyber2000fb_decode_clock()
678 new_pll = pll_ps / cfb->divisors[div2]; in cyber2000fb_decode_clock()
685 if (div2 == 4) in cyber2000fb_decode_clock()
741 hw->clock_div = div2 << 6 | (best_div1 - 1); in cyber2000fb_decode_clock()
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| D | amifb.c | 545 #define div2(v) ((v)>>1) macro
1028 #define vsstrt2hw(vsstrt) (div2(vsstrt))
1029 #define vsstop2hw(vsstop) (div2(vsstop))
1030 #define vtotal2hw(vtotal) (div2(vtotal) - 1)
1037 #define vbstrt2hw(vbstrt) (div2(vbstrt))
1038 #define vbstop2hw(vbstop) (div2(vbstop))
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| /drivers/media/dvb-frontends/ |
| D | stb0899_algo.c | 1274 int div1, div2, rem1, rem2; in stb0899_dvbs2_get_srate() local
1277 div2 = config->btr_nco_bits - div1 - 1; in stb0899_dvbs2_get_srate()
1286 intval2 = bTrNomFreq / (1 << div2); in stb0899_dvbs2_get_srate()
1289 rem2 = bTrNomFreq % (1 << div2); in stb0899_dvbs2_get_srate()
1291 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1)); in stb0899_dvbs2_get_srate()
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| /drivers/clk/pxa/ |
| D | clk-pxa.h | 140 unsigned int div2; member
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| D | clk-pxa.c | 185 if (freq->div2) { in pxa2xx_cpll_change()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.c | 2801 int div2; in icl_mg_pll_find_divisors() local
2809 for (div2 = 10; div2 > 0; div2--) { in icl_mg_pll_find_divisors()
2810 int dco = div1 * div2 * clock_khz * 5; in icl_mg_pll_find_divisors()
2817 if (div2 >= 2) { in icl_mg_pll_find_divisors()
2860 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2); in icl_mg_pll_find_divisors()
3080 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; in icl_ddi_mg_pll_get_freq() local
3129 div2 = (pll_state->mg_clktop2_hsclkctl & in icl_ddi_mg_pll_get_freq()
3134 if (div2 == 0) in icl_ddi_mg_pll_get_freq()
3135 div2 = 1; in icl_ddi_mg_pll_get_freq()
3143 tmp = div_u64(tmp, 5 * div1 * div2); in icl_ddi_mg_pll_get_freq()
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| /drivers/iio/adc/ |
| D | at91-sama5d2_adc.c | 1870 u64 div1, div2; in at91_adc_read_temp() local
1915 div2 = DIV_ROUND_CLOSEST_ULL((u64)clb->p4, AT91_ADC_TS_VTEMP_DT); in at91_adc_read_temp()
1916 div2 *= 1000; in at91_adc_read_temp()
1917 *val = clb->p1 + (int)div1 - (int)div2; in at91_adc_read_temp()
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