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/drivers/clk/at91/
Dclk-sam9x60-pll.c445 u32 divid; in sam9x60_div_pll_compute_div() local
454 for (divid = 1; divid < core->layout->div_mask; divid++) { in sam9x60_div_pll_compute_div()
455 tmp_parent_rate = clk_hw_round_rate(parent, rate * divid); in sam9x60_div_pll_compute_div()
459 tmp_rate = DIV_ROUND_CLOSEST_ULL(tmp_parent_rate, divid); in sam9x60_div_pll_compute_div()