1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2006, Intel Corporation.
4 *
5 * Copyright (C) 2006-2008 Intel Corporation
6 * Author: Ashok Raj <ashok.raj@intel.com>
7 * Author: Shaohua Li <shaohua.li@intel.com>
8 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
9 *
10 * This file implements early detection/parsing of Remapping Devices
11 * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
12 * tables.
13 *
14 * These routines are used by both DMA-remapping and Interrupt-remapping
15 */
16
17 #define pr_fmt(fmt) "DMAR: " fmt
18
19 #include <linux/pci.h>
20 #include <linux/dmar.h>
21 #include <linux/iova.h>
22 #include <linux/timer.h>
23 #include <linux/irq.h>
24 #include <linux/interrupt.h>
25 #include <linux/tboot.h>
26 #include <linux/dmi.h>
27 #include <linux/slab.h>
28 #include <linux/iommu.h>
29 #include <linux/numa.h>
30 #include <linux/limits.h>
31 #include <asm/irq_remapping.h>
32
33 #include "iommu.h"
34 #include "../irq_remapping.h"
35 #include "perf.h"
36 #include "trace.h"
37
38 typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);
39 struct dmar_res_callback {
40 dmar_res_handler_t cb[ACPI_DMAR_TYPE_RESERVED];
41 void *arg[ACPI_DMAR_TYPE_RESERVED];
42 bool ignore_unhandled;
43 bool print_entry;
44 };
45
46 /*
47 * Assumptions:
48 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
49 * before IO devices managed by that unit.
50 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
51 * after IO devices managed by that unit.
52 * 3) Hotplug events are rare.
53 *
54 * Locking rules for DMA and interrupt remapping related global data structures:
55 * 1) Use dmar_global_lock in process context
56 * 2) Use RCU in interrupt context
57 */
58 DECLARE_RWSEM(dmar_global_lock);
59 LIST_HEAD(dmar_drhd_units);
60
61 struct acpi_table_header * __initdata dmar_tbl;
62 static int dmar_dev_scope_status = 1;
63 static DEFINE_IDA(dmar_seq_ids);
64
65 static int alloc_iommu(struct dmar_drhd_unit *drhd);
66 static void free_iommu(struct intel_iommu *iommu);
67
dmar_register_drhd_unit(struct dmar_drhd_unit * drhd)68 static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
69 {
70 /*
71 * add INCLUDE_ALL at the tail, so scan the list will find it at
72 * the very end.
73 */
74 if (drhd->include_all)
75 list_add_tail_rcu(&drhd->list, &dmar_drhd_units);
76 else
77 list_add_rcu(&drhd->list, &dmar_drhd_units);
78 }
79
dmar_alloc_dev_scope(void * start,void * end,int * cnt)80 void *dmar_alloc_dev_scope(void *start, void *end, int *cnt)
81 {
82 struct acpi_dmar_device_scope *scope;
83
84 *cnt = 0;
85 while (start < end) {
86 scope = start;
87 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE ||
88 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
89 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
90 (*cnt)++;
91 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC &&
92 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) {
93 pr_warn("Unsupported device scope\n");
94 }
95 start += scope->length;
96 }
97 if (*cnt == 0)
98 return NULL;
99
100 return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL);
101 }
102
dmar_free_dev_scope(struct dmar_dev_scope ** devices,int * cnt)103 void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt)
104 {
105 int i;
106 struct device *tmp_dev;
107
108 if (*devices && *cnt) {
109 for_each_active_dev_scope(*devices, *cnt, i, tmp_dev)
110 put_device(tmp_dev);
111 kfree(*devices);
112 }
113
114 *devices = NULL;
115 *cnt = 0;
116 }
117
118 /* Optimize out kzalloc()/kfree() for normal cases */
119 static char dmar_pci_notify_info_buf[64];
120
121 static struct dmar_pci_notify_info *
dmar_alloc_pci_notify_info(struct pci_dev * dev,unsigned long event)122 dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event)
123 {
124 int level = 0;
125 size_t size;
126 struct pci_dev *tmp;
127 struct dmar_pci_notify_info *info;
128
129 BUG_ON(dev->is_virtfn);
130
131 /*
132 * Ignore devices that have a domain number higher than what can
133 * be looked up in DMAR, e.g. VMD subdevices with domain 0x10000
134 */
135 if (pci_domain_nr(dev->bus) > U16_MAX)
136 return NULL;
137
138 /* Only generate path[] for device addition event */
139 if (event == BUS_NOTIFY_ADD_DEVICE)
140 for (tmp = dev; tmp; tmp = tmp->bus->self)
141 level++;
142
143 size = struct_size(info, path, level);
144 if (size <= sizeof(dmar_pci_notify_info_buf)) {
145 info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf;
146 } else {
147 info = kzalloc(size, GFP_KERNEL);
148 if (!info) {
149 if (dmar_dev_scope_status == 0)
150 dmar_dev_scope_status = -ENOMEM;
151 return NULL;
152 }
153 }
154
155 info->event = event;
156 info->dev = dev;
157 info->seg = pci_domain_nr(dev->bus);
158 info->level = level;
159 if (event == BUS_NOTIFY_ADD_DEVICE) {
160 for (tmp = dev; tmp; tmp = tmp->bus->self) {
161 level--;
162 info->path[level].bus = tmp->bus->number;
163 info->path[level].device = PCI_SLOT(tmp->devfn);
164 info->path[level].function = PCI_FUNC(tmp->devfn);
165 if (pci_is_root_bus(tmp->bus))
166 info->bus = tmp->bus->number;
167 }
168 }
169
170 return info;
171 }
172
dmar_free_pci_notify_info(struct dmar_pci_notify_info * info)173 static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info)
174 {
175 if ((void *)info != dmar_pci_notify_info_buf)
176 kfree(info);
177 }
178
dmar_match_pci_path(struct dmar_pci_notify_info * info,int bus,struct acpi_dmar_pci_path * path,int count)179 static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus,
180 struct acpi_dmar_pci_path *path, int count)
181 {
182 int i;
183
184 if (info->bus != bus)
185 goto fallback;
186 if (info->level != count)
187 goto fallback;
188
189 for (i = 0; i < count; i++) {
190 if (path[i].device != info->path[i].device ||
191 path[i].function != info->path[i].function)
192 goto fallback;
193 }
194
195 return true;
196
197 fallback:
198
199 if (count != 1)
200 return false;
201
202 i = info->level - 1;
203 if (bus == info->path[i].bus &&
204 path[0].device == info->path[i].device &&
205 path[0].function == info->path[i].function) {
206 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n",
207 bus, path[0].device, path[0].function);
208 return true;
209 }
210
211 return false;
212 }
213
214 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
dmar_insert_dev_scope(struct dmar_pci_notify_info * info,void * start,void * end,u16 segment,struct dmar_dev_scope * devices,int devices_cnt)215 int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
216 void *start, void*end, u16 segment,
217 struct dmar_dev_scope *devices,
218 int devices_cnt)
219 {
220 int i, level;
221 struct device *tmp, *dev = &info->dev->dev;
222 struct acpi_dmar_device_scope *scope;
223 struct acpi_dmar_pci_path *path;
224
225 if (segment != info->seg)
226 return 0;
227
228 for (; start < end; start += scope->length) {
229 scope = start;
230 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
231 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
232 continue;
233
234 path = (struct acpi_dmar_pci_path *)(scope + 1);
235 level = (scope->length - sizeof(*scope)) / sizeof(*path);
236 if (!dmar_match_pci_path(info, scope->bus, path, level))
237 continue;
238
239 /*
240 * We expect devices with endpoint scope to have normal PCI
241 * headers, and devices with bridge scope to have bridge PCI
242 * headers. However PCI NTB devices may be listed in the
243 * DMAR table with bridge scope, even though they have a
244 * normal PCI header. NTB devices are identified by class
245 * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch
246 * for this special case.
247 */
248 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
249 info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) ||
250 (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE &&
251 (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
252 info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) {
253 pr_warn("Device scope type does not match for %s\n",
254 pci_name(info->dev));
255 return -EINVAL;
256 }
257
258 for_each_dev_scope(devices, devices_cnt, i, tmp)
259 if (tmp == NULL) {
260 devices[i].bus = info->dev->bus->number;
261 devices[i].devfn = info->dev->devfn;
262 rcu_assign_pointer(devices[i].dev,
263 get_device(dev));
264 return 1;
265 }
266 BUG_ON(i >= devices_cnt);
267 }
268
269 return 0;
270 }
271
dmar_remove_dev_scope(struct dmar_pci_notify_info * info,u16 segment,struct dmar_dev_scope * devices,int count)272 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment,
273 struct dmar_dev_scope *devices, int count)
274 {
275 int index;
276 struct device *tmp;
277
278 if (info->seg != segment)
279 return 0;
280
281 for_each_active_dev_scope(devices, count, index, tmp)
282 if (tmp == &info->dev->dev) {
283 RCU_INIT_POINTER(devices[index].dev, NULL);
284 synchronize_rcu();
285 put_device(tmp);
286 return 1;
287 }
288
289 return 0;
290 }
291
dmar_pci_bus_add_dev(struct dmar_pci_notify_info * info)292 static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info)
293 {
294 int ret = 0;
295 struct dmar_drhd_unit *dmaru;
296 struct acpi_dmar_hardware_unit *drhd;
297
298 for_each_drhd_unit(dmaru) {
299 if (dmaru->include_all)
300 continue;
301
302 drhd = container_of(dmaru->hdr,
303 struct acpi_dmar_hardware_unit, header);
304 ret = dmar_insert_dev_scope(info, (void *)(drhd + 1),
305 ((void *)drhd) + drhd->header.length,
306 dmaru->segment,
307 dmaru->devices, dmaru->devices_cnt);
308 if (ret)
309 break;
310 }
311 if (ret >= 0)
312 ret = dmar_iommu_notify_scope_dev(info);
313 if (ret < 0 && dmar_dev_scope_status == 0)
314 dmar_dev_scope_status = ret;
315
316 if (ret >= 0)
317 intel_irq_remap_add_device(info);
318
319 return ret;
320 }
321
dmar_pci_bus_del_dev(struct dmar_pci_notify_info * info)322 static void dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info)
323 {
324 struct dmar_drhd_unit *dmaru;
325
326 for_each_drhd_unit(dmaru)
327 if (dmar_remove_dev_scope(info, dmaru->segment,
328 dmaru->devices, dmaru->devices_cnt))
329 break;
330 dmar_iommu_notify_scope_dev(info);
331 }
332
vf_inherit_msi_domain(struct pci_dev * pdev)333 static inline void vf_inherit_msi_domain(struct pci_dev *pdev)
334 {
335 struct pci_dev *physfn = pci_physfn(pdev);
336
337 dev_set_msi_domain(&pdev->dev, dev_get_msi_domain(&physfn->dev));
338 }
339
dmar_pci_bus_notifier(struct notifier_block * nb,unsigned long action,void * data)340 static int dmar_pci_bus_notifier(struct notifier_block *nb,
341 unsigned long action, void *data)
342 {
343 struct pci_dev *pdev = to_pci_dev(data);
344 struct dmar_pci_notify_info *info;
345
346 /* Only care about add/remove events for physical functions.
347 * For VFs we actually do the lookup based on the corresponding
348 * PF in device_to_iommu() anyway. */
349 if (pdev->is_virtfn) {
350 /*
351 * Ensure that the VF device inherits the irq domain of the
352 * PF device. Ideally the device would inherit the domain
353 * from the bus, but DMAR can have multiple units per bus
354 * which makes this impossible. The VF 'bus' could inherit
355 * from the PF device, but that's yet another x86'sism to
356 * inflict on everybody else.
357 */
358 if (action == BUS_NOTIFY_ADD_DEVICE)
359 vf_inherit_msi_domain(pdev);
360 return NOTIFY_DONE;
361 }
362
363 if (action != BUS_NOTIFY_ADD_DEVICE &&
364 action != BUS_NOTIFY_REMOVED_DEVICE)
365 return NOTIFY_DONE;
366
367 info = dmar_alloc_pci_notify_info(pdev, action);
368 if (!info)
369 return NOTIFY_DONE;
370
371 down_write(&dmar_global_lock);
372 if (action == BUS_NOTIFY_ADD_DEVICE)
373 dmar_pci_bus_add_dev(info);
374 else if (action == BUS_NOTIFY_REMOVED_DEVICE)
375 dmar_pci_bus_del_dev(info);
376 up_write(&dmar_global_lock);
377
378 dmar_free_pci_notify_info(info);
379
380 return NOTIFY_OK;
381 }
382
383 static struct notifier_block dmar_pci_bus_nb = {
384 .notifier_call = dmar_pci_bus_notifier,
385 .priority = 1,
386 };
387
388 static struct dmar_drhd_unit *
dmar_find_dmaru(struct acpi_dmar_hardware_unit * drhd)389 dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd)
390 {
391 struct dmar_drhd_unit *dmaru;
392
393 list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list,
394 dmar_rcu_check())
395 if (dmaru->segment == drhd->segment &&
396 dmaru->reg_base_addr == drhd->address)
397 return dmaru;
398
399 return NULL;
400 }
401
402 /*
403 * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
404 * structure which uniquely represent one DMA remapping hardware unit
405 * present in the platform
406 */
dmar_parse_one_drhd(struct acpi_dmar_header * header,void * arg)407 static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg)
408 {
409 struct acpi_dmar_hardware_unit *drhd;
410 struct dmar_drhd_unit *dmaru;
411 int ret;
412
413 drhd = (struct acpi_dmar_hardware_unit *)header;
414 dmaru = dmar_find_dmaru(drhd);
415 if (dmaru)
416 goto out;
417
418 dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL);
419 if (!dmaru)
420 return -ENOMEM;
421
422 /*
423 * If header is allocated from slab by ACPI _DSM method, we need to
424 * copy the content because the memory buffer will be freed on return.
425 */
426 dmaru->hdr = (void *)(dmaru + 1);
427 memcpy(dmaru->hdr, header, header->length);
428 dmaru->reg_base_addr = drhd->address;
429 dmaru->segment = drhd->segment;
430 dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
431 dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1),
432 ((void *)drhd) + drhd->header.length,
433 &dmaru->devices_cnt);
434 if (dmaru->devices_cnt && dmaru->devices == NULL) {
435 kfree(dmaru);
436 return -ENOMEM;
437 }
438
439 ret = alloc_iommu(dmaru);
440 if (ret) {
441 dmar_free_dev_scope(&dmaru->devices,
442 &dmaru->devices_cnt);
443 kfree(dmaru);
444 return ret;
445 }
446 dmar_register_drhd_unit(dmaru);
447
448 out:
449 if (arg)
450 (*(int *)arg)++;
451
452 return 0;
453 }
454
dmar_free_drhd(struct dmar_drhd_unit * dmaru)455 static void dmar_free_drhd(struct dmar_drhd_unit *dmaru)
456 {
457 if (dmaru->devices && dmaru->devices_cnt)
458 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt);
459 if (dmaru->iommu)
460 free_iommu(dmaru->iommu);
461 kfree(dmaru);
462 }
463
dmar_parse_one_andd(struct acpi_dmar_header * header,void * arg)464 static int __init dmar_parse_one_andd(struct acpi_dmar_header *header,
465 void *arg)
466 {
467 struct acpi_dmar_andd *andd = (void *)header;
468
469 /* Check for NUL termination within the designated length */
470 if (strnlen(andd->device_name, header->length - 8) == header->length - 8) {
471 pr_warn(FW_BUG
472 "Your BIOS is broken; ANDD object name is not NUL-terminated\n"
473 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
474 dmi_get_system_info(DMI_BIOS_VENDOR),
475 dmi_get_system_info(DMI_BIOS_VERSION),
476 dmi_get_system_info(DMI_PRODUCT_VERSION));
477 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
478 return -EINVAL;
479 }
480 pr_info("ANDD device: %x name: %s\n", andd->device_number,
481 andd->device_name);
482
483 return 0;
484 }
485
486 #ifdef CONFIG_ACPI_NUMA
dmar_parse_one_rhsa(struct acpi_dmar_header * header,void * arg)487 static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg)
488 {
489 struct acpi_dmar_rhsa *rhsa;
490 struct dmar_drhd_unit *drhd;
491
492 rhsa = (struct acpi_dmar_rhsa *)header;
493 for_each_drhd_unit(drhd) {
494 if (drhd->reg_base_addr == rhsa->base_address) {
495 int node = pxm_to_node(rhsa->proximity_domain);
496
497 if (node != NUMA_NO_NODE && !node_online(node))
498 node = NUMA_NO_NODE;
499 drhd->iommu->node = node;
500 return 0;
501 }
502 }
503 pr_warn(FW_BUG
504 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n"
505 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
506 rhsa->base_address,
507 dmi_get_system_info(DMI_BIOS_VENDOR),
508 dmi_get_system_info(DMI_BIOS_VERSION),
509 dmi_get_system_info(DMI_PRODUCT_VERSION));
510 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
511
512 return 0;
513 }
514 #else
515 #define dmar_parse_one_rhsa dmar_res_noop
516 #endif
517
518 static void
dmar_table_print_dmar_entry(struct acpi_dmar_header * header)519 dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
520 {
521 struct acpi_dmar_hardware_unit *drhd;
522 struct acpi_dmar_reserved_memory *rmrr;
523 struct acpi_dmar_atsr *atsr;
524 struct acpi_dmar_rhsa *rhsa;
525 struct acpi_dmar_satc *satc;
526
527 switch (header->type) {
528 case ACPI_DMAR_TYPE_HARDWARE_UNIT:
529 drhd = container_of(header, struct acpi_dmar_hardware_unit,
530 header);
531 pr_info("DRHD base: %#016Lx flags: %#x\n",
532 (unsigned long long)drhd->address, drhd->flags);
533 break;
534 case ACPI_DMAR_TYPE_RESERVED_MEMORY:
535 rmrr = container_of(header, struct acpi_dmar_reserved_memory,
536 header);
537 pr_info("RMRR base: %#016Lx end: %#016Lx\n",
538 (unsigned long long)rmrr->base_address,
539 (unsigned long long)rmrr->end_address);
540 break;
541 case ACPI_DMAR_TYPE_ROOT_ATS:
542 atsr = container_of(header, struct acpi_dmar_atsr, header);
543 pr_info("ATSR flags: %#x\n", atsr->flags);
544 break;
545 case ACPI_DMAR_TYPE_HARDWARE_AFFINITY:
546 rhsa = container_of(header, struct acpi_dmar_rhsa, header);
547 pr_info("RHSA base: %#016Lx proximity domain: %#x\n",
548 (unsigned long long)rhsa->base_address,
549 rhsa->proximity_domain);
550 break;
551 case ACPI_DMAR_TYPE_NAMESPACE:
552 /* We don't print this here because we need to sanity-check
553 it first. So print it in dmar_parse_one_andd() instead. */
554 break;
555 case ACPI_DMAR_TYPE_SATC:
556 satc = container_of(header, struct acpi_dmar_satc, header);
557 pr_info("SATC flags: 0x%x\n", satc->flags);
558 break;
559 }
560 }
561
562 /**
563 * dmar_table_detect - checks to see if the platform supports DMAR devices
564 */
dmar_table_detect(void)565 static int __init dmar_table_detect(void)
566 {
567 acpi_status status = AE_OK;
568
569 /* if we could find DMAR table, then there are DMAR devices */
570 status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
571
572 if (ACPI_SUCCESS(status) && !dmar_tbl) {
573 pr_warn("Unable to map DMAR\n");
574 status = AE_NOT_FOUND;
575 }
576
577 return ACPI_SUCCESS(status) ? 0 : -ENOENT;
578 }
579
dmar_walk_remapping_entries(struct acpi_dmar_header * start,size_t len,struct dmar_res_callback * cb)580 static int dmar_walk_remapping_entries(struct acpi_dmar_header *start,
581 size_t len, struct dmar_res_callback *cb)
582 {
583 struct acpi_dmar_header *iter, *next;
584 struct acpi_dmar_header *end = ((void *)start) + len;
585
586 for (iter = start; iter < end; iter = next) {
587 next = (void *)iter + iter->length;
588 if (iter->length == 0) {
589 /* Avoid looping forever on bad ACPI tables */
590 pr_debug(FW_BUG "Invalid 0-length structure\n");
591 break;
592 } else if (next > end) {
593 /* Avoid passing table end */
594 pr_warn(FW_BUG "Record passes table end\n");
595 return -EINVAL;
596 }
597
598 if (cb->print_entry)
599 dmar_table_print_dmar_entry(iter);
600
601 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) {
602 /* continue for forward compatibility */
603 pr_debug("Unknown DMAR structure type %d\n",
604 iter->type);
605 } else if (cb->cb[iter->type]) {
606 int ret;
607
608 ret = cb->cb[iter->type](iter, cb->arg[iter->type]);
609 if (ret)
610 return ret;
611 } else if (!cb->ignore_unhandled) {
612 pr_warn("No handler for DMAR structure type %d\n",
613 iter->type);
614 return -EINVAL;
615 }
616 }
617
618 return 0;
619 }
620
dmar_walk_dmar_table(struct acpi_table_dmar * dmar,struct dmar_res_callback * cb)621 static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar,
622 struct dmar_res_callback *cb)
623 {
624 return dmar_walk_remapping_entries((void *)(dmar + 1),
625 dmar->header.length - sizeof(*dmar), cb);
626 }
627
628 /**
629 * parse_dmar_table - parses the DMA reporting table
630 */
631 static int __init
parse_dmar_table(void)632 parse_dmar_table(void)
633 {
634 struct acpi_table_dmar *dmar;
635 int drhd_count = 0;
636 int ret;
637 struct dmar_res_callback cb = {
638 .print_entry = true,
639 .ignore_unhandled = true,
640 .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count,
641 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd,
642 .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr,
643 .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr,
644 .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa,
645 .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd,
646 .cb[ACPI_DMAR_TYPE_SATC] = &dmar_parse_one_satc,
647 };
648
649 /*
650 * Do it again, earlier dmar_tbl mapping could be mapped with
651 * fixed map.
652 */
653 dmar_table_detect();
654
655 /*
656 * ACPI tables may not be DMA protected by tboot, so use DMAR copy
657 * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
658 */
659 dmar_tbl = tboot_get_dmar_table(dmar_tbl);
660
661 dmar = (struct acpi_table_dmar *)dmar_tbl;
662 if (!dmar)
663 return -ENODEV;
664
665 if (dmar->width < PAGE_SHIFT - 1) {
666 pr_warn("Invalid DMAR haw\n");
667 return -EINVAL;
668 }
669
670 pr_info("Host address width %d\n", dmar->width + 1);
671 ret = dmar_walk_dmar_table(dmar, &cb);
672 if (ret == 0 && drhd_count == 0)
673 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n");
674
675 return ret;
676 }
677
dmar_pci_device_match(struct dmar_dev_scope devices[],int cnt,struct pci_dev * dev)678 static int dmar_pci_device_match(struct dmar_dev_scope devices[],
679 int cnt, struct pci_dev *dev)
680 {
681 int index;
682 struct device *tmp;
683
684 while (dev) {
685 for_each_active_dev_scope(devices, cnt, index, tmp)
686 if (dev_is_pci(tmp) && dev == to_pci_dev(tmp))
687 return 1;
688
689 /* Check our parent */
690 dev = dev->bus->self;
691 }
692
693 return 0;
694 }
695
696 struct dmar_drhd_unit *
dmar_find_matched_drhd_unit(struct pci_dev * dev)697 dmar_find_matched_drhd_unit(struct pci_dev *dev)
698 {
699 struct dmar_drhd_unit *dmaru;
700 struct acpi_dmar_hardware_unit *drhd;
701
702 dev = pci_physfn(dev);
703
704 rcu_read_lock();
705 for_each_drhd_unit(dmaru) {
706 drhd = container_of(dmaru->hdr,
707 struct acpi_dmar_hardware_unit,
708 header);
709
710 if (dmaru->include_all &&
711 drhd->segment == pci_domain_nr(dev->bus))
712 goto out;
713
714 if (dmar_pci_device_match(dmaru->devices,
715 dmaru->devices_cnt, dev))
716 goto out;
717 }
718 dmaru = NULL;
719 out:
720 rcu_read_unlock();
721
722 return dmaru;
723 }
724
dmar_acpi_insert_dev_scope(u8 device_number,struct acpi_device * adev)725 static void __init dmar_acpi_insert_dev_scope(u8 device_number,
726 struct acpi_device *adev)
727 {
728 struct dmar_drhd_unit *dmaru;
729 struct acpi_dmar_hardware_unit *drhd;
730 struct acpi_dmar_device_scope *scope;
731 struct device *tmp;
732 int i;
733 struct acpi_dmar_pci_path *path;
734
735 for_each_drhd_unit(dmaru) {
736 drhd = container_of(dmaru->hdr,
737 struct acpi_dmar_hardware_unit,
738 header);
739
740 for (scope = (void *)(drhd + 1);
741 (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length;
742 scope = ((void *)scope) + scope->length) {
743 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE)
744 continue;
745 if (scope->enumeration_id != device_number)
746 continue;
747
748 path = (void *)(scope + 1);
749 pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n",
750 dev_name(&adev->dev), dmaru->reg_base_addr,
751 scope->bus, path->device, path->function);
752 for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp)
753 if (tmp == NULL) {
754 dmaru->devices[i].bus = scope->bus;
755 dmaru->devices[i].devfn = PCI_DEVFN(path->device,
756 path->function);
757 rcu_assign_pointer(dmaru->devices[i].dev,
758 get_device(&adev->dev));
759 return;
760 }
761 BUG_ON(i >= dmaru->devices_cnt);
762 }
763 }
764 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n",
765 device_number, dev_name(&adev->dev));
766 }
767
dmar_acpi_dev_scope_init(void)768 static int __init dmar_acpi_dev_scope_init(void)
769 {
770 struct acpi_dmar_andd *andd;
771
772 if (dmar_tbl == NULL)
773 return -ENODEV;
774
775 for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar);
776 ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length;
777 andd = ((void *)andd) + andd->header.length) {
778 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) {
779 acpi_handle h;
780 struct acpi_device *adev;
781
782 if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT,
783 andd->device_name,
784 &h))) {
785 pr_err("Failed to find handle for ACPI object %s\n",
786 andd->device_name);
787 continue;
788 }
789 adev = acpi_fetch_acpi_dev(h);
790 if (!adev) {
791 pr_err("Failed to get device for ACPI object %s\n",
792 andd->device_name);
793 continue;
794 }
795 dmar_acpi_insert_dev_scope(andd->device_number, adev);
796 }
797 }
798 return 0;
799 }
800
dmar_dev_scope_init(void)801 int __init dmar_dev_scope_init(void)
802 {
803 struct pci_dev *dev = NULL;
804 struct dmar_pci_notify_info *info;
805
806 if (dmar_dev_scope_status != 1)
807 return dmar_dev_scope_status;
808
809 if (list_empty(&dmar_drhd_units)) {
810 dmar_dev_scope_status = -ENODEV;
811 } else {
812 dmar_dev_scope_status = 0;
813
814 dmar_acpi_dev_scope_init();
815
816 for_each_pci_dev(dev) {
817 if (dev->is_virtfn)
818 continue;
819
820 info = dmar_alloc_pci_notify_info(dev,
821 BUS_NOTIFY_ADD_DEVICE);
822 if (!info) {
823 pci_dev_put(dev);
824 return dmar_dev_scope_status;
825 } else {
826 dmar_pci_bus_add_dev(info);
827 dmar_free_pci_notify_info(info);
828 }
829 }
830 }
831
832 return dmar_dev_scope_status;
833 }
834
dmar_register_bus_notifier(void)835 void __init dmar_register_bus_notifier(void)
836 {
837 bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb);
838 }
839
840
dmar_table_init(void)841 int __init dmar_table_init(void)
842 {
843 static int dmar_table_initialized;
844 int ret;
845
846 if (dmar_table_initialized == 0) {
847 ret = parse_dmar_table();
848 if (ret < 0) {
849 if (ret != -ENODEV)
850 pr_info("Parse DMAR table failure.\n");
851 } else if (list_empty(&dmar_drhd_units)) {
852 pr_info("No DMAR devices found\n");
853 ret = -ENODEV;
854 }
855
856 if (ret < 0)
857 dmar_table_initialized = ret;
858 else
859 dmar_table_initialized = 1;
860 }
861
862 return dmar_table_initialized < 0 ? dmar_table_initialized : 0;
863 }
864
warn_invalid_dmar(u64 addr,const char * message)865 static void warn_invalid_dmar(u64 addr, const char *message)
866 {
867 pr_warn_once(FW_BUG
868 "Your BIOS is broken; DMAR reported at address %llx%s!\n"
869 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
870 addr, message,
871 dmi_get_system_info(DMI_BIOS_VENDOR),
872 dmi_get_system_info(DMI_BIOS_VERSION),
873 dmi_get_system_info(DMI_PRODUCT_VERSION));
874 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
875 }
876
877 static int __ref
dmar_validate_one_drhd(struct acpi_dmar_header * entry,void * arg)878 dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg)
879 {
880 struct acpi_dmar_hardware_unit *drhd;
881 void __iomem *addr;
882 u64 cap, ecap;
883
884 drhd = (void *)entry;
885 if (!drhd->address) {
886 warn_invalid_dmar(0, "");
887 return -EINVAL;
888 }
889
890 if (arg)
891 addr = ioremap(drhd->address, VTD_PAGE_SIZE);
892 else
893 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE);
894 if (!addr) {
895 pr_warn("Can't validate DRHD address: %llx\n", drhd->address);
896 return -EINVAL;
897 }
898
899 cap = dmar_readq(addr + DMAR_CAP_REG);
900 ecap = dmar_readq(addr + DMAR_ECAP_REG);
901
902 if (arg)
903 iounmap(addr);
904 else
905 early_iounmap(addr, VTD_PAGE_SIZE);
906
907 if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) {
908 warn_invalid_dmar(drhd->address, " returns all ones");
909 return -EINVAL;
910 }
911
912 return 0;
913 }
914
detect_intel_iommu(void)915 void __init detect_intel_iommu(void)
916 {
917 int ret;
918 struct dmar_res_callback validate_drhd_cb = {
919 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd,
920 .ignore_unhandled = true,
921 };
922
923 down_write(&dmar_global_lock);
924 ret = dmar_table_detect();
925 if (!ret)
926 ret = dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl,
927 &validate_drhd_cb);
928 if (!ret && !no_iommu && !iommu_detected &&
929 (!dmar_disabled || dmar_platform_optin())) {
930 iommu_detected = 1;
931 /* Make sure ACS will be enabled */
932 pci_request_acs();
933 }
934
935 #ifdef CONFIG_X86
936 if (!ret) {
937 x86_init.iommu.iommu_init = intel_iommu_init;
938 x86_platform.iommu_shutdown = intel_iommu_shutdown;
939 }
940
941 #endif
942
943 if (dmar_tbl) {
944 acpi_put_table(dmar_tbl);
945 dmar_tbl = NULL;
946 }
947 up_write(&dmar_global_lock);
948 }
949
unmap_iommu(struct intel_iommu * iommu)950 static void unmap_iommu(struct intel_iommu *iommu)
951 {
952 iounmap(iommu->reg);
953 release_mem_region(iommu->reg_phys, iommu->reg_size);
954 }
955
956 /**
957 * map_iommu: map the iommu's registers
958 * @iommu: the iommu to map
959 * @phys_addr: the physical address of the base resgister
960 *
961 * Memory map the iommu's registers. Start w/ a single page, and
962 * possibly expand if that turns out to be insufficent.
963 */
map_iommu(struct intel_iommu * iommu,u64 phys_addr)964 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
965 {
966 int map_size, err=0;
967
968 iommu->reg_phys = phys_addr;
969 iommu->reg_size = VTD_PAGE_SIZE;
970
971 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {
972 pr_err("Can't reserve memory\n");
973 err = -EBUSY;
974 goto out;
975 }
976
977 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
978 if (!iommu->reg) {
979 pr_err("Can't map the region\n");
980 err = -ENOMEM;
981 goto release;
982 }
983
984 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
985 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
986
987 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
988 err = -EINVAL;
989 warn_invalid_dmar(phys_addr, " returns all ones");
990 goto unmap;
991 }
992 if (ecap_vcs(iommu->ecap))
993 iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG);
994
995 /* the registers might be more than one page */
996 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
997 cap_max_fault_reg_offset(iommu->cap));
998 map_size = VTD_PAGE_ALIGN(map_size);
999 if (map_size > iommu->reg_size) {
1000 iounmap(iommu->reg);
1001 release_mem_region(iommu->reg_phys, iommu->reg_size);
1002 iommu->reg_size = map_size;
1003 if (!request_mem_region(iommu->reg_phys, iommu->reg_size,
1004 iommu->name)) {
1005 pr_err("Can't reserve memory\n");
1006 err = -EBUSY;
1007 goto out;
1008 }
1009 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
1010 if (!iommu->reg) {
1011 pr_err("Can't map the region\n");
1012 err = -ENOMEM;
1013 goto release;
1014 }
1015 }
1016 err = 0;
1017 goto out;
1018
1019 unmap:
1020 iounmap(iommu->reg);
1021 release:
1022 release_mem_region(iommu->reg_phys, iommu->reg_size);
1023 out:
1024 return err;
1025 }
1026
alloc_iommu(struct dmar_drhd_unit * drhd)1027 static int alloc_iommu(struct dmar_drhd_unit *drhd)
1028 {
1029 struct intel_iommu *iommu;
1030 u32 ver, sts;
1031 int agaw = -1;
1032 int msagaw = -1;
1033 int err;
1034
1035 if (!drhd->reg_base_addr) {
1036 warn_invalid_dmar(0, "");
1037 return -EINVAL;
1038 }
1039
1040 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
1041 if (!iommu)
1042 return -ENOMEM;
1043
1044 iommu->seq_id = ida_alloc_range(&dmar_seq_ids, 0,
1045 DMAR_UNITS_SUPPORTED - 1, GFP_KERNEL);
1046 if (iommu->seq_id < 0) {
1047 pr_err("Failed to allocate seq_id\n");
1048 err = iommu->seq_id;
1049 goto error;
1050 }
1051 sprintf(iommu->name, "dmar%d", iommu->seq_id);
1052
1053 err = map_iommu(iommu, drhd->reg_base_addr);
1054 if (err) {
1055 pr_err("Failed to map %s\n", iommu->name);
1056 goto error_free_seq_id;
1057 }
1058
1059 err = -EINVAL;
1060 if (!cap_sagaw(iommu->cap) &&
1061 (!ecap_smts(iommu->ecap) || ecap_slts(iommu->ecap))) {
1062 pr_info("%s: No supported address widths. Not attempting DMA translation.\n",
1063 iommu->name);
1064 drhd->ignored = 1;
1065 }
1066
1067 if (!drhd->ignored) {
1068 agaw = iommu_calculate_agaw(iommu);
1069 if (agaw < 0) {
1070 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n",
1071 iommu->seq_id);
1072 drhd->ignored = 1;
1073 }
1074 }
1075 if (!drhd->ignored) {
1076 msagaw = iommu_calculate_max_sagaw(iommu);
1077 if (msagaw < 0) {
1078 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n",
1079 iommu->seq_id);
1080 drhd->ignored = 1;
1081 agaw = -1;
1082 }
1083 }
1084 iommu->agaw = agaw;
1085 iommu->msagaw = msagaw;
1086 iommu->segment = drhd->segment;
1087
1088 iommu->node = NUMA_NO_NODE;
1089
1090 ver = readl(iommu->reg + DMAR_VER_REG);
1091 pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
1092 iommu->name,
1093 (unsigned long long)drhd->reg_base_addr,
1094 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
1095 (unsigned long long)iommu->cap,
1096 (unsigned long long)iommu->ecap);
1097
1098 /* Reflect status in gcmd */
1099 sts = readl(iommu->reg + DMAR_GSTS_REG);
1100 if (sts & DMA_GSTS_IRES)
1101 iommu->gcmd |= DMA_GCMD_IRE;
1102 if (sts & DMA_GSTS_TES)
1103 iommu->gcmd |= DMA_GCMD_TE;
1104 if (sts & DMA_GSTS_QIES)
1105 iommu->gcmd |= DMA_GCMD_QIE;
1106
1107 raw_spin_lock_init(&iommu->register_lock);
1108
1109 /*
1110 * A value of N in PSS field of eCap register indicates hardware
1111 * supports PASID field of N+1 bits.
1112 */
1113 if (pasid_supported(iommu))
1114 iommu->iommu.max_pasids = 2UL << ecap_pss(iommu->ecap);
1115
1116 /*
1117 * This is only for hotplug; at boot time intel_iommu_enabled won't
1118 * be set yet. When intel_iommu_init() runs, it registers the units
1119 * present at boot time, then sets intel_iommu_enabled.
1120 */
1121 if (intel_iommu_enabled && !drhd->ignored) {
1122 err = iommu_device_sysfs_add(&iommu->iommu, NULL,
1123 intel_iommu_groups,
1124 "%s", iommu->name);
1125 if (err)
1126 goto err_unmap;
1127
1128 err = iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL);
1129 if (err)
1130 goto err_sysfs;
1131 }
1132
1133 drhd->iommu = iommu;
1134 iommu->drhd = drhd;
1135
1136 return 0;
1137
1138 err_sysfs:
1139 iommu_device_sysfs_remove(&iommu->iommu);
1140 err_unmap:
1141 unmap_iommu(iommu);
1142 error_free_seq_id:
1143 ida_free(&dmar_seq_ids, iommu->seq_id);
1144 error:
1145 kfree(iommu);
1146 return err;
1147 }
1148
free_iommu(struct intel_iommu * iommu)1149 static void free_iommu(struct intel_iommu *iommu)
1150 {
1151 if (intel_iommu_enabled && !iommu->drhd->ignored) {
1152 iommu_device_unregister(&iommu->iommu);
1153 iommu_device_sysfs_remove(&iommu->iommu);
1154 }
1155
1156 if (iommu->irq) {
1157 if (iommu->pr_irq) {
1158 free_irq(iommu->pr_irq, iommu);
1159 dmar_free_hwirq(iommu->pr_irq);
1160 iommu->pr_irq = 0;
1161 }
1162 free_irq(iommu->irq, iommu);
1163 dmar_free_hwirq(iommu->irq);
1164 iommu->irq = 0;
1165 }
1166
1167 if (iommu->qi) {
1168 free_page((unsigned long)iommu->qi->desc);
1169 kfree(iommu->qi->desc_status);
1170 kfree(iommu->qi);
1171 }
1172
1173 if (iommu->reg)
1174 unmap_iommu(iommu);
1175
1176 ida_free(&dmar_seq_ids, iommu->seq_id);
1177 kfree(iommu);
1178 }
1179
1180 /*
1181 * Reclaim all the submitted descriptors which have completed its work.
1182 */
reclaim_free_desc(struct q_inval * qi)1183 static inline void reclaim_free_desc(struct q_inval *qi)
1184 {
1185 while (qi->desc_status[qi->free_tail] == QI_DONE ||
1186 qi->desc_status[qi->free_tail] == QI_ABORT) {
1187 qi->desc_status[qi->free_tail] = QI_FREE;
1188 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
1189 qi->free_cnt++;
1190 }
1191 }
1192
qi_type_string(u8 type)1193 static const char *qi_type_string(u8 type)
1194 {
1195 switch (type) {
1196 case QI_CC_TYPE:
1197 return "Context-cache Invalidation";
1198 case QI_IOTLB_TYPE:
1199 return "IOTLB Invalidation";
1200 case QI_DIOTLB_TYPE:
1201 return "Device-TLB Invalidation";
1202 case QI_IEC_TYPE:
1203 return "Interrupt Entry Cache Invalidation";
1204 case QI_IWD_TYPE:
1205 return "Invalidation Wait";
1206 case QI_EIOTLB_TYPE:
1207 return "PASID-based IOTLB Invalidation";
1208 case QI_PC_TYPE:
1209 return "PASID-cache Invalidation";
1210 case QI_DEIOTLB_TYPE:
1211 return "PASID-based Device-TLB Invalidation";
1212 case QI_PGRP_RESP_TYPE:
1213 return "Page Group Response";
1214 default:
1215 return "UNKNOWN";
1216 }
1217 }
1218
qi_dump_fault(struct intel_iommu * iommu,u32 fault)1219 static void qi_dump_fault(struct intel_iommu *iommu, u32 fault)
1220 {
1221 unsigned int head = dmar_readl(iommu->reg + DMAR_IQH_REG);
1222 u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG);
1223 struct qi_desc *desc = iommu->qi->desc + head;
1224
1225 if (fault & DMA_FSTS_IQE)
1226 pr_err("VT-d detected Invalidation Queue Error: Reason %llx",
1227 DMAR_IQER_REG_IQEI(iqe_err));
1228 if (fault & DMA_FSTS_ITE)
1229 pr_err("VT-d detected Invalidation Time-out Error: SID %llx",
1230 DMAR_IQER_REG_ITESID(iqe_err));
1231 if (fault & DMA_FSTS_ICE)
1232 pr_err("VT-d detected Invalidation Completion Error: SID %llx",
1233 DMAR_IQER_REG_ICESID(iqe_err));
1234
1235 pr_err("QI HEAD: %s qw0 = 0x%llx, qw1 = 0x%llx\n",
1236 qi_type_string(desc->qw0 & 0xf),
1237 (unsigned long long)desc->qw0,
1238 (unsigned long long)desc->qw1);
1239
1240 head = ((head >> qi_shift(iommu)) + QI_LENGTH - 1) % QI_LENGTH;
1241 head <<= qi_shift(iommu);
1242 desc = iommu->qi->desc + head;
1243
1244 pr_err("QI PRIOR: %s qw0 = 0x%llx, qw1 = 0x%llx\n",
1245 qi_type_string(desc->qw0 & 0xf),
1246 (unsigned long long)desc->qw0,
1247 (unsigned long long)desc->qw1);
1248 }
1249
qi_check_fault(struct intel_iommu * iommu,int index,int wait_index)1250 static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index)
1251 {
1252 u32 fault;
1253 int head, tail;
1254 struct q_inval *qi = iommu->qi;
1255 int shift = qi_shift(iommu);
1256
1257 if (qi->desc_status[wait_index] == QI_ABORT)
1258 return -EAGAIN;
1259
1260 fault = readl(iommu->reg + DMAR_FSTS_REG);
1261 if (fault & (DMA_FSTS_IQE | DMA_FSTS_ITE | DMA_FSTS_ICE))
1262 qi_dump_fault(iommu, fault);
1263
1264 /*
1265 * If IQE happens, the head points to the descriptor associated
1266 * with the error. No new descriptors are fetched until the IQE
1267 * is cleared.
1268 */
1269 if (fault & DMA_FSTS_IQE) {
1270 head = readl(iommu->reg + DMAR_IQH_REG);
1271 if ((head >> shift) == index) {
1272 struct qi_desc *desc = qi->desc + head;
1273
1274 /*
1275 * desc->qw2 and desc->qw3 are either reserved or
1276 * used by software as private data. We won't print
1277 * out these two qw's for security consideration.
1278 */
1279 memcpy(desc, qi->desc + (wait_index << shift),
1280 1 << shift);
1281 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
1282 pr_info("Invalidation Queue Error (IQE) cleared\n");
1283 return -EINVAL;
1284 }
1285 }
1286
1287 /*
1288 * If ITE happens, all pending wait_desc commands are aborted.
1289 * No new descriptors are fetched until the ITE is cleared.
1290 */
1291 if (fault & DMA_FSTS_ITE) {
1292 head = readl(iommu->reg + DMAR_IQH_REG);
1293 head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
1294 head |= 1;
1295 tail = readl(iommu->reg + DMAR_IQT_REG);
1296 tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
1297
1298 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
1299 pr_info("Invalidation Time-out Error (ITE) cleared\n");
1300
1301 do {
1302 if (qi->desc_status[head] == QI_IN_USE)
1303 qi->desc_status[head] = QI_ABORT;
1304 head = (head - 2 + QI_LENGTH) % QI_LENGTH;
1305 } while (head != tail);
1306
1307 if (qi->desc_status[wait_index] == QI_ABORT)
1308 return -EAGAIN;
1309 }
1310
1311 if (fault & DMA_FSTS_ICE) {
1312 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);
1313 pr_info("Invalidation Completion Error (ICE) cleared\n");
1314 }
1315
1316 return 0;
1317 }
1318
1319 /*
1320 * Function to submit invalidation descriptors of all types to the queued
1321 * invalidation interface(QI). Multiple descriptors can be submitted at a
1322 * time, a wait descriptor will be appended to each submission to ensure
1323 * hardware has completed the invalidation before return. Wait descriptors
1324 * can be part of the submission but it will not be polled for completion.
1325 */
qi_submit_sync(struct intel_iommu * iommu,struct qi_desc * desc,unsigned int count,unsigned long options)1326 int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc,
1327 unsigned int count, unsigned long options)
1328 {
1329 struct q_inval *qi = iommu->qi;
1330 s64 devtlb_start_ktime = 0;
1331 s64 iotlb_start_ktime = 0;
1332 s64 iec_start_ktime = 0;
1333 struct qi_desc wait_desc;
1334 int wait_index, index;
1335 unsigned long flags;
1336 int offset, shift;
1337 int rc, i;
1338 u64 type;
1339
1340 if (!qi)
1341 return 0;
1342
1343 type = desc->qw0 & GENMASK_ULL(3, 0);
1344
1345 if ((type == QI_IOTLB_TYPE || type == QI_EIOTLB_TYPE) &&
1346 dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IOTLB))
1347 iotlb_start_ktime = ktime_to_ns(ktime_get());
1348
1349 if ((type == QI_DIOTLB_TYPE || type == QI_DEIOTLB_TYPE) &&
1350 dmar_latency_enabled(iommu, DMAR_LATENCY_INV_DEVTLB))
1351 devtlb_start_ktime = ktime_to_ns(ktime_get());
1352
1353 if (type == QI_IEC_TYPE &&
1354 dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IEC))
1355 iec_start_ktime = ktime_to_ns(ktime_get());
1356
1357 restart:
1358 rc = 0;
1359
1360 raw_spin_lock_irqsave(&qi->q_lock, flags);
1361 /*
1362 * Check if we have enough empty slots in the queue to submit,
1363 * the calculation is based on:
1364 * # of desc + 1 wait desc + 1 space between head and tail
1365 */
1366 while (qi->free_cnt < count + 2) {
1367 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1368 cpu_relax();
1369 raw_spin_lock_irqsave(&qi->q_lock, flags);
1370 }
1371
1372 index = qi->free_head;
1373 wait_index = (index + count) % QI_LENGTH;
1374 shift = qi_shift(iommu);
1375
1376 for (i = 0; i < count; i++) {
1377 offset = ((index + i) % QI_LENGTH) << shift;
1378 memcpy(qi->desc + offset, &desc[i], 1 << shift);
1379 qi->desc_status[(index + i) % QI_LENGTH] = QI_IN_USE;
1380 trace_qi_submit(iommu, desc[i].qw0, desc[i].qw1,
1381 desc[i].qw2, desc[i].qw3);
1382 }
1383 qi->desc_status[wait_index] = QI_IN_USE;
1384
1385 wait_desc.qw0 = QI_IWD_STATUS_DATA(QI_DONE) |
1386 QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
1387 if (options & QI_OPT_WAIT_DRAIN)
1388 wait_desc.qw0 |= QI_IWD_PRQ_DRAIN;
1389 wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]);
1390 wait_desc.qw2 = 0;
1391 wait_desc.qw3 = 0;
1392
1393 offset = wait_index << shift;
1394 memcpy(qi->desc + offset, &wait_desc, 1 << shift);
1395
1396 qi->free_head = (qi->free_head + count + 1) % QI_LENGTH;
1397 qi->free_cnt -= count + 1;
1398
1399 /*
1400 * update the HW tail register indicating the presence of
1401 * new descriptors.
1402 */
1403 writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG);
1404
1405 while (qi->desc_status[wait_index] != QI_DONE) {
1406 /*
1407 * We will leave the interrupts disabled, to prevent interrupt
1408 * context to queue another cmd while a cmd is already submitted
1409 * and waiting for completion on this cpu. This is to avoid
1410 * a deadlock where the interrupt context can wait indefinitely
1411 * for free slots in the queue.
1412 */
1413 rc = qi_check_fault(iommu, index, wait_index);
1414 if (rc)
1415 break;
1416
1417 raw_spin_unlock(&qi->q_lock);
1418 cpu_relax();
1419 raw_spin_lock(&qi->q_lock);
1420 }
1421
1422 for (i = 0; i < count; i++)
1423 qi->desc_status[(index + i) % QI_LENGTH] = QI_DONE;
1424
1425 reclaim_free_desc(qi);
1426 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1427
1428 if (rc == -EAGAIN)
1429 goto restart;
1430
1431 if (iotlb_start_ktime)
1432 dmar_latency_update(iommu, DMAR_LATENCY_INV_IOTLB,
1433 ktime_to_ns(ktime_get()) - iotlb_start_ktime);
1434
1435 if (devtlb_start_ktime)
1436 dmar_latency_update(iommu, DMAR_LATENCY_INV_DEVTLB,
1437 ktime_to_ns(ktime_get()) - devtlb_start_ktime);
1438
1439 if (iec_start_ktime)
1440 dmar_latency_update(iommu, DMAR_LATENCY_INV_IEC,
1441 ktime_to_ns(ktime_get()) - iec_start_ktime);
1442
1443 return rc;
1444 }
1445
1446 /*
1447 * Flush the global interrupt entry cache.
1448 */
qi_global_iec(struct intel_iommu * iommu)1449 void qi_global_iec(struct intel_iommu *iommu)
1450 {
1451 struct qi_desc desc;
1452
1453 desc.qw0 = QI_IEC_TYPE;
1454 desc.qw1 = 0;
1455 desc.qw2 = 0;
1456 desc.qw3 = 0;
1457
1458 /* should never fail */
1459 qi_submit_sync(iommu, &desc, 1, 0);
1460 }
1461
qi_flush_context(struct intel_iommu * iommu,u16 did,u16 sid,u8 fm,u64 type)1462 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
1463 u64 type)
1464 {
1465 struct qi_desc desc;
1466
1467 desc.qw0 = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
1468 | QI_CC_GRAN(type) | QI_CC_TYPE;
1469 desc.qw1 = 0;
1470 desc.qw2 = 0;
1471 desc.qw3 = 0;
1472
1473 qi_submit_sync(iommu, &desc, 1, 0);
1474 }
1475
qi_flush_iotlb(struct intel_iommu * iommu,u16 did,u64 addr,unsigned int size_order,u64 type)1476 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1477 unsigned int size_order, u64 type)
1478 {
1479 u8 dw = 0, dr = 0;
1480
1481 struct qi_desc desc;
1482 int ih = 0;
1483
1484 if (cap_write_drain(iommu->cap))
1485 dw = 1;
1486
1487 if (cap_read_drain(iommu->cap))
1488 dr = 1;
1489
1490 desc.qw0 = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
1491 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
1492 desc.qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
1493 | QI_IOTLB_AM(size_order);
1494 desc.qw2 = 0;
1495 desc.qw3 = 0;
1496
1497 qi_submit_sync(iommu, &desc, 1, 0);
1498 }
1499
qi_flush_dev_iotlb(struct intel_iommu * iommu,u16 sid,u16 pfsid,u16 qdep,u64 addr,unsigned mask)1500 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
1501 u16 qdep, u64 addr, unsigned mask)
1502 {
1503 struct qi_desc desc;
1504
1505 /*
1506 * VT-d spec, section 4.3:
1507 *
1508 * Software is recommended to not submit any Device-TLB invalidation
1509 * requests while address remapping hardware is disabled.
1510 */
1511 if (!(iommu->gcmd & DMA_GCMD_TE))
1512 return;
1513
1514 if (mask) {
1515 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
1516 desc.qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
1517 } else
1518 desc.qw1 = QI_DEV_IOTLB_ADDR(addr);
1519
1520 if (qdep >= QI_DEV_IOTLB_MAX_INVS)
1521 qdep = 0;
1522
1523 desc.qw0 = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
1524 QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
1525 desc.qw2 = 0;
1526 desc.qw3 = 0;
1527
1528 qi_submit_sync(iommu, &desc, 1, 0);
1529 }
1530
1531 /* PASID-based IOTLB invalidation */
qi_flush_piotlb(struct intel_iommu * iommu,u16 did,u32 pasid,u64 addr,unsigned long npages,bool ih)1532 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
1533 unsigned long npages, bool ih)
1534 {
1535 struct qi_desc desc = {.qw2 = 0, .qw3 = 0};
1536
1537 /*
1538 * npages == -1 means a PASID-selective invalidation, otherwise,
1539 * a positive value for Page-selective-within-PASID invalidation.
1540 * 0 is not a valid input.
1541 */
1542 if (WARN_ON(!npages)) {
1543 pr_err("Invalid input npages = %ld\n", npages);
1544 return;
1545 }
1546
1547 if (npages == -1) {
1548 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1549 QI_EIOTLB_DID(did) |
1550 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
1551 QI_EIOTLB_TYPE;
1552 desc.qw1 = 0;
1553 } else {
1554 int mask = ilog2(__roundup_pow_of_two(npages));
1555 unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask));
1556
1557 if (WARN_ON_ONCE(!IS_ALIGNED(addr, align)))
1558 addr = ALIGN_DOWN(addr, align);
1559
1560 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1561 QI_EIOTLB_DID(did) |
1562 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
1563 QI_EIOTLB_TYPE;
1564 desc.qw1 = QI_EIOTLB_ADDR(addr) |
1565 QI_EIOTLB_IH(ih) |
1566 QI_EIOTLB_AM(mask);
1567 }
1568
1569 qi_submit_sync(iommu, &desc, 1, 0);
1570 }
1571
1572 /* PASID-based device IOTLB Invalidate */
qi_flush_dev_iotlb_pasid(struct intel_iommu * iommu,u16 sid,u16 pfsid,u32 pasid,u16 qdep,u64 addr,unsigned int size_order)1573 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
1574 u32 pasid, u16 qdep, u64 addr, unsigned int size_order)
1575 {
1576 unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);
1577 struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};
1578
1579 /*
1580 * VT-d spec, section 4.3:
1581 *
1582 * Software is recommended to not submit any Device-TLB invalidation
1583 * requests while address remapping hardware is disabled.
1584 */
1585 if (!(iommu->gcmd & DMA_GCMD_TE))
1586 return;
1587
1588 desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
1589 QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
1590 QI_DEV_IOTLB_PFSID(pfsid);
1591
1592 /*
1593 * If S bit is 0, we only flush a single page. If S bit is set,
1594 * The least significant zero bit indicates the invalidation address
1595 * range. VT-d spec 6.5.2.6.
1596 * e.g. address bit 12[0] indicates 8KB, 13[0] indicates 16KB.
1597 * size order = 0 is PAGE_SIZE 4KB
1598 * Max Invs Pending (MIP) is set to 0 for now until we have DIT in
1599 * ECAP.
1600 */
1601 if (!IS_ALIGNED(addr, VTD_PAGE_SIZE << size_order))
1602 pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n",
1603 addr, size_order);
1604
1605 /* Take page address */
1606 desc.qw1 = QI_DEV_EIOTLB_ADDR(addr);
1607
1608 if (size_order) {
1609 /*
1610 * Existing 0s in address below size_order may be the least
1611 * significant bit, we must set them to 1s to avoid having
1612 * smaller size than desired.
1613 */
1614 desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1,
1615 VTD_PAGE_SHIFT);
1616 /* Clear size_order bit to indicate size */
1617 desc.qw1 &= ~mask;
1618 /* Set the S bit to indicate flushing more than 1 page */
1619 desc.qw1 |= QI_DEV_EIOTLB_SIZE;
1620 }
1621
1622 qi_submit_sync(iommu, &desc, 1, 0);
1623 }
1624
qi_flush_pasid_cache(struct intel_iommu * iommu,u16 did,u64 granu,u32 pasid)1625 void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did,
1626 u64 granu, u32 pasid)
1627 {
1628 struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};
1629
1630 desc.qw0 = QI_PC_PASID(pasid) | QI_PC_DID(did) |
1631 QI_PC_GRAN(granu) | QI_PC_TYPE;
1632 qi_submit_sync(iommu, &desc, 1, 0);
1633 }
1634
1635 /*
1636 * Disable Queued Invalidation interface.
1637 */
dmar_disable_qi(struct intel_iommu * iommu)1638 void dmar_disable_qi(struct intel_iommu *iommu)
1639 {
1640 unsigned long flags;
1641 u32 sts;
1642 cycles_t start_time = get_cycles();
1643
1644 if (!ecap_qis(iommu->ecap))
1645 return;
1646
1647 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1648
1649 sts = readl(iommu->reg + DMAR_GSTS_REG);
1650 if (!(sts & DMA_GSTS_QIES))
1651 goto end;
1652
1653 /*
1654 * Give a chance to HW to complete the pending invalidation requests.
1655 */
1656 while ((readl(iommu->reg + DMAR_IQT_REG) !=
1657 readl(iommu->reg + DMAR_IQH_REG)) &&
1658 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time)))
1659 cpu_relax();
1660
1661 iommu->gcmd &= ~DMA_GCMD_QIE;
1662 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1663
1664 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
1665 !(sts & DMA_GSTS_QIES), sts);
1666 end:
1667 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1668 }
1669
1670 /*
1671 * Enable queued invalidation.
1672 */
__dmar_enable_qi(struct intel_iommu * iommu)1673 static void __dmar_enable_qi(struct intel_iommu *iommu)
1674 {
1675 u32 sts;
1676 unsigned long flags;
1677 struct q_inval *qi = iommu->qi;
1678 u64 val = virt_to_phys(qi->desc);
1679
1680 qi->free_head = qi->free_tail = 0;
1681 qi->free_cnt = QI_LENGTH;
1682
1683 /*
1684 * Set DW=1 and QS=1 in IQA_REG when Scalable Mode capability
1685 * is present.
1686 */
1687 if (ecap_smts(iommu->ecap))
1688 val |= (1 << 11) | 1;
1689
1690 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1691
1692 /* write zero to the tail reg */
1693 writel(0, iommu->reg + DMAR_IQT_REG);
1694
1695 dmar_writeq(iommu->reg + DMAR_IQA_REG, val);
1696
1697 iommu->gcmd |= DMA_GCMD_QIE;
1698 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1699
1700 /* Make sure hardware complete it */
1701 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
1702
1703 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1704 }
1705
1706 /*
1707 * Enable Queued Invalidation interface. This is a must to support
1708 * interrupt-remapping. Also used by DMA-remapping, which replaces
1709 * register based IOTLB invalidation.
1710 */
dmar_enable_qi(struct intel_iommu * iommu)1711 int dmar_enable_qi(struct intel_iommu *iommu)
1712 {
1713 struct q_inval *qi;
1714 struct page *desc_page;
1715
1716 if (!ecap_qis(iommu->ecap))
1717 return -ENOENT;
1718
1719 /*
1720 * queued invalidation is already setup and enabled.
1721 */
1722 if (iommu->qi)
1723 return 0;
1724
1725 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);
1726 if (!iommu->qi)
1727 return -ENOMEM;
1728
1729 qi = iommu->qi;
1730
1731 /*
1732 * Need two pages to accommodate 256 descriptors of 256 bits each
1733 * if the remapping hardware supports scalable mode translation.
1734 */
1735 desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,
1736 !!ecap_smts(iommu->ecap));
1737 if (!desc_page) {
1738 kfree(qi);
1739 iommu->qi = NULL;
1740 return -ENOMEM;
1741 }
1742
1743 qi->desc = page_address(desc_page);
1744
1745 qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC);
1746 if (!qi->desc_status) {
1747 free_page((unsigned long) qi->desc);
1748 kfree(qi);
1749 iommu->qi = NULL;
1750 return -ENOMEM;
1751 }
1752
1753 raw_spin_lock_init(&qi->q_lock);
1754
1755 __dmar_enable_qi(iommu);
1756
1757 return 0;
1758 }
1759
1760 /* iommu interrupt handling. Most stuff are MSI-like. */
1761
1762 enum faulttype {
1763 DMA_REMAP,
1764 INTR_REMAP,
1765 UNKNOWN,
1766 };
1767
1768 static const char *dma_remap_fault_reasons[] =
1769 {
1770 "Software",
1771 "Present bit in root entry is clear",
1772 "Present bit in context entry is clear",
1773 "Invalid context entry",
1774 "Access beyond MGAW",
1775 "PTE Write access is not set",
1776 "PTE Read access is not set",
1777 "Next page table ptr is invalid",
1778 "Root table address invalid",
1779 "Context table ptr is invalid",
1780 "non-zero reserved fields in RTP",
1781 "non-zero reserved fields in CTP",
1782 "non-zero reserved fields in PTE",
1783 "PCE for translation request specifies blocking",
1784 };
1785
1786 static const char * const dma_remap_sm_fault_reasons[] = {
1787 "SM: Invalid Root Table Address",
1788 "SM: TTM 0 for request with PASID",
1789 "SM: TTM 0 for page group request",
1790 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */
1791 "SM: Error attempting to access Root Entry",
1792 "SM: Present bit in Root Entry is clear",
1793 "SM: Non-zero reserved field set in Root Entry",
1794 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */
1795 "SM: Error attempting to access Context Entry",
1796 "SM: Present bit in Context Entry is clear",
1797 "SM: Non-zero reserved field set in the Context Entry",
1798 "SM: Invalid Context Entry",
1799 "SM: DTE field in Context Entry is clear",
1800 "SM: PASID Enable field in Context Entry is clear",
1801 "SM: PASID is larger than the max in Context Entry",
1802 "SM: PRE field in Context-Entry is clear",
1803 "SM: RID_PASID field error in Context-Entry",
1804 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */
1805 "SM: Error attempting to access the PASID Directory Entry",
1806 "SM: Present bit in Directory Entry is clear",
1807 "SM: Non-zero reserved field set in PASID Directory Entry",
1808 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */
1809 "SM: Error attempting to access PASID Table Entry",
1810 "SM: Present bit in PASID Table Entry is clear",
1811 "SM: Non-zero reserved field set in PASID Table Entry",
1812 "SM: Invalid Scalable-Mode PASID Table Entry",
1813 "SM: ERE field is clear in PASID Table Entry",
1814 "SM: SRE field is clear in PASID Table Entry",
1815 "Unknown", "Unknown",/* 0x5E-0x5F */
1816 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x67 */
1817 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x6F */
1818 "SM: Error attempting to access first-level paging entry",
1819 "SM: Present bit in first-level paging entry is clear",
1820 "SM: Non-zero reserved field set in first-level paging entry",
1821 "SM: Error attempting to access FL-PML4 entry",
1822 "SM: First-level entry address beyond MGAW in Nested translation",
1823 "SM: Read permission error in FL-PML4 entry in Nested translation",
1824 "SM: Read permission error in first-level paging entry in Nested translation",
1825 "SM: Write permission error in first-level paging entry in Nested translation",
1826 "SM: Error attempting to access second-level paging entry",
1827 "SM: Read/Write permission error in second-level paging entry",
1828 "SM: Non-zero reserved field set in second-level paging entry",
1829 "SM: Invalid second-level page table pointer",
1830 "SM: A/D bit update needed in second-level entry when set up in no snoop",
1831 "Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */
1832 "SM: Address in first-level translation is not canonical",
1833 "SM: U/S set 0 for first-level translation with user privilege",
1834 "SM: No execute permission for request with PASID and ER=1",
1835 "SM: Address beyond the DMA hardware max",
1836 "SM: Second-level entry address beyond the max",
1837 "SM: No write permission for Write/AtomicOp request",
1838 "SM: No read permission for Read/AtomicOp request",
1839 "SM: Invalid address-interrupt address",
1840 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x8F */
1841 "SM: A/D bit update needed in first-level entry when set up in no snoop",
1842 };
1843
1844 static const char *irq_remap_fault_reasons[] =
1845 {
1846 "Detected reserved fields in the decoded interrupt-remapped request",
1847 "Interrupt index exceeded the interrupt-remapping table size",
1848 "Present field in the IRTE entry is clear",
1849 "Error accessing interrupt-remapping table pointed by IRTA_REG",
1850 "Detected reserved fields in the IRTE entry",
1851 "Blocked a compatibility format interrupt request",
1852 "Blocked an interrupt request due to source-id verification failure",
1853 };
1854
dmar_get_fault_reason(u8 fault_reason,int * fault_type)1855 static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
1856 {
1857 if (fault_reason >= 0x20 && (fault_reason - 0x20 <
1858 ARRAY_SIZE(irq_remap_fault_reasons))) {
1859 *fault_type = INTR_REMAP;
1860 return irq_remap_fault_reasons[fault_reason - 0x20];
1861 } else if (fault_reason >= 0x30 && (fault_reason - 0x30 <
1862 ARRAY_SIZE(dma_remap_sm_fault_reasons))) {
1863 *fault_type = DMA_REMAP;
1864 return dma_remap_sm_fault_reasons[fault_reason - 0x30];
1865 } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) {
1866 *fault_type = DMA_REMAP;
1867 return dma_remap_fault_reasons[fault_reason];
1868 } else {
1869 *fault_type = UNKNOWN;
1870 return "Unknown";
1871 }
1872 }
1873
1874
dmar_msi_reg(struct intel_iommu * iommu,int irq)1875 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq)
1876 {
1877 if (iommu->irq == irq)
1878 return DMAR_FECTL_REG;
1879 else if (iommu->pr_irq == irq)
1880 return DMAR_PECTL_REG;
1881 else
1882 BUG();
1883 }
1884
dmar_msi_unmask(struct irq_data * data)1885 void dmar_msi_unmask(struct irq_data *data)
1886 {
1887 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1888 int reg = dmar_msi_reg(iommu, data->irq);
1889 unsigned long flag;
1890
1891 /* unmask it */
1892 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1893 writel(0, iommu->reg + reg);
1894 /* Read a reg to force flush the post write */
1895 readl(iommu->reg + reg);
1896 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1897 }
1898
dmar_msi_mask(struct irq_data * data)1899 void dmar_msi_mask(struct irq_data *data)
1900 {
1901 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1902 int reg = dmar_msi_reg(iommu, data->irq);
1903 unsigned long flag;
1904
1905 /* mask it */
1906 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1907 writel(DMA_FECTL_IM, iommu->reg + reg);
1908 /* Read a reg to force flush the post write */
1909 readl(iommu->reg + reg);
1910 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1911 }
1912
dmar_msi_write(int irq,struct msi_msg * msg)1913 void dmar_msi_write(int irq, struct msi_msg *msg)
1914 {
1915 struct intel_iommu *iommu = irq_get_handler_data(irq);
1916 int reg = dmar_msi_reg(iommu, irq);
1917 unsigned long flag;
1918
1919 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1920 writel(msg->data, iommu->reg + reg + 4);
1921 writel(msg->address_lo, iommu->reg + reg + 8);
1922 writel(msg->address_hi, iommu->reg + reg + 12);
1923 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1924 }
1925
dmar_msi_read(int irq,struct msi_msg * msg)1926 void dmar_msi_read(int irq, struct msi_msg *msg)
1927 {
1928 struct intel_iommu *iommu = irq_get_handler_data(irq);
1929 int reg = dmar_msi_reg(iommu, irq);
1930 unsigned long flag;
1931
1932 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1933 msg->data = readl(iommu->reg + reg + 4);
1934 msg->address_lo = readl(iommu->reg + reg + 8);
1935 msg->address_hi = readl(iommu->reg + reg + 12);
1936 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1937 }
1938
dmar_fault_do_one(struct intel_iommu * iommu,int type,u8 fault_reason,u32 pasid,u16 source_id,unsigned long long addr)1939 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
1940 u8 fault_reason, u32 pasid, u16 source_id,
1941 unsigned long long addr)
1942 {
1943 const char *reason;
1944 int fault_type;
1945
1946 reason = dmar_get_fault_reason(fault_reason, &fault_type);
1947
1948 if (fault_type == INTR_REMAP) {
1949 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index 0x%llx [fault reason 0x%02x] %s\n",
1950 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1951 PCI_FUNC(source_id & 0xFF), addr >> 48,
1952 fault_reason, reason);
1953
1954 return 0;
1955 }
1956
1957 if (pasid == INVALID_IOASID)
1958 pr_err("[%s NO_PASID] Request device [%02x:%02x.%d] fault addr 0x%llx [fault reason 0x%02x] %s\n",
1959 type ? "DMA Read" : "DMA Write",
1960 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1961 PCI_FUNC(source_id & 0xFF), addr,
1962 fault_reason, reason);
1963 else
1964 pr_err("[%s PASID 0x%x] Request device [%02x:%02x.%d] fault addr 0x%llx [fault reason 0x%02x] %s\n",
1965 type ? "DMA Read" : "DMA Write", pasid,
1966 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1967 PCI_FUNC(source_id & 0xFF), addr,
1968 fault_reason, reason);
1969
1970 dmar_fault_dump_ptes(iommu, source_id, addr, pasid);
1971
1972 return 0;
1973 }
1974
1975 #define PRIMARY_FAULT_REG_LEN (16)
dmar_fault(int irq,void * dev_id)1976 irqreturn_t dmar_fault(int irq, void *dev_id)
1977 {
1978 struct intel_iommu *iommu = dev_id;
1979 int reg, fault_index;
1980 u32 fault_status;
1981 unsigned long flag;
1982 static DEFINE_RATELIMIT_STATE(rs,
1983 DEFAULT_RATELIMIT_INTERVAL,
1984 DEFAULT_RATELIMIT_BURST);
1985
1986 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1987 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1988 if (fault_status && __ratelimit(&rs))
1989 pr_err("DRHD: handling fault status reg %x\n", fault_status);
1990
1991 /* TBD: ignore advanced fault log currently */
1992 if (!(fault_status & DMA_FSTS_PPF))
1993 goto unlock_exit;
1994
1995 fault_index = dma_fsts_fault_record_index(fault_status);
1996 reg = cap_fault_reg_offset(iommu->cap);
1997 while (1) {
1998 /* Disable printing, simply clear the fault when ratelimited */
1999 bool ratelimited = !__ratelimit(&rs);
2000 u8 fault_reason;
2001 u16 source_id;
2002 u64 guest_addr;
2003 u32 pasid;
2004 int type;
2005 u32 data;
2006 bool pasid_present;
2007
2008 /* highest 32 bits */
2009 data = readl(iommu->reg + reg +
2010 fault_index * PRIMARY_FAULT_REG_LEN + 12);
2011 if (!(data & DMA_FRCD_F))
2012 break;
2013
2014 if (!ratelimited) {
2015 fault_reason = dma_frcd_fault_reason(data);
2016 type = dma_frcd_type(data);
2017
2018 pasid = dma_frcd_pasid_value(data);
2019 data = readl(iommu->reg + reg +
2020 fault_index * PRIMARY_FAULT_REG_LEN + 8);
2021 source_id = dma_frcd_source_id(data);
2022
2023 pasid_present = dma_frcd_pasid_present(data);
2024 guest_addr = dmar_readq(iommu->reg + reg +
2025 fault_index * PRIMARY_FAULT_REG_LEN);
2026 guest_addr = dma_frcd_page_addr(guest_addr);
2027 }
2028
2029 /* clear the fault */
2030 writel(DMA_FRCD_F, iommu->reg + reg +
2031 fault_index * PRIMARY_FAULT_REG_LEN + 12);
2032
2033 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
2034
2035 if (!ratelimited)
2036 /* Using pasid -1 if pasid is not present */
2037 dmar_fault_do_one(iommu, type, fault_reason,
2038 pasid_present ? pasid : INVALID_IOASID,
2039 source_id, guest_addr);
2040
2041 fault_index++;
2042 if (fault_index >= cap_num_fault_regs(iommu->cap))
2043 fault_index = 0;
2044 raw_spin_lock_irqsave(&iommu->register_lock, flag);
2045 }
2046
2047 writel(DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_PRO,
2048 iommu->reg + DMAR_FSTS_REG);
2049
2050 unlock_exit:
2051 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
2052 return IRQ_HANDLED;
2053 }
2054
dmar_set_interrupt(struct intel_iommu * iommu)2055 int dmar_set_interrupt(struct intel_iommu *iommu)
2056 {
2057 int irq, ret;
2058
2059 /*
2060 * Check if the fault interrupt is already initialized.
2061 */
2062 if (iommu->irq)
2063 return 0;
2064
2065 irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu);
2066 if (irq > 0) {
2067 iommu->irq = irq;
2068 } else {
2069 pr_err("No free IRQ vectors\n");
2070 return -EINVAL;
2071 }
2072
2073 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);
2074 if (ret)
2075 pr_err("Can't request irq\n");
2076 return ret;
2077 }
2078
enable_drhd_fault_handling(void)2079 int __init enable_drhd_fault_handling(void)
2080 {
2081 struct dmar_drhd_unit *drhd;
2082 struct intel_iommu *iommu;
2083
2084 /*
2085 * Enable fault control interrupt.
2086 */
2087 for_each_iommu(iommu, drhd) {
2088 u32 fault_status;
2089 int ret = dmar_set_interrupt(iommu);
2090
2091 if (ret) {
2092 pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n",
2093 (unsigned long long)drhd->reg_base_addr, ret);
2094 return -1;
2095 }
2096
2097 /*
2098 * Clear any previous faults.
2099 */
2100 dmar_fault(iommu->irq, iommu);
2101 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
2102 writel(fault_status, iommu->reg + DMAR_FSTS_REG);
2103 }
2104
2105 return 0;
2106 }
2107
2108 /*
2109 * Re-enable Queued Invalidation interface.
2110 */
dmar_reenable_qi(struct intel_iommu * iommu)2111 int dmar_reenable_qi(struct intel_iommu *iommu)
2112 {
2113 if (!ecap_qis(iommu->ecap))
2114 return -ENOENT;
2115
2116 if (!iommu->qi)
2117 return -ENOENT;
2118
2119 /*
2120 * First disable queued invalidation.
2121 */
2122 dmar_disable_qi(iommu);
2123 /*
2124 * Then enable queued invalidation again. Since there is no pending
2125 * invalidation requests now, it's safe to re-enable queued
2126 * invalidation.
2127 */
2128 __dmar_enable_qi(iommu);
2129
2130 return 0;
2131 }
2132
2133 /*
2134 * Check interrupt remapping support in DMAR table description.
2135 */
dmar_ir_support(void)2136 int __init dmar_ir_support(void)
2137 {
2138 struct acpi_table_dmar *dmar;
2139 dmar = (struct acpi_table_dmar *)dmar_tbl;
2140 if (!dmar)
2141 return 0;
2142 return dmar->flags & 0x1;
2143 }
2144
2145 /* Check whether DMAR units are in use */
dmar_in_use(void)2146 static inline bool dmar_in_use(void)
2147 {
2148 return irq_remapping_enabled || intel_iommu_enabled;
2149 }
2150
dmar_free_unused_resources(void)2151 static int __init dmar_free_unused_resources(void)
2152 {
2153 struct dmar_drhd_unit *dmaru, *dmaru_n;
2154
2155 if (dmar_in_use())
2156 return 0;
2157
2158 if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units))
2159 bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb);
2160
2161 down_write(&dmar_global_lock);
2162 list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) {
2163 list_del(&dmaru->list);
2164 dmar_free_drhd(dmaru);
2165 }
2166 up_write(&dmar_global_lock);
2167
2168 return 0;
2169 }
2170
2171 late_initcall(dmar_free_unused_resources);
2172
2173 /*
2174 * DMAR Hotplug Support
2175 * For more details, please refer to Intel(R) Virtualization Technology
2176 * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
2177 * "Remapping Hardware Unit Hot Plug".
2178 */
2179 static guid_t dmar_hp_guid =
2180 GUID_INIT(0xD8C1A3A6, 0xBE9B, 0x4C9B,
2181 0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF);
2182
2183 /*
2184 * Currently there's only one revision and BIOS will not check the revision id,
2185 * so use 0 for safety.
2186 */
2187 #define DMAR_DSM_REV_ID 0
2188 #define DMAR_DSM_FUNC_DRHD 1
2189 #define DMAR_DSM_FUNC_ATSR 2
2190 #define DMAR_DSM_FUNC_RHSA 3
2191 #define DMAR_DSM_FUNC_SATC 4
2192
dmar_detect_dsm(acpi_handle handle,int func)2193 static inline bool dmar_detect_dsm(acpi_handle handle, int func)
2194 {
2195 return acpi_check_dsm(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 1 << func);
2196 }
2197
dmar_walk_dsm_resource(acpi_handle handle,int func,dmar_res_handler_t handler,void * arg)2198 static int dmar_walk_dsm_resource(acpi_handle handle, int func,
2199 dmar_res_handler_t handler, void *arg)
2200 {
2201 int ret = -ENODEV;
2202 union acpi_object *obj;
2203 struct acpi_dmar_header *start;
2204 struct dmar_res_callback callback;
2205 static int res_type[] = {
2206 [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT,
2207 [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS,
2208 [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY,
2209 [DMAR_DSM_FUNC_SATC] = ACPI_DMAR_TYPE_SATC,
2210 };
2211
2212 if (!dmar_detect_dsm(handle, func))
2213 return 0;
2214
2215 obj = acpi_evaluate_dsm_typed(handle, &dmar_hp_guid, DMAR_DSM_REV_ID,
2216 func, NULL, ACPI_TYPE_BUFFER);
2217 if (!obj)
2218 return -ENODEV;
2219
2220 memset(&callback, 0, sizeof(callback));
2221 callback.cb[res_type[func]] = handler;
2222 callback.arg[res_type[func]] = arg;
2223 start = (struct acpi_dmar_header *)obj->buffer.pointer;
2224 ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback);
2225
2226 ACPI_FREE(obj);
2227
2228 return ret;
2229 }
2230
dmar_hp_add_drhd(struct acpi_dmar_header * header,void * arg)2231 static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg)
2232 {
2233 int ret;
2234 struct dmar_drhd_unit *dmaru;
2235
2236 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2237 if (!dmaru)
2238 return -ENODEV;
2239
2240 ret = dmar_ir_hotplug(dmaru, true);
2241 if (ret == 0)
2242 ret = dmar_iommu_hotplug(dmaru, true);
2243
2244 return ret;
2245 }
2246
dmar_hp_remove_drhd(struct acpi_dmar_header * header,void * arg)2247 static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg)
2248 {
2249 int i, ret;
2250 struct device *dev;
2251 struct dmar_drhd_unit *dmaru;
2252
2253 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2254 if (!dmaru)
2255 return 0;
2256
2257 /*
2258 * All PCI devices managed by this unit should have been destroyed.
2259 */
2260 if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) {
2261 for_each_active_dev_scope(dmaru->devices,
2262 dmaru->devices_cnt, i, dev)
2263 return -EBUSY;
2264 }
2265
2266 ret = dmar_ir_hotplug(dmaru, false);
2267 if (ret == 0)
2268 ret = dmar_iommu_hotplug(dmaru, false);
2269
2270 return ret;
2271 }
2272
dmar_hp_release_drhd(struct acpi_dmar_header * header,void * arg)2273 static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg)
2274 {
2275 struct dmar_drhd_unit *dmaru;
2276
2277 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2278 if (dmaru) {
2279 list_del_rcu(&dmaru->list);
2280 synchronize_rcu();
2281 dmar_free_drhd(dmaru);
2282 }
2283
2284 return 0;
2285 }
2286
dmar_hotplug_insert(acpi_handle handle)2287 static int dmar_hotplug_insert(acpi_handle handle)
2288 {
2289 int ret;
2290 int drhd_count = 0;
2291
2292 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2293 &dmar_validate_one_drhd, (void *)1);
2294 if (ret)
2295 goto out;
2296
2297 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2298 &dmar_parse_one_drhd, (void *)&drhd_count);
2299 if (ret == 0 && drhd_count == 0) {
2300 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n");
2301 goto out;
2302 } else if (ret) {
2303 goto release_drhd;
2304 }
2305
2306 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA,
2307 &dmar_parse_one_rhsa, NULL);
2308 if (ret)
2309 goto release_drhd;
2310
2311 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2312 &dmar_parse_one_atsr, NULL);
2313 if (ret)
2314 goto release_atsr;
2315
2316 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2317 &dmar_hp_add_drhd, NULL);
2318 if (!ret)
2319 return 0;
2320
2321 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2322 &dmar_hp_remove_drhd, NULL);
2323 release_atsr:
2324 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2325 &dmar_release_one_atsr, NULL);
2326 release_drhd:
2327 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2328 &dmar_hp_release_drhd, NULL);
2329 out:
2330 return ret;
2331 }
2332
dmar_hotplug_remove(acpi_handle handle)2333 static int dmar_hotplug_remove(acpi_handle handle)
2334 {
2335 int ret;
2336
2337 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2338 &dmar_check_one_atsr, NULL);
2339 if (ret)
2340 return ret;
2341
2342 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2343 &dmar_hp_remove_drhd, NULL);
2344 if (ret == 0) {
2345 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2346 &dmar_release_one_atsr, NULL));
2347 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2348 &dmar_hp_release_drhd, NULL));
2349 } else {
2350 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2351 &dmar_hp_add_drhd, NULL);
2352 }
2353
2354 return ret;
2355 }
2356
dmar_get_dsm_handle(acpi_handle handle,u32 lvl,void * context,void ** retval)2357 static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl,
2358 void *context, void **retval)
2359 {
2360 acpi_handle *phdl = retval;
2361
2362 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2363 *phdl = handle;
2364 return AE_CTRL_TERMINATE;
2365 }
2366
2367 return AE_OK;
2368 }
2369
dmar_device_hotplug(acpi_handle handle,bool insert)2370 static int dmar_device_hotplug(acpi_handle handle, bool insert)
2371 {
2372 int ret;
2373 acpi_handle tmp = NULL;
2374 acpi_status status;
2375
2376 if (!dmar_in_use())
2377 return 0;
2378
2379 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2380 tmp = handle;
2381 } else {
2382 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,
2383 ACPI_UINT32_MAX,
2384 dmar_get_dsm_handle,
2385 NULL, NULL, &tmp);
2386 if (ACPI_FAILURE(status)) {
2387 pr_warn("Failed to locate _DSM method.\n");
2388 return -ENXIO;
2389 }
2390 }
2391 if (tmp == NULL)
2392 return 0;
2393
2394 down_write(&dmar_global_lock);
2395 if (insert)
2396 ret = dmar_hotplug_insert(tmp);
2397 else
2398 ret = dmar_hotplug_remove(tmp);
2399 up_write(&dmar_global_lock);
2400
2401 return ret;
2402 }
2403
dmar_device_add(acpi_handle handle)2404 int dmar_device_add(acpi_handle handle)
2405 {
2406 return dmar_device_hotplug(handle, true);
2407 }
2408
dmar_device_remove(acpi_handle handle)2409 int dmar_device_remove(acpi_handle handle)
2410 {
2411 return dmar_device_hotplug(handle, false);
2412 }
2413
2414 /*
2415 * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table
2416 *
2417 * Returns true if the platform has %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in
2418 * the ACPI DMAR table. This means that the platform boot firmware has made
2419 * sure no device can issue DMA outside of RMRR regions.
2420 */
dmar_platform_optin(void)2421 bool dmar_platform_optin(void)
2422 {
2423 struct acpi_table_dmar *dmar;
2424 acpi_status status;
2425 bool ret;
2426
2427 status = acpi_get_table(ACPI_SIG_DMAR, 0,
2428 (struct acpi_table_header **)&dmar);
2429 if (ACPI_FAILURE(status))
2430 return false;
2431
2432 ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN);
2433 acpi_put_table((struct acpi_table_header *)dmar);
2434
2435 return ret;
2436 }
2437 EXPORT_SYMBOL_GPL(dmar_platform_optin);
2438