1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef DMUB_CMD_H
27 #define DMUB_CMD_H
28
29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4)
30 #include "dmub_fw_types.h"
31 #include "include_legacy/atomfirmware.h"
32
33 #if defined(_TEST_HARNESS)
34 #include <string.h>
35 #endif
36 #else
37
38 #include <asm/byteorder.h>
39 #include <linux/types.h>
40 #include <linux/string.h>
41 #include <linux/delay.h>
42
43 #include "atomfirmware.h"
44
45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4)
46
47 //<DMUB_TYPES>==================================================================
48 /* Basic type definitions. */
49
50 #define __forceinline inline
51
52 /**
53 * Flag from driver to indicate that ABM should be disabled gradually
54 * by slowly reversing all backlight programming and pixel compensation.
55 */
56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
57
58 /**
59 * Flag from driver to indicate that ABM should be disabled immediately
60 * and undo all backlight programming and pixel compensation.
61 */
62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
63
64 /**
65 * Flag from driver to indicate that ABM should be disabled immediately
66 * and keep the current backlight programming and pixel compensation.
67 */
68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
69
70 /**
71 * Flag from driver to set the current ABM pipe index or ABM operating level.
72 */
73 #define SET_ABM_PIPE_NORMAL 1
74
75 /**
76 * Number of ambient light levels in ABM algorithm.
77 */
78 #define NUM_AMBI_LEVEL 5
79
80 /**
81 * Number of operating/aggression levels in ABM algorithm.
82 */
83 #define NUM_AGGR_LEVEL 4
84
85 /**
86 * Number of segments in the gamma curve.
87 */
88 #define NUM_POWER_FN_SEGS 8
89
90 /**
91 * Number of segments in the backlight curve.
92 */
93 #define NUM_BL_CURVE_SEGS 16
94
95 /* Maximum number of SubVP streams */
96 #define DMUB_MAX_SUBVP_STREAMS 2
97
98 /* Maximum number of streams on any ASIC. */
99 #define DMUB_MAX_STREAMS 6
100
101 /* Maximum number of planes on any ASIC. */
102 #define DMUB_MAX_PLANES 6
103
104 /* Trace buffer offset for entry */
105 #define TRACE_BUFFER_ENTRY_OFFSET 16
106
107 /**
108 * Maximum number of dirty rects supported by FW.
109 */
110 #define DMUB_MAX_DIRTY_RECTS 3
111
112 /**
113 *
114 * PSR control version legacy
115 */
116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
117 /**
118 * PSR control version with multi edp support
119 */
120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
121
122
123 /**
124 * ABM control version legacy
125 */
126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
127
128 /**
129 * ABM control version with multi edp support
130 */
131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
132
133 /**
134 * Physical framebuffer address location, 64-bit.
135 */
136 #ifndef PHYSICAL_ADDRESS_LOC
137 #define PHYSICAL_ADDRESS_LOC union large_integer
138 #endif
139
140 /**
141 * OS/FW agnostic memcpy
142 */
143 #ifndef dmub_memcpy
144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
145 #endif
146
147 /**
148 * OS/FW agnostic memset
149 */
150 #ifndef dmub_memset
151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
152 #endif
153
154 #if defined(__cplusplus)
155 extern "C" {
156 #endif
157
158 /**
159 * OS/FW agnostic udelay
160 */
161 #ifndef dmub_udelay
162 #define dmub_udelay(microseconds) udelay(microseconds)
163 #endif
164
165 /**
166 * union dmub_addr - DMUB physical/virtual 64-bit address.
167 */
168 union dmub_addr {
169 struct {
170 uint32_t low_part; /**< Lower 32 bits */
171 uint32_t high_part; /**< Upper 32 bits */
172 } u; /*<< Low/high bit access */
173 uint64_t quad_part; /*<< 64 bit address */
174 };
175
176 /**
177 * Dirty rect definition.
178 */
179 struct dmub_rect {
180 /**
181 * Dirty rect x offset.
182 */
183 uint32_t x;
184
185 /**
186 * Dirty rect y offset.
187 */
188 uint32_t y;
189
190 /**
191 * Dirty rect width.
192 */
193 uint32_t width;
194
195 /**
196 * Dirty rect height.
197 */
198 uint32_t height;
199 };
200
201 /**
202 * Flags that can be set by driver to change some PSR behaviour.
203 */
204 union dmub_psr_debug_flags {
205 /**
206 * Debug flags.
207 */
208 struct {
209 /**
210 * Enable visual confirm in FW.
211 */
212 uint32_t visual_confirm : 1;
213
214 /**
215 * Force all selective updates to bw full frame updates.
216 */
217 uint32_t force_full_frame_update : 1;
218
219 /**
220 * Use HW Lock Mgr object to do HW locking in FW.
221 */
222 uint32_t use_hw_lock_mgr : 1;
223
224 /**
225 * Use TPS3 signal when restore main link.
226 */
227 uint32_t force_wakeup_by_tps3 : 1;
228 } bitfields;
229
230 /**
231 * Union for debug flags.
232 */
233 uint32_t u32All;
234 };
235
236 /**
237 * DMUB visual confirm color
238 */
239 struct dmub_feature_caps {
240 /**
241 * Max PSR version supported by FW.
242 */
243 uint8_t psr;
244 uint8_t fw_assisted_mclk_switch;
245 uint8_t reserved[6];
246 };
247
248 struct dmub_visual_confirm_color {
249 /**
250 * Maximum 10 bits color value
251 */
252 uint16_t color_r_cr;
253 uint16_t color_g_y;
254 uint16_t color_b_cb;
255 uint16_t panel_inst;
256 };
257
258 #if defined(__cplusplus)
259 }
260 #endif
261
262 //==============================================================================
263 //</DMUB_TYPES>=================================================================
264 //==============================================================================
265 //< DMUB_META>==================================================================
266 //==============================================================================
267 #pragma pack(push, 1)
268
269 /* Magic value for identifying dmub_fw_meta_info */
270 #define DMUB_FW_META_MAGIC 0x444D5542
271
272 /* Offset from the end of the file to the dmub_fw_meta_info */
273 #define DMUB_FW_META_OFFSET 0x24
274
275 /**
276 * struct dmub_fw_meta_info - metadata associated with fw binary
277 *
278 * NOTE: This should be considered a stable API. Fields should
279 * not be repurposed or reordered. New fields should be
280 * added instead to extend the structure.
281 *
282 * @magic_value: magic value identifying DMUB firmware meta info
283 * @fw_region_size: size of the firmware state region
284 * @trace_buffer_size: size of the tracebuffer region
285 * @fw_version: the firmware version information
286 * @dal_fw: 1 if the firmware is DAL
287 */
288 struct dmub_fw_meta_info {
289 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
290 uint32_t fw_region_size; /**< size of the firmware state region */
291 uint32_t trace_buffer_size; /**< size of the tracebuffer region */
292 uint32_t fw_version; /**< the firmware version information */
293 uint8_t dal_fw; /**< 1 if the firmware is DAL */
294 uint8_t reserved[3]; /**< padding bits */
295 };
296
297 /**
298 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
299 */
300 union dmub_fw_meta {
301 struct dmub_fw_meta_info info; /**< metadata info */
302 uint8_t reserved[64]; /**< padding bits */
303 };
304
305 #pragma pack(pop)
306
307 //==============================================================================
308 //< DMUB Trace Buffer>================================================================
309 //==============================================================================
310 /**
311 * dmub_trace_code_t - firmware trace code, 32-bits
312 */
313 typedef uint32_t dmub_trace_code_t;
314
315 /**
316 * struct dmcub_trace_buf_entry - Firmware trace entry
317 */
318 struct dmcub_trace_buf_entry {
319 dmub_trace_code_t trace_code; /**< trace code for the event */
320 uint32_t tick_count; /**< the tick count at time of trace */
321 uint32_t param0; /**< trace defined parameter 0 */
322 uint32_t param1; /**< trace defined parameter 1 */
323 };
324
325 //==============================================================================
326 //< DMUB_STATUS>================================================================
327 //==============================================================================
328
329 /**
330 * DMCUB scratch registers can be used to determine firmware status.
331 * Current scratch register usage is as follows:
332 *
333 * SCRATCH0: FW Boot Status register
334 * SCRATCH5: LVTMA Status Register
335 * SCRATCH15: FW Boot Options register
336 */
337
338 /**
339 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
340 */
341 union dmub_fw_boot_status {
342 struct {
343 uint32_t dal_fw : 1; /**< 1 if DAL FW */
344 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
345 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
346 uint32_t restore_required : 1; /**< 1 if driver should call restore */
347 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
348 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
349 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
350
351 } bits; /**< status bits */
352 uint32_t all; /**< 32-bit access to status bits */
353 };
354
355 /**
356 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
357 */
358 enum dmub_fw_boot_status_bit {
359 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
360 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
361 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
362 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
363 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
364 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
365 };
366
367 /* Register bit definition for SCRATCH5 */
368 union dmub_lvtma_status {
369 struct {
370 uint32_t psp_ok : 1;
371 uint32_t edp_on : 1;
372 uint32_t reserved : 30;
373 } bits;
374 uint32_t all;
375 };
376
377 enum dmub_lvtma_status_bit {
378 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
379 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
380 };
381
382 /**
383 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
384 */
385 union dmub_fw_boot_options {
386 struct {
387 uint32_t pemu_env : 1; /**< 1 if PEMU */
388 uint32_t fpga_env : 1; /**< 1 if FPGA */
389 uint32_t optimized_init : 1; /**< 1 if optimized init */
390 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
391 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
392 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
393 uint32_t z10_disable: 1; /**< 1 to disable z10 */
394 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
395 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
396 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
397 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */
398 /**< 1 if all root clock gating is enabled and low power memory is enabled*/
399 uint32_t power_optimization: 1;
400 uint32_t diag_env: 1; /* 1 if diagnostic environment */
401 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
402 uint32_t usb4_cm_version: 1; /**< 1 CM support */
403 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */
404
405 uint32_t reserved : 16; /**< reserved */
406 } bits; /**< boot bits */
407 uint32_t all; /**< 32-bit access to bits */
408 };
409
410 enum dmub_fw_boot_options_bit {
411 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
412 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
413 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
414 };
415
416 //==============================================================================
417 //</DMUB_STATUS>================================================================
418 //==============================================================================
419 //< DMUB_VBIOS>=================================================================
420 //==============================================================================
421
422 /*
423 * enum dmub_cmd_vbios_type - VBIOS commands.
424 *
425 * Command IDs should be treated as stable ABI.
426 * Do not reuse or modify IDs.
427 */
428 enum dmub_cmd_vbios_type {
429 /**
430 * Configures the DIG encoder.
431 */
432 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
433 /**
434 * Controls the PHY.
435 */
436 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
437 /**
438 * Sets the pixel clock/symbol clock.
439 */
440 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
441 /**
442 * Enables or disables power gating.
443 */
444 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
445 /**
446 * Controls embedded panels.
447 */
448 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
449 /**
450 * Query DP alt status on a transmitter.
451 */
452 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26,
453 /**
454 * Controls domain power gating
455 */
456 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,
457 };
458
459 //==============================================================================
460 //</DMUB_VBIOS>=================================================================
461 //==============================================================================
462 //< DMUB_GPINT>=================================================================
463 //==============================================================================
464
465 /**
466 * The shifts and masks below may alternatively be used to format and read
467 * the command register bits.
468 */
469
470 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
471 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
472
473 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
474 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
475
476 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
477 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
478
479 /**
480 * Command responses.
481 */
482
483 /**
484 * Return response for DMUB_GPINT__STOP_FW command.
485 */
486 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
487
488 /**
489 * union dmub_gpint_data_register - Format for sending a command via the GPINT.
490 */
491 union dmub_gpint_data_register {
492 struct {
493 uint32_t param : 16; /**< 16-bit parameter */
494 uint32_t command_code : 12; /**< GPINT command */
495 uint32_t status : 4; /**< Command status bit */
496 } bits; /**< GPINT bit access */
497 uint32_t all; /**< GPINT 32-bit access */
498 };
499
500 /*
501 * enum dmub_gpint_command - GPINT command to DMCUB FW
502 *
503 * Command IDs should be treated as stable ABI.
504 * Do not reuse or modify IDs.
505 */
506 enum dmub_gpint_command {
507 /**
508 * Invalid command, ignored.
509 */
510 DMUB_GPINT__INVALID_COMMAND = 0,
511 /**
512 * DESC: Queries the firmware version.
513 * RETURN: Firmware version.
514 */
515 DMUB_GPINT__GET_FW_VERSION = 1,
516 /**
517 * DESC: Halts the firmware.
518 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
519 */
520 DMUB_GPINT__STOP_FW = 2,
521 /**
522 * DESC: Get PSR state from FW.
523 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
524 */
525 DMUB_GPINT__GET_PSR_STATE = 7,
526 /**
527 * DESC: Notifies DMCUB of the currently active streams.
528 * ARGS: Stream mask, 1 bit per active stream index.
529 */
530 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
531 /**
532 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
533 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
534 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
535 * RETURN: PSR residency in milli-percent.
536 */
537 DMUB_GPINT__PSR_RESIDENCY = 9,
538
539 /**
540 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
541 */
542 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
543 };
544
545 /**
546 * INBOX0 generic command definition
547 */
548 union dmub_inbox0_cmd_common {
549 struct {
550 uint32_t command_code: 8; /**< INBOX0 command code */
551 uint32_t param: 24; /**< 24-bit parameter */
552 } bits;
553 uint32_t all;
554 };
555
556 /**
557 * INBOX0 hw_lock command definition
558 */
559 union dmub_inbox0_cmd_lock_hw {
560 struct {
561 uint32_t command_code: 8;
562
563 /* NOTE: Must be have enough bits to match: enum hw_lock_client */
564 uint32_t hw_lock_client: 2;
565
566 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
567 uint32_t otg_inst: 3;
568 uint32_t opp_inst: 3;
569 uint32_t dig_inst: 3;
570
571 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */
572 uint32_t lock_pipe: 1;
573 uint32_t lock_cursor: 1;
574 uint32_t lock_dig: 1;
575 uint32_t triple_buffer_lock: 1;
576
577 uint32_t lock: 1; /**< Lock */
578 uint32_t should_release: 1; /**< Release */
579 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */
580 } bits;
581 uint32_t all;
582 };
583
584 union dmub_inbox0_data_register {
585 union dmub_inbox0_cmd_common inbox0_cmd_common;
586 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
587 };
588
589 enum dmub_inbox0_command {
590 /**
591 * DESC: Invalid command, ignored.
592 */
593 DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
594 /**
595 * DESC: Notification to acquire/release HW lock
596 * ARGS:
597 */
598 DMUB_INBOX0_CMD__HW_LOCK = 1,
599 };
600 //==============================================================================
601 //</DMUB_GPINT>=================================================================
602 //==============================================================================
603 //< DMUB_CMD>===================================================================
604 //==============================================================================
605
606 /**
607 * Size in bytes of each DMUB command.
608 */
609 #define DMUB_RB_CMD_SIZE 64
610
611 /**
612 * Maximum number of items in the DMUB ringbuffer.
613 */
614 #define DMUB_RB_MAX_ENTRY 128
615
616 /**
617 * Ringbuffer size in bytes.
618 */
619 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
620
621 /**
622 * REG_SET mask for reg offload.
623 */
624 #define REG_SET_MASK 0xFFFF
625
626 /*
627 * enum dmub_cmd_type - DMUB inbox command.
628 *
629 * Command IDs should be treated as stable ABI.
630 * Do not reuse or modify IDs.
631 */
632 enum dmub_cmd_type {
633 /**
634 * Invalid command.
635 */
636 DMUB_CMD__NULL = 0,
637 /**
638 * Read modify write register sequence offload.
639 */
640 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
641 /**
642 * Field update register sequence offload.
643 */
644 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
645 /**
646 * Burst write sequence offload.
647 */
648 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
649 /**
650 * Reg wait sequence offload.
651 */
652 DMUB_CMD__REG_REG_WAIT = 4,
653 /**
654 * Workaround to avoid HUBP underflow during NV12 playback.
655 */
656 DMUB_CMD__PLAT_54186_WA = 5,
657 /**
658 * Command type used to query FW feature caps.
659 */
660 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
661 /**
662 * Command type used to get visual confirm color.
663 */
664 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
665 /**
666 * Command type used for all PSR commands.
667 */
668 DMUB_CMD__PSR = 64,
669 /**
670 * Command type used for all MALL commands.
671 */
672 DMUB_CMD__MALL = 65,
673 /**
674 * Command type used for all ABM commands.
675 */
676 DMUB_CMD__ABM = 66,
677 /**
678 * Command type used to update dirty rects in FW.
679 */
680 DMUB_CMD__UPDATE_DIRTY_RECT = 67,
681 /**
682 * Command type used to update cursor info in FW.
683 */
684 DMUB_CMD__UPDATE_CURSOR_INFO = 68,
685 /**
686 * Command type used for HW locking in FW.
687 */
688 DMUB_CMD__HW_LOCK = 69,
689 /**
690 * Command type used to access DP AUX.
691 */
692 DMUB_CMD__DP_AUX_ACCESS = 70,
693 /**
694 * Command type used for OUTBOX1 notification enable
695 */
696 DMUB_CMD__OUTBOX1_ENABLE = 71,
697
698 /**
699 * Command type used for all idle optimization commands.
700 */
701 DMUB_CMD__IDLE_OPT = 72,
702 /**
703 * Command type used for all clock manager commands.
704 */
705 DMUB_CMD__CLK_MGR = 73,
706 /**
707 * Command type used for all panel control commands.
708 */
709 DMUB_CMD__PANEL_CNTL = 74,
710 /**
711 * Command type used for <TODO:description>
712 */
713 DMUB_CMD__CAB_FOR_SS = 75,
714
715 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,
716
717 /**
718 * Command type used for interfacing with DPIA.
719 */
720 DMUB_CMD__DPIA = 77,
721 /**
722 * Command type used for EDID CEA parsing
723 */
724 DMUB_CMD__EDID_CEA = 79,
725 /**
726 * Command type used for getting usbc cable ID
727 */
728 DMUB_CMD_GET_USBC_CABLE_ID = 81,
729 /**
730 * Command type used to query HPD state.
731 */
732 DMUB_CMD__QUERY_HPD_STATE = 82,
733 /**
734 * Command type used for all VBIOS interface commands.
735 */
736
737 /**
738 * Command type used to set DPIA HPD interrupt state
739 */
740 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
741
742 DMUB_CMD__VBIOS = 128,
743 };
744
745 /**
746 * enum dmub_out_cmd_type - DMUB outbox commands.
747 */
748 enum dmub_out_cmd_type {
749 /**
750 * Invalid outbox command, ignored.
751 */
752 DMUB_OUT_CMD__NULL = 0,
753 /**
754 * Command type used for DP AUX Reply data notification
755 */
756 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
757 /**
758 * Command type used for DP HPD event notification
759 */
760 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
761 /**
762 * Command type used for SET_CONFIG Reply notification
763 */
764 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
765 };
766
767 /* DMUB_CMD__DPIA command sub-types. */
768 enum dmub_cmd_dpia_type {
769 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
770 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1,
771 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,
772 };
773
774 #pragma pack(push, 1)
775
776 /**
777 * struct dmub_cmd_header - Common command header fields.
778 */
779 struct dmub_cmd_header {
780 unsigned int type : 8; /**< command type */
781 unsigned int sub_type : 8; /**< command sub type */
782 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
783 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
784 unsigned int reserved0 : 6; /**< reserved bits */
785 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
786 unsigned int reserved1 : 2; /**< reserved bits */
787 };
788
789 /*
790 * struct dmub_cmd_read_modify_write_sequence - Read modify write
791 *
792 * 60 payload bytes can hold up to 5 sets of read modify writes,
793 * each take 3 dwords.
794 *
795 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
796 *
797 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
798 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
799 */
800 struct dmub_cmd_read_modify_write_sequence {
801 uint32_t addr; /**< register address */
802 uint32_t modify_mask; /**< modify mask */
803 uint32_t modify_value; /**< modify value */
804 };
805
806 /**
807 * Maximum number of ops in read modify write sequence.
808 */
809 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
810
811 /**
812 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
813 */
814 struct dmub_rb_cmd_read_modify_write {
815 struct dmub_cmd_header header; /**< command header */
816 /**
817 * Read modify write sequence.
818 */
819 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
820 };
821
822 /*
823 * Update a register with specified masks and values sequeunce
824 *
825 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
826 *
827 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
828 *
829 *
830 * USE CASE:
831 * 1. auto-increment register where additional read would update pointer and produce wrong result
832 * 2. toggle a bit without read in the middle
833 */
834
835 struct dmub_cmd_reg_field_update_sequence {
836 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
837 uint32_t modify_value; /**< value to update with */
838 };
839
840 /**
841 * Maximum number of ops in field update sequence.
842 */
843 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
844
845 /**
846 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
847 */
848 struct dmub_rb_cmd_reg_field_update_sequence {
849 struct dmub_cmd_header header; /**< command header */
850 uint32_t addr; /**< register address */
851 /**
852 * Field update sequence.
853 */
854 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
855 };
856
857
858 /**
859 * Maximum number of burst write values.
860 */
861 #define DMUB_BURST_WRITE_VALUES__MAX 14
862
863 /*
864 * struct dmub_rb_cmd_burst_write - Burst write
865 *
866 * support use case such as writing out LUTs.
867 *
868 * 60 payload bytes can hold up to 14 values to write to given address
869 *
870 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
871 */
872 struct dmub_rb_cmd_burst_write {
873 struct dmub_cmd_header header; /**< command header */
874 uint32_t addr; /**< register start address */
875 /**
876 * Burst write register values.
877 */
878 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
879 };
880
881 /**
882 * struct dmub_rb_cmd_common - Common command header
883 */
884 struct dmub_rb_cmd_common {
885 struct dmub_cmd_header header; /**< command header */
886 /**
887 * Padding to RB_CMD_SIZE
888 */
889 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
890 };
891
892 /**
893 * struct dmub_cmd_reg_wait_data - Register wait data
894 */
895 struct dmub_cmd_reg_wait_data {
896 uint32_t addr; /**< Register address */
897 uint32_t mask; /**< Mask for register bits */
898 uint32_t condition_field_value; /**< Value to wait for */
899 uint32_t time_out_us; /**< Time out for reg wait in microseconds */
900 };
901
902 /**
903 * struct dmub_rb_cmd_reg_wait - Register wait command
904 */
905 struct dmub_rb_cmd_reg_wait {
906 struct dmub_cmd_header header; /**< Command header */
907 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
908 };
909
910 /**
911 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
912 *
913 * Reprograms surface parameters to avoid underflow.
914 */
915 struct dmub_cmd_PLAT_54186_wa {
916 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
917 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
918 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
919 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
920 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
921 struct {
922 uint8_t hubp_inst : 4; /**< HUBP instance */
923 uint8_t tmz_surface : 1; /**< TMZ enable or disable */
924 uint8_t immediate :1; /**< Immediate flip */
925 uint8_t vmid : 4; /**< VMID */
926 uint8_t grph_stereo : 1; /**< 1 if stereo */
927 uint32_t reserved : 21; /**< Reserved */
928 } flip_params; /**< Pageflip parameters */
929 uint32_t reserved[9]; /**< Reserved bits */
930 };
931
932 /**
933 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
934 */
935 struct dmub_rb_cmd_PLAT_54186_wa {
936 struct dmub_cmd_header header; /**< Command header */
937 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
938 };
939
940 /**
941 * struct dmub_rb_cmd_mall - MALL command data.
942 */
943 struct dmub_rb_cmd_mall {
944 struct dmub_cmd_header header; /**< Common command header */
945 union dmub_addr cursor_copy_src; /**< Cursor copy address */
946 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
947 uint32_t tmr_delay; /**< Timer delay */
948 uint32_t tmr_scale; /**< Timer scale */
949 uint16_t cursor_width; /**< Cursor width in pixels */
950 uint16_t cursor_pitch; /**< Cursor pitch in pixels */
951 uint16_t cursor_height; /**< Cursor height in pixels */
952 uint8_t cursor_bpp; /**< Cursor bits per pixel */
953 uint8_t debug_bits; /**< Debug bits */
954
955 uint8_t reserved1; /**< Reserved bits */
956 uint8_t reserved2; /**< Reserved bits */
957 };
958
959 /**
960 * enum dmub_cmd_cab_type - TODO:
961 */
962 enum dmub_cmd_cab_type {
963 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
964 DMUB_CMD__CAB_NO_DCN_REQ = 1,
965 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
966 };
967
968 /**
969 * struct dmub_rb_cmd_cab_for_ss - TODO:
970 */
971 struct dmub_rb_cmd_cab_for_ss {
972 struct dmub_cmd_header header;
973 uint8_t cab_alloc_ways; /* total number of ways */
974 uint8_t debug_bits; /* debug bits */
975 };
976
977 enum mclk_switch_mode {
978 NONE = 0,
979 FPO = 1,
980 SUBVP = 2,
981 VBLANK = 3,
982 };
983
984 /* Per pipe struct which stores the MCLK switch mode
985 * data to be sent to DMUB.
986 * Named "v2" for now -- once FPO and SUBVP are fully merged
987 * the type name can be updated
988 */
989 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {
990 union {
991 struct {
992 uint32_t pix_clk_100hz;
993 uint16_t main_vblank_start;
994 uint16_t main_vblank_end;
995 uint16_t mall_region_lines;
996 uint16_t prefetch_lines;
997 uint16_t prefetch_to_mall_start_lines;
998 uint16_t processing_delay_lines;
999 uint16_t htotal; // required to calculate line time for multi-display cases
1000 uint16_t vtotal;
1001 uint8_t main_pipe_index;
1002 uint8_t phantom_pipe_index;
1003 /* Since the microschedule is calculated in terms of OTG lines,
1004 * include any scaling factors to make sure when we get accurate
1005 * conversion when programming MALL_START_LINE (which is in terms
1006 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor
1007 * is 1/2 (numerator = 1, denominator = 2).
1008 */
1009 uint8_t scale_factor_numerator;
1010 uint8_t scale_factor_denominator;
1011 uint8_t is_drr;
1012 uint8_t main_split_pipe_index;
1013 uint8_t phantom_split_pipe_index;
1014 } subvp_data;
1015
1016 struct {
1017 uint32_t pix_clk_100hz;
1018 uint16_t vblank_start;
1019 uint16_t vblank_end;
1020 uint16_t vstartup_start;
1021 uint16_t vtotal;
1022 uint16_t htotal;
1023 uint8_t vblank_pipe_index;
1024 uint8_t padding[2];
1025 struct {
1026 uint8_t drr_in_use;
1027 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame
1028 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK
1029 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling
1030 uint8_t use_ramping; // Use ramping or not
1031 } drr_info; // DRR considered as part of SubVP + VBLANK case
1032 } vblank_data;
1033 } pipe_config;
1034
1035 /* - subvp_data in the union (pipe_config) takes up 27 bytes.
1036 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only
1037 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state).
1038 */
1039 uint8_t mode; // enum mclk_switch_mode
1040 };
1041
1042 /**
1043 * Config data for Sub-VP and FPO
1044 * Named "v2" for now -- once FPO and SUBVP are fully merged
1045 * the type name can be updated
1046 */
1047 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {
1048 uint16_t watermark_a_cache;
1049 uint8_t vertical_int_margin_us;
1050 uint8_t pstate_allow_width_us;
1051 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];
1052 };
1053
1054 /**
1055 * DMUB rb command definition for Sub-VP and FPO
1056 * Named "v2" for now -- once FPO and SUBVP are fully merged
1057 * the type name can be updated
1058 */
1059 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {
1060 struct dmub_cmd_header header;
1061 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;
1062 };
1063
1064 /**
1065 * enum dmub_cmd_idle_opt_type - Idle optimization command type.
1066 */
1067 enum dmub_cmd_idle_opt_type {
1068 /**
1069 * DCN hardware restore.
1070 */
1071 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
1072
1073 /**
1074 * DCN hardware save.
1075 */
1076 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1
1077 };
1078
1079 /**
1080 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
1081 */
1082 struct dmub_rb_cmd_idle_opt_dcn_restore {
1083 struct dmub_cmd_header header; /**< header */
1084 };
1085
1086 /**
1087 * struct dmub_clocks - Clock update notification.
1088 */
1089 struct dmub_clocks {
1090 uint32_t dispclk_khz; /**< dispclk kHz */
1091 uint32_t dppclk_khz; /**< dppclk kHz */
1092 uint32_t dcfclk_khz; /**< dcfclk kHz */
1093 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
1094 };
1095
1096 /**
1097 * enum dmub_cmd_clk_mgr_type - Clock manager commands.
1098 */
1099 enum dmub_cmd_clk_mgr_type {
1100 /**
1101 * Notify DMCUB of clock update.
1102 */
1103 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
1104 };
1105
1106 /**
1107 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
1108 */
1109 struct dmub_rb_cmd_clk_mgr_notify_clocks {
1110 struct dmub_cmd_header header; /**< header */
1111 struct dmub_clocks clocks; /**< clock data */
1112 };
1113
1114 /**
1115 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
1116 */
1117 struct dmub_cmd_digx_encoder_control_data {
1118 union dig_encoder_control_parameters_v1_5 dig; /**< payload */
1119 };
1120
1121 /**
1122 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
1123 */
1124 struct dmub_rb_cmd_digx_encoder_control {
1125 struct dmub_cmd_header header; /**< header */
1126 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
1127 };
1128
1129 /**
1130 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
1131 */
1132 struct dmub_cmd_set_pixel_clock_data {
1133 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
1134 };
1135
1136 /**
1137 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
1138 */
1139 struct dmub_rb_cmd_set_pixel_clock {
1140 struct dmub_cmd_header header; /**< header */
1141 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
1142 };
1143
1144 /**
1145 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
1146 */
1147 struct dmub_cmd_enable_disp_power_gating_data {
1148 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
1149 };
1150
1151 /**
1152 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
1153 */
1154 struct dmub_rb_cmd_enable_disp_power_gating {
1155 struct dmub_cmd_header header; /**< header */
1156 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
1157 };
1158
1159 /**
1160 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
1161 */
1162 struct dmub_dig_transmitter_control_data_v1_7 {
1163 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
1164 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
1165 union {
1166 uint8_t digmode; /**< enum atom_encode_mode_def */
1167 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
1168 } mode_laneset;
1169 uint8_t lanenum; /**< Number of lanes */
1170 union {
1171 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
1172 } symclk_units;
1173 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
1174 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
1175 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
1176 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */
1177 uint8_t reserved1; /**< For future use */
1178 uint8_t reserved2[3]; /**< For future use */
1179 uint32_t reserved3[11]; /**< For future use */
1180 };
1181
1182 /**
1183 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
1184 */
1185 union dmub_cmd_dig1_transmitter_control_data {
1186 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
1187 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
1188 };
1189
1190 /**
1191 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
1192 */
1193 struct dmub_rb_cmd_dig1_transmitter_control {
1194 struct dmub_cmd_header header; /**< header */
1195 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
1196 };
1197
1198 /**
1199 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control
1200 */
1201 struct dmub_rb_cmd_domain_control_data {
1202 uint8_t inst : 6; /**< DOMAIN instance to control */
1203 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */
1204 uint8_t reserved[3]; /**< Reserved for future use */
1205 };
1206
1207 /**
1208 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating
1209 */
1210 struct dmub_rb_cmd_domain_control {
1211 struct dmub_cmd_header header; /**< header */
1212 struct dmub_rb_cmd_domain_control_data data; /**< payload */
1213 };
1214
1215 /**
1216 * DPIA tunnel command parameters.
1217 */
1218 struct dmub_cmd_dig_dpia_control_data {
1219 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */
1220 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */
1221 union {
1222 uint8_t digmode; /** enum atom_encode_mode_def */
1223 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */
1224 } mode_laneset;
1225 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */
1226 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */
1227 uint8_t hpdsel; /** =0: HPD is not assigned */
1228 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */
1229 uint8_t dpia_id; /** Index of DPIA */
1230 uint8_t fec_rdy : 1;
1231 uint8_t reserved : 7;
1232 uint32_t reserved1;
1233 };
1234
1235 /**
1236 * DMUB command for DPIA tunnel control.
1237 */
1238 struct dmub_rb_cmd_dig1_dpia_control {
1239 struct dmub_cmd_header header;
1240 struct dmub_cmd_dig_dpia_control_data dpia_control;
1241 };
1242
1243 /**
1244 * SET_CONFIG Command Payload
1245 */
1246 struct set_config_cmd_payload {
1247 uint8_t msg_type; /* set config message type */
1248 uint8_t msg_data; /* set config message data */
1249 };
1250
1251 /**
1252 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
1253 */
1254 struct dmub_cmd_set_config_control_data {
1255 struct set_config_cmd_payload cmd_pkt;
1256 uint8_t instance; /* DPIA instance */
1257 uint8_t immed_status; /* Immediate status returned in case of error */
1258 };
1259
1260 /**
1261 * DMUB command structure for SET_CONFIG command.
1262 */
1263 struct dmub_rb_cmd_set_config_access {
1264 struct dmub_cmd_header header; /* header */
1265 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */
1266 };
1267
1268 /**
1269 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
1270 */
1271 struct dmub_cmd_mst_alloc_slots_control_data {
1272 uint8_t mst_alloc_slots; /* mst slots to be allotted */
1273 uint8_t instance; /* DPIA instance */
1274 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */
1275 uint8_t mst_slots_in_use; /* returns slots in use for error cases */
1276 };
1277
1278 /**
1279 * DMUB command structure for SET_ command.
1280 */
1281 struct dmub_rb_cmd_set_mst_alloc_slots {
1282 struct dmub_cmd_header header; /* header */
1283 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */
1284 };
1285
1286 /**
1287 * DMUB command structure for DPIA HPD int enable control.
1288 */
1289 struct dmub_rb_cmd_dpia_hpd_int_enable {
1290 struct dmub_cmd_header header; /* header */
1291 uint32_t enable; /* dpia hpd interrupt enable */
1292 };
1293
1294 /**
1295 * struct dmub_rb_cmd_dpphy_init - DPPHY init.
1296 */
1297 struct dmub_rb_cmd_dpphy_init {
1298 struct dmub_cmd_header header; /**< header */
1299 uint8_t reserved[60]; /**< reserved bits */
1300 };
1301
1302 /**
1303 * enum dp_aux_request_action - DP AUX request command listing.
1304 *
1305 * 4 AUX request command bits are shifted to high nibble.
1306 */
1307 enum dp_aux_request_action {
1308 /** I2C-over-AUX write request */
1309 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
1310 /** I2C-over-AUX read request */
1311 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
1312 /** I2C-over-AUX write status request */
1313 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
1314 /** I2C-over-AUX write request with MOT=1 */
1315 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
1316 /** I2C-over-AUX read request with MOT=1 */
1317 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
1318 /** I2C-over-AUX write status request with MOT=1 */
1319 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
1320 /** Native AUX write request */
1321 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
1322 /** Native AUX read request */
1323 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
1324 };
1325
1326 /**
1327 * enum aux_return_code_type - DP AUX process return code listing.
1328 */
1329 enum aux_return_code_type {
1330 /** AUX process succeeded */
1331 AUX_RET_SUCCESS = 0,
1332 /** AUX process failed with unknown reason */
1333 AUX_RET_ERROR_UNKNOWN,
1334 /** AUX process completed with invalid reply */
1335 AUX_RET_ERROR_INVALID_REPLY,
1336 /** AUX process timed out */
1337 AUX_RET_ERROR_TIMEOUT,
1338 /** HPD was low during AUX process */
1339 AUX_RET_ERROR_HPD_DISCON,
1340 /** Failed to acquire AUX engine */
1341 AUX_RET_ERROR_ENGINE_ACQUIRE,
1342 /** AUX request not supported */
1343 AUX_RET_ERROR_INVALID_OPERATION,
1344 /** AUX process not available */
1345 AUX_RET_ERROR_PROTOCOL_ERROR,
1346 };
1347
1348 /**
1349 * enum aux_channel_type - DP AUX channel type listing.
1350 */
1351 enum aux_channel_type {
1352 /** AUX thru Legacy DP AUX */
1353 AUX_CHANNEL_LEGACY_DDC,
1354 /** AUX thru DPIA DP tunneling */
1355 AUX_CHANNEL_DPIA
1356 };
1357
1358 /**
1359 * struct aux_transaction_parameters - DP AUX request transaction data
1360 */
1361 struct aux_transaction_parameters {
1362 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
1363 uint8_t action; /**< enum dp_aux_request_action */
1364 uint8_t length; /**< DP AUX request data length */
1365 uint8_t reserved; /**< For future use */
1366 uint32_t address; /**< DP AUX address */
1367 uint8_t data[16]; /**< DP AUX write data */
1368 };
1369
1370 /**
1371 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1372 */
1373 struct dmub_cmd_dp_aux_control_data {
1374 uint8_t instance; /**< AUX instance or DPIA instance */
1375 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
1376 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
1377 uint8_t reserved0; /**< For future use */
1378 uint16_t timeout; /**< timeout time in us */
1379 uint16_t reserved1; /**< For future use */
1380 enum aux_channel_type type; /**< enum aux_channel_type */
1381 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
1382 };
1383
1384 /**
1385 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
1386 */
1387 struct dmub_rb_cmd_dp_aux_access {
1388 /**
1389 * Command header.
1390 */
1391 struct dmub_cmd_header header;
1392 /**
1393 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1394 */
1395 struct dmub_cmd_dp_aux_control_data aux_control;
1396 };
1397
1398 /**
1399 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
1400 */
1401 struct dmub_rb_cmd_outbox1_enable {
1402 /**
1403 * Command header.
1404 */
1405 struct dmub_cmd_header header;
1406 /**
1407 * enable: 0x0 -> disable outbox1 notification (default value)
1408 * 0x1 -> enable outbox1 notification
1409 */
1410 uint32_t enable;
1411 };
1412
1413 /* DP AUX Reply command - OutBox Cmd */
1414 /**
1415 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1416 */
1417 struct aux_reply_data {
1418 /**
1419 * Aux cmd
1420 */
1421 uint8_t command;
1422 /**
1423 * Aux reply data length (max: 16 bytes)
1424 */
1425 uint8_t length;
1426 /**
1427 * Alignment only
1428 */
1429 uint8_t pad[2];
1430 /**
1431 * Aux reply data
1432 */
1433 uint8_t data[16];
1434 };
1435
1436 /**
1437 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1438 */
1439 struct aux_reply_control_data {
1440 /**
1441 * Reserved for future use
1442 */
1443 uint32_t handle;
1444 /**
1445 * Aux Instance
1446 */
1447 uint8_t instance;
1448 /**
1449 * Aux transaction result: definition in enum aux_return_code_type
1450 */
1451 uint8_t result;
1452 /**
1453 * Alignment only
1454 */
1455 uint16_t pad;
1456 };
1457
1458 /**
1459 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
1460 */
1461 struct dmub_rb_cmd_dp_aux_reply {
1462 /**
1463 * Command header.
1464 */
1465 struct dmub_cmd_header header;
1466 /**
1467 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1468 */
1469 struct aux_reply_control_data control;
1470 /**
1471 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1472 */
1473 struct aux_reply_data reply_data;
1474 };
1475
1476 /* DP HPD Notify command - OutBox Cmd */
1477 /**
1478 * DP HPD Type
1479 */
1480 enum dp_hpd_type {
1481 /**
1482 * Normal DP HPD
1483 */
1484 DP_HPD = 0,
1485 /**
1486 * DP HPD short pulse
1487 */
1488 DP_IRQ
1489 };
1490
1491 /**
1492 * DP HPD Status
1493 */
1494 enum dp_hpd_status {
1495 /**
1496 * DP_HPD status low
1497 */
1498 DP_HPD_UNPLUG = 0,
1499 /**
1500 * DP_HPD status high
1501 */
1502 DP_HPD_PLUG
1503 };
1504
1505 /**
1506 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1507 */
1508 struct dp_hpd_data {
1509 /**
1510 * DP HPD instance
1511 */
1512 uint8_t instance;
1513 /**
1514 * HPD type
1515 */
1516 uint8_t hpd_type;
1517 /**
1518 * HPD status: only for type: DP_HPD to indicate status
1519 */
1520 uint8_t hpd_status;
1521 /**
1522 * Alignment only
1523 */
1524 uint8_t pad;
1525 };
1526
1527 /**
1528 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1529 */
1530 struct dmub_rb_cmd_dp_hpd_notify {
1531 /**
1532 * Command header.
1533 */
1534 struct dmub_cmd_header header;
1535 /**
1536 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1537 */
1538 struct dp_hpd_data hpd_data;
1539 };
1540
1541 /**
1542 * Definition of a SET_CONFIG reply from DPOA.
1543 */
1544 enum set_config_status {
1545 SET_CONFIG_PENDING = 0,
1546 SET_CONFIG_ACK_RECEIVED,
1547 SET_CONFIG_RX_TIMEOUT,
1548 SET_CONFIG_UNKNOWN_ERROR,
1549 };
1550
1551 /**
1552 * Definition of a set_config reply
1553 */
1554 struct set_config_reply_control_data {
1555 uint8_t instance; /* DPIA Instance */
1556 uint8_t status; /* Set Config reply */
1557 uint16_t pad; /* Alignment */
1558 };
1559
1560 /**
1561 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command.
1562 */
1563 struct dmub_rb_cmd_dp_set_config_reply {
1564 struct dmub_cmd_header header;
1565 struct set_config_reply_control_data set_config_reply_control;
1566 };
1567
1568 /**
1569 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
1570 */
1571 struct dmub_cmd_hpd_state_query_data {
1572 uint8_t instance; /**< HPD instance or DPIA instance */
1573 uint8_t result; /**< For returning HPD state */
1574 uint16_t pad; /** < Alignment */
1575 enum aux_channel_type ch_type; /**< enum aux_channel_type */
1576 enum aux_return_code_type status; /**< for returning the status of command */
1577 };
1578
1579 /**
1580 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
1581 */
1582 struct dmub_rb_cmd_query_hpd_state {
1583 /**
1584 * Command header.
1585 */
1586 struct dmub_cmd_header header;
1587 /**
1588 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
1589 */
1590 struct dmub_cmd_hpd_state_query_data data;
1591 };
1592
1593 /*
1594 * Command IDs should be treated as stable ABI.
1595 * Do not reuse or modify IDs.
1596 */
1597
1598 /**
1599 * PSR command sub-types.
1600 */
1601 enum dmub_cmd_psr_type {
1602 /**
1603 * Set PSR version support.
1604 */
1605 DMUB_CMD__PSR_SET_VERSION = 0,
1606 /**
1607 * Copy driver-calculated parameters to PSR state.
1608 */
1609 DMUB_CMD__PSR_COPY_SETTINGS = 1,
1610 /**
1611 * Enable PSR.
1612 */
1613 DMUB_CMD__PSR_ENABLE = 2,
1614
1615 /**
1616 * Disable PSR.
1617 */
1618 DMUB_CMD__PSR_DISABLE = 3,
1619
1620 /**
1621 * Set PSR level.
1622 * PSR level is a 16-bit value dicated by driver that
1623 * will enable/disable different functionality.
1624 */
1625 DMUB_CMD__PSR_SET_LEVEL = 4,
1626
1627 /**
1628 * Forces PSR enabled until an explicit PSR disable call.
1629 */
1630 DMUB_CMD__PSR_FORCE_STATIC = 5,
1631 /**
1632 * Set vtotal in psr active for FreeSync PSR.
1633 */
1634 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
1635 /**
1636 * Set PSR power option
1637 */
1638 DMUB_CMD__SET_PSR_POWER_OPT = 7,
1639 };
1640
1641 enum dmub_cmd_fams_type {
1642 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0,
1643 DMUB_CMD__FAMS_DRR_UPDATE = 1,
1644 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd
1645 /**
1646 * For SubVP set manual trigger in FW because it
1647 * triggers DRR_UPDATE_PENDING which SubVP relies
1648 * on (for any SubVP cases that use a DRR display)
1649 */
1650 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,
1651 };
1652
1653 /**
1654 * PSR versions.
1655 */
1656 enum psr_version {
1657 /**
1658 * PSR version 1.
1659 */
1660 PSR_VERSION_1 = 0,
1661 /**
1662 * Freesync PSR SU.
1663 */
1664 PSR_VERSION_SU_1 = 1,
1665 /**
1666 * PSR not supported.
1667 */
1668 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
1669 };
1670
1671 /**
1672 * enum dmub_cmd_mall_type - MALL commands
1673 */
1674 enum dmub_cmd_mall_type {
1675 /**
1676 * Allows display refresh from MALL.
1677 */
1678 DMUB_CMD__MALL_ACTION_ALLOW = 0,
1679 /**
1680 * Disallows display refresh from MALL.
1681 */
1682 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
1683 /**
1684 * Cursor copy for MALL.
1685 */
1686 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
1687 /**
1688 * Controls DF requests.
1689 */
1690 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
1691 };
1692
1693 /**
1694 * PHY Link rate for DP.
1695 */
1696 enum phy_link_rate {
1697 /**
1698 * not supported.
1699 */
1700 PHY_RATE_UNKNOWN = 0,
1701 /**
1702 * Rate_1 (RBR) - 1.62 Gbps/Lane
1703 */
1704 PHY_RATE_162 = 1,
1705 /**
1706 * Rate_2 - 2.16 Gbps/Lane
1707 */
1708 PHY_RATE_216 = 2,
1709 /**
1710 * Rate_3 - 2.43 Gbps/Lane
1711 */
1712 PHY_RATE_243 = 3,
1713 /**
1714 * Rate_4 (HBR) - 2.70 Gbps/Lane
1715 */
1716 PHY_RATE_270 = 4,
1717 /**
1718 * Rate_5 (RBR2)- 3.24 Gbps/Lane
1719 */
1720 PHY_RATE_324 = 5,
1721 /**
1722 * Rate_6 - 4.32 Gbps/Lane
1723 */
1724 PHY_RATE_432 = 6,
1725 /**
1726 * Rate_7 (HBR2)- 5.40 Gbps/Lane
1727 */
1728 PHY_RATE_540 = 7,
1729 /**
1730 * Rate_8 (HBR3)- 8.10 Gbps/Lane
1731 */
1732 PHY_RATE_810 = 8,
1733 /**
1734 * UHBR10 - 10.0 Gbps/Lane
1735 */
1736 PHY_RATE_1000 = 9,
1737 /**
1738 * UHBR13.5 - 13.5 Gbps/Lane
1739 */
1740 PHY_RATE_1350 = 10,
1741 /**
1742 * UHBR10 - 20.0 Gbps/Lane
1743 */
1744 PHY_RATE_2000 = 11,
1745 };
1746
1747 /**
1748 * enum dmub_phy_fsm_state - PHY FSM states.
1749 * PHY FSM state to transit to during PSR enable/disable.
1750 */
1751 enum dmub_phy_fsm_state {
1752 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,
1753 DMUB_PHY_FSM_RESET,
1754 DMUB_PHY_FSM_RESET_RELEASED,
1755 DMUB_PHY_FSM_SRAM_LOAD_DONE,
1756 DMUB_PHY_FSM_INITIALIZED,
1757 DMUB_PHY_FSM_CALIBRATED,
1758 DMUB_PHY_FSM_CALIBRATED_LP,
1759 DMUB_PHY_FSM_CALIBRATED_PG,
1760 DMUB_PHY_FSM_POWER_DOWN,
1761 DMUB_PHY_FSM_PLL_EN,
1762 DMUB_PHY_FSM_TX_EN,
1763 DMUB_PHY_FSM_FAST_LP,
1764 };
1765
1766 /**
1767 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1768 */
1769 struct dmub_cmd_psr_copy_settings_data {
1770 /**
1771 * Flags that can be set by driver to change some PSR behaviour.
1772 */
1773 union dmub_psr_debug_flags debug;
1774 /**
1775 * 16-bit value dicated by driver that will enable/disable different functionality.
1776 */
1777 uint16_t psr_level;
1778 /**
1779 * DPP HW instance.
1780 */
1781 uint8_t dpp_inst;
1782 /**
1783 * MPCC HW instance.
1784 * Not used in dmub fw,
1785 * dmub fw will get active opp by reading odm registers.
1786 */
1787 uint8_t mpcc_inst;
1788 /**
1789 * OPP HW instance.
1790 * Not used in dmub fw,
1791 * dmub fw will get active opp by reading odm registers.
1792 */
1793 uint8_t opp_inst;
1794 /**
1795 * OTG HW instance.
1796 */
1797 uint8_t otg_inst;
1798 /**
1799 * DIG FE HW instance.
1800 */
1801 uint8_t digfe_inst;
1802 /**
1803 * DIG BE HW instance.
1804 */
1805 uint8_t digbe_inst;
1806 /**
1807 * DP PHY HW instance.
1808 */
1809 uint8_t dpphy_inst;
1810 /**
1811 * AUX HW instance.
1812 */
1813 uint8_t aux_inst;
1814 /**
1815 * Determines if SMU optimzations are enabled/disabled.
1816 */
1817 uint8_t smu_optimizations_en;
1818 /**
1819 * Unused.
1820 * TODO: Remove.
1821 */
1822 uint8_t frame_delay;
1823 /**
1824 * If RFB setup time is greater than the total VBLANK time,
1825 * it is not possible for the sink to capture the video frame
1826 * in the same frame the SDP is sent. In this case,
1827 * the frame capture indication bit should be set and an extra
1828 * static frame should be transmitted to the sink.
1829 */
1830 uint8_t frame_cap_ind;
1831 /**
1832 * Granularity of Y offset supported by sink.
1833 */
1834 uint8_t su_y_granularity;
1835 /**
1836 * Indicates whether sink should start capturing
1837 * immediately following active scan line,
1838 * or starting with the 2nd active scan line.
1839 */
1840 uint8_t line_capture_indication;
1841 /**
1842 * Multi-display optimizations are implemented on certain ASICs.
1843 */
1844 uint8_t multi_disp_optimizations_en;
1845 /**
1846 * The last possible line SDP may be transmitted without violating
1847 * the RFB setup time or entering the active video frame.
1848 */
1849 uint16_t init_sdp_deadline;
1850 /**
1851 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
1852 */
1853 uint8_t rate_control_caps ;
1854 /*
1855 * Force PSRSU always doing full frame update
1856 */
1857 uint8_t force_ffu_mode;
1858 /**
1859 * Length of each horizontal line in us.
1860 */
1861 uint32_t line_time_in_us;
1862 /**
1863 * FEC enable status in driver
1864 */
1865 uint8_t fec_enable_status;
1866 /**
1867 * FEC re-enable delay when PSR exit.
1868 * unit is 100us, range form 0~255(0xFF).
1869 */
1870 uint8_t fec_enable_delay_in100us;
1871 /**
1872 * PSR control version.
1873 */
1874 uint8_t cmd_version;
1875 /**
1876 * Panel Instance.
1877 * Panel isntance to identify which psr_state to use
1878 * Currently the support is only for 0 or 1
1879 */
1880 uint8_t panel_inst;
1881 /*
1882 * DSC enable status in driver
1883 */
1884 uint8_t dsc_enable_status;
1885 /*
1886 * Use FSM state for PSR power up/down
1887 */
1888 uint8_t use_phy_fsm;
1889 /**
1890 * Explicit padding to 2 byte boundary.
1891 */
1892 uint8_t pad3[2];
1893 };
1894
1895 /**
1896 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
1897 */
1898 struct dmub_rb_cmd_psr_copy_settings {
1899 /**
1900 * Command header.
1901 */
1902 struct dmub_cmd_header header;
1903 /**
1904 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1905 */
1906 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
1907 };
1908
1909 /**
1910 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
1911 */
1912 struct dmub_cmd_psr_set_level_data {
1913 /**
1914 * 16-bit value dicated by driver that will enable/disable different functionality.
1915 */
1916 uint16_t psr_level;
1917 /**
1918 * PSR control version.
1919 */
1920 uint8_t cmd_version;
1921 /**
1922 * Panel Instance.
1923 * Panel isntance to identify which psr_state to use
1924 * Currently the support is only for 0 or 1
1925 */
1926 uint8_t panel_inst;
1927 };
1928
1929 /**
1930 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1931 */
1932 struct dmub_rb_cmd_psr_set_level {
1933 /**
1934 * Command header.
1935 */
1936 struct dmub_cmd_header header;
1937 /**
1938 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1939 */
1940 struct dmub_cmd_psr_set_level_data psr_set_level_data;
1941 };
1942
1943 struct dmub_rb_cmd_psr_enable_data {
1944 /**
1945 * PSR control version.
1946 */
1947 uint8_t cmd_version;
1948 /**
1949 * Panel Instance.
1950 * Panel isntance to identify which psr_state to use
1951 * Currently the support is only for 0 or 1
1952 */
1953 uint8_t panel_inst;
1954 /**
1955 * Phy state to enter.
1956 * Values to use are defined in dmub_phy_fsm_state
1957 */
1958 uint8_t phy_fsm_state;
1959 /**
1960 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
1961 * Set this using enum phy_link_rate.
1962 * This does not support HDMI/DP2 for now.
1963 */
1964 uint8_t phy_rate;
1965 };
1966
1967 /**
1968 * Definition of a DMUB_CMD__PSR_ENABLE command.
1969 * PSR enable/disable is controlled using the sub_type.
1970 */
1971 struct dmub_rb_cmd_psr_enable {
1972 /**
1973 * Command header.
1974 */
1975 struct dmub_cmd_header header;
1976
1977 struct dmub_rb_cmd_psr_enable_data data;
1978 };
1979
1980 /**
1981 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
1982 */
1983 struct dmub_cmd_psr_set_version_data {
1984 /**
1985 * PSR version that FW should implement.
1986 */
1987 enum psr_version version;
1988 /**
1989 * PSR control version.
1990 */
1991 uint8_t cmd_version;
1992 /**
1993 * Panel Instance.
1994 * Panel isntance to identify which psr_state to use
1995 * Currently the support is only for 0 or 1
1996 */
1997 uint8_t panel_inst;
1998 /**
1999 * Explicit padding to 4 byte boundary.
2000 */
2001 uint8_t pad[2];
2002 };
2003
2004 /**
2005 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
2006 */
2007 struct dmub_rb_cmd_psr_set_version {
2008 /**
2009 * Command header.
2010 */
2011 struct dmub_cmd_header header;
2012 /**
2013 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
2014 */
2015 struct dmub_cmd_psr_set_version_data psr_set_version_data;
2016 };
2017
2018 struct dmub_cmd_psr_force_static_data {
2019 /**
2020 * PSR control version.
2021 */
2022 uint8_t cmd_version;
2023 /**
2024 * Panel Instance.
2025 * Panel isntance to identify which psr_state to use
2026 * Currently the support is only for 0 or 1
2027 */
2028 uint8_t panel_inst;
2029 /**
2030 * Explicit padding to 4 byte boundary.
2031 */
2032 uint8_t pad[2];
2033 };
2034
2035 /**
2036 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
2037 */
2038 struct dmub_rb_cmd_psr_force_static {
2039 /**
2040 * Command header.
2041 */
2042 struct dmub_cmd_header header;
2043 /**
2044 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
2045 */
2046 struct dmub_cmd_psr_force_static_data psr_force_static_data;
2047 };
2048
2049 /**
2050 * PSR SU debug flags.
2051 */
2052 union dmub_psr_su_debug_flags {
2053 /**
2054 * PSR SU debug flags.
2055 */
2056 struct {
2057 /**
2058 * Update dirty rect in SW only.
2059 */
2060 uint8_t update_dirty_rect_only : 1;
2061 /**
2062 * Reset the cursor/plane state before processing the call.
2063 */
2064 uint8_t reset_state : 1;
2065 } bitfields;
2066
2067 /**
2068 * Union for debug flags.
2069 */
2070 uint32_t u32All;
2071 };
2072
2073 /**
2074 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
2075 * This triggers a selective update for PSR SU.
2076 */
2077 struct dmub_cmd_update_dirty_rect_data {
2078 /**
2079 * Dirty rects from OS.
2080 */
2081 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
2082 /**
2083 * PSR SU debug flags.
2084 */
2085 union dmub_psr_su_debug_flags debug_flags;
2086 /**
2087 * OTG HW instance.
2088 */
2089 uint8_t pipe_idx;
2090 /**
2091 * Number of dirty rects.
2092 */
2093 uint8_t dirty_rect_count;
2094 /**
2095 * PSR control version.
2096 */
2097 uint8_t cmd_version;
2098 /**
2099 * Panel Instance.
2100 * Panel isntance to identify which psr_state to use
2101 * Currently the support is only for 0 or 1
2102 */
2103 uint8_t panel_inst;
2104 };
2105
2106 /**
2107 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
2108 */
2109 struct dmub_rb_cmd_update_dirty_rect {
2110 /**
2111 * Command header.
2112 */
2113 struct dmub_cmd_header header;
2114 /**
2115 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
2116 */
2117 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
2118 };
2119
2120 /**
2121 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
2122 */
2123 union dmub_reg_cursor_control_cfg {
2124 struct {
2125 uint32_t cur_enable: 1;
2126 uint32_t reser0: 3;
2127 uint32_t cur_2x_magnify: 1;
2128 uint32_t reser1: 3;
2129 uint32_t mode: 3;
2130 uint32_t reser2: 5;
2131 uint32_t pitch: 2;
2132 uint32_t reser3: 6;
2133 uint32_t line_per_chunk: 5;
2134 uint32_t reser4: 3;
2135 } bits;
2136 uint32_t raw;
2137 };
2138 struct dmub_cursor_position_cache_hubp {
2139 union dmub_reg_cursor_control_cfg cur_ctl;
2140 union dmub_reg_position_cfg {
2141 struct {
2142 uint32_t cur_x_pos: 16;
2143 uint32_t cur_y_pos: 16;
2144 } bits;
2145 uint32_t raw;
2146 } position;
2147 union dmub_reg_hot_spot_cfg {
2148 struct {
2149 uint32_t hot_x: 16;
2150 uint32_t hot_y: 16;
2151 } bits;
2152 uint32_t raw;
2153 } hot_spot;
2154 union dmub_reg_dst_offset_cfg {
2155 struct {
2156 uint32_t dst_x_offset: 13;
2157 uint32_t reserved: 19;
2158 } bits;
2159 uint32_t raw;
2160 } dst_offset;
2161 };
2162
2163 union dmub_reg_cur0_control_cfg {
2164 struct {
2165 uint32_t cur0_enable: 1;
2166 uint32_t expansion_mode: 1;
2167 uint32_t reser0: 1;
2168 uint32_t cur0_rom_en: 1;
2169 uint32_t mode: 3;
2170 uint32_t reserved: 25;
2171 } bits;
2172 uint32_t raw;
2173 };
2174 struct dmub_cursor_position_cache_dpp {
2175 union dmub_reg_cur0_control_cfg cur0_ctl;
2176 };
2177 struct dmub_cursor_position_cfg {
2178 struct dmub_cursor_position_cache_hubp pHubp;
2179 struct dmub_cursor_position_cache_dpp pDpp;
2180 uint8_t pipe_idx;
2181 /*
2182 * Padding is required. To be 4 Bytes Aligned.
2183 */
2184 uint8_t padding[3];
2185 };
2186
2187 struct dmub_cursor_attribute_cache_hubp {
2188 uint32_t SURFACE_ADDR_HIGH;
2189 uint32_t SURFACE_ADDR;
2190 union dmub_reg_cursor_control_cfg cur_ctl;
2191 union dmub_reg_cursor_size_cfg {
2192 struct {
2193 uint32_t width: 16;
2194 uint32_t height: 16;
2195 } bits;
2196 uint32_t raw;
2197 } size;
2198 union dmub_reg_cursor_settings_cfg {
2199 struct {
2200 uint32_t dst_y_offset: 8;
2201 uint32_t chunk_hdl_adjust: 2;
2202 uint32_t reserved: 22;
2203 } bits;
2204 uint32_t raw;
2205 } settings;
2206 };
2207 struct dmub_cursor_attribute_cache_dpp {
2208 union dmub_reg_cur0_control_cfg cur0_ctl;
2209 };
2210 struct dmub_cursor_attributes_cfg {
2211 struct dmub_cursor_attribute_cache_hubp aHubp;
2212 struct dmub_cursor_attribute_cache_dpp aDpp;
2213 };
2214
2215 struct dmub_cmd_update_cursor_payload0 {
2216 /**
2217 * Cursor dirty rects.
2218 */
2219 struct dmub_rect cursor_rect;
2220 /**
2221 * PSR SU debug flags.
2222 */
2223 union dmub_psr_su_debug_flags debug_flags;
2224 /**
2225 * Cursor enable/disable.
2226 */
2227 uint8_t enable;
2228 /**
2229 * OTG HW instance.
2230 */
2231 uint8_t pipe_idx;
2232 /**
2233 * PSR control version.
2234 */
2235 uint8_t cmd_version;
2236 /**
2237 * Panel Instance.
2238 * Panel isntance to identify which psr_state to use
2239 * Currently the support is only for 0 or 1
2240 */
2241 uint8_t panel_inst;
2242 /**
2243 * Cursor Position Register.
2244 * Registers contains Hubp & Dpp modules
2245 */
2246 struct dmub_cursor_position_cfg position_cfg;
2247 };
2248
2249 struct dmub_cmd_update_cursor_payload1 {
2250 struct dmub_cursor_attributes_cfg attribute_cfg;
2251 };
2252
2253 union dmub_cmd_update_cursor_info_data {
2254 struct dmub_cmd_update_cursor_payload0 payload0;
2255 struct dmub_cmd_update_cursor_payload1 payload1;
2256 };
2257 /**
2258 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
2259 */
2260 struct dmub_rb_cmd_update_cursor_info {
2261 /**
2262 * Command header.
2263 */
2264 struct dmub_cmd_header header;
2265 /**
2266 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
2267 */
2268 union dmub_cmd_update_cursor_info_data update_cursor_info_data;
2269 };
2270
2271 /**
2272 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2273 */
2274 struct dmub_cmd_psr_set_vtotal_data {
2275 /**
2276 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
2277 */
2278 uint16_t psr_vtotal_idle;
2279 /**
2280 * PSR control version.
2281 */
2282 uint8_t cmd_version;
2283 /**
2284 * Panel Instance.
2285 * Panel isntance to identify which psr_state to use
2286 * Currently the support is only for 0 or 1
2287 */
2288 uint8_t panel_inst;
2289 /*
2290 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
2291 */
2292 uint16_t psr_vtotal_su;
2293 /**
2294 * Explicit padding to 4 byte boundary.
2295 */
2296 uint8_t pad2[2];
2297 };
2298
2299 /**
2300 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2301 */
2302 struct dmub_rb_cmd_psr_set_vtotal {
2303 /**
2304 * Command header.
2305 */
2306 struct dmub_cmd_header header;
2307 /**
2308 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2309 */
2310 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
2311 };
2312
2313 /**
2314 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
2315 */
2316 struct dmub_cmd_psr_set_power_opt_data {
2317 /**
2318 * PSR control version.
2319 */
2320 uint8_t cmd_version;
2321 /**
2322 * Panel Instance.
2323 * Panel isntance to identify which psr_state to use
2324 * Currently the support is only for 0 or 1
2325 */
2326 uint8_t panel_inst;
2327 /**
2328 * Explicit padding to 4 byte boundary.
2329 */
2330 uint8_t pad[2];
2331 /**
2332 * PSR power option
2333 */
2334 uint32_t power_opt;
2335 };
2336
2337 /**
2338 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
2339 */
2340 struct dmub_rb_cmd_psr_set_power_opt {
2341 /**
2342 * Command header.
2343 */
2344 struct dmub_cmd_header header;
2345 /**
2346 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
2347 */
2348 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
2349 };
2350
2351 /**
2352 * Set of HW components that can be locked.
2353 *
2354 * Note: If updating with more HW components, fields
2355 * in dmub_inbox0_cmd_lock_hw must be updated to match.
2356 */
2357 union dmub_hw_lock_flags {
2358 /**
2359 * Set of HW components that can be locked.
2360 */
2361 struct {
2362 /**
2363 * Lock/unlock OTG master update lock.
2364 */
2365 uint8_t lock_pipe : 1;
2366 /**
2367 * Lock/unlock cursor.
2368 */
2369 uint8_t lock_cursor : 1;
2370 /**
2371 * Lock/unlock global update lock.
2372 */
2373 uint8_t lock_dig : 1;
2374 /**
2375 * Triple buffer lock requires additional hw programming to usual OTG master lock.
2376 */
2377 uint8_t triple_buffer_lock : 1;
2378 } bits;
2379
2380 /**
2381 * Union for HW Lock flags.
2382 */
2383 uint8_t u8All;
2384 };
2385
2386 /**
2387 * Instances of HW to be locked.
2388 *
2389 * Note: If updating with more HW components, fields
2390 * in dmub_inbox0_cmd_lock_hw must be updated to match.
2391 */
2392 struct dmub_hw_lock_inst_flags {
2393 /**
2394 * OTG HW instance for OTG master update lock.
2395 */
2396 uint8_t otg_inst;
2397 /**
2398 * OPP instance for cursor lock.
2399 */
2400 uint8_t opp_inst;
2401 /**
2402 * OTG HW instance for global update lock.
2403 * TODO: Remove, and re-use otg_inst.
2404 */
2405 uint8_t dig_inst;
2406 /**
2407 * Explicit pad to 4 byte boundary.
2408 */
2409 uint8_t pad;
2410 };
2411
2412 /**
2413 * Clients that can acquire the HW Lock Manager.
2414 *
2415 * Note: If updating with more clients, fields in
2416 * dmub_inbox0_cmd_lock_hw must be updated to match.
2417 */
2418 enum hw_lock_client {
2419 /**
2420 * Driver is the client of HW Lock Manager.
2421 */
2422 HW_LOCK_CLIENT_DRIVER = 0,
2423 /**
2424 * PSR SU is the client of HW Lock Manager.
2425 */
2426 HW_LOCK_CLIENT_PSR_SU = 1,
2427 /**
2428 * Invalid client.
2429 */
2430 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
2431 };
2432
2433 /**
2434 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
2435 */
2436 struct dmub_cmd_lock_hw_data {
2437 /**
2438 * Specifies the client accessing HW Lock Manager.
2439 */
2440 enum hw_lock_client client;
2441 /**
2442 * HW instances to be locked.
2443 */
2444 struct dmub_hw_lock_inst_flags inst_flags;
2445 /**
2446 * Which components to be locked.
2447 */
2448 union dmub_hw_lock_flags hw_locks;
2449 /**
2450 * Specifies lock/unlock.
2451 */
2452 uint8_t lock;
2453 /**
2454 * HW can be unlocked separately from releasing the HW Lock Mgr.
2455 * This flag is set if the client wishes to release the object.
2456 */
2457 uint8_t should_release;
2458 /**
2459 * Explicit padding to 4 byte boundary.
2460 */
2461 uint8_t pad;
2462 };
2463
2464 /**
2465 * Definition of a DMUB_CMD__HW_LOCK command.
2466 * Command is used by driver and FW.
2467 */
2468 struct dmub_rb_cmd_lock_hw {
2469 /**
2470 * Command header.
2471 */
2472 struct dmub_cmd_header header;
2473 /**
2474 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
2475 */
2476 struct dmub_cmd_lock_hw_data lock_hw_data;
2477 };
2478
2479 /**
2480 * ABM command sub-types.
2481 */
2482 enum dmub_cmd_abm_type {
2483 /**
2484 * Initialize parameters for ABM algorithm.
2485 * Data is passed through an indirect buffer.
2486 */
2487 DMUB_CMD__ABM_INIT_CONFIG = 0,
2488 /**
2489 * Set OTG and panel HW instance.
2490 */
2491 DMUB_CMD__ABM_SET_PIPE = 1,
2492 /**
2493 * Set user requested backklight level.
2494 */
2495 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
2496 /**
2497 * Set ABM operating/aggression level.
2498 */
2499 DMUB_CMD__ABM_SET_LEVEL = 3,
2500 /**
2501 * Set ambient light level.
2502 */
2503 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
2504 /**
2505 * Enable/disable fractional duty cycle for backlight PWM.
2506 */
2507 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
2508
2509 /**
2510 * unregister vertical interrupt after steady state is reached
2511 */
2512 DMUB_CMD__ABM_PAUSE = 6,
2513 };
2514
2515 /**
2516 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
2517 * Requirements:
2518 * - Padded explicitly to 32-bit boundary.
2519 * - Must ensure this structure matches the one on driver-side,
2520 * otherwise it won't be aligned.
2521 */
2522 struct abm_config_table {
2523 /**
2524 * Gamma curve thresholds, used for crgb conversion.
2525 */
2526 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
2527 /**
2528 * Gamma curve offsets, used for crgb conversion.
2529 */
2530 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
2531 /**
2532 * Gamma curve slopes, used for crgb conversion.
2533 */
2534 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
2535 /**
2536 * Custom backlight curve thresholds.
2537 */
2538 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
2539 /**
2540 * Custom backlight curve offsets.
2541 */
2542 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
2543 /**
2544 * Ambient light thresholds.
2545 */
2546 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
2547 /**
2548 * Minimum programmable backlight.
2549 */
2550 uint16_t min_abm_backlight; // 122B
2551 /**
2552 * Minimum reduction values.
2553 */
2554 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
2555 /**
2556 * Maximum reduction values.
2557 */
2558 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
2559 /**
2560 * Bright positive gain.
2561 */
2562 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
2563 /**
2564 * Dark negative gain.
2565 */
2566 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
2567 /**
2568 * Hybrid factor.
2569 */
2570 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
2571 /**
2572 * Contrast factor.
2573 */
2574 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
2575 /**
2576 * Deviation gain.
2577 */
2578 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
2579 /**
2580 * Minimum knee.
2581 */
2582 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
2583 /**
2584 * Maximum knee.
2585 */
2586 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
2587 /**
2588 * Unused.
2589 */
2590 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
2591 /**
2592 * Explicit padding to 4 byte boundary.
2593 */
2594 uint8_t pad3[3]; // 229B
2595 /**
2596 * Backlight ramp reduction.
2597 */
2598 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
2599 /**
2600 * Backlight ramp start.
2601 */
2602 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
2603 };
2604
2605 /**
2606 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
2607 */
2608 struct dmub_cmd_abm_set_pipe_data {
2609 /**
2610 * OTG HW instance.
2611 */
2612 uint8_t otg_inst;
2613
2614 /**
2615 * Panel Control HW instance.
2616 */
2617 uint8_t panel_inst;
2618
2619 /**
2620 * Controls how ABM will interpret a set pipe or set level command.
2621 */
2622 uint8_t set_pipe_option;
2623
2624 /**
2625 * Unused.
2626 * TODO: Remove.
2627 */
2628 uint8_t ramping_boundary;
2629 };
2630
2631 /**
2632 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
2633 */
2634 struct dmub_rb_cmd_abm_set_pipe {
2635 /**
2636 * Command header.
2637 */
2638 struct dmub_cmd_header header;
2639
2640 /**
2641 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
2642 */
2643 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
2644 };
2645
2646 /**
2647 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
2648 */
2649 struct dmub_cmd_abm_set_backlight_data {
2650 /**
2651 * Number of frames to ramp to backlight user level.
2652 */
2653 uint32_t frame_ramp;
2654
2655 /**
2656 * Requested backlight level from user.
2657 */
2658 uint32_t backlight_user_level;
2659
2660 /**
2661 * ABM control version.
2662 */
2663 uint8_t version;
2664
2665 /**
2666 * Panel Control HW instance mask.
2667 * Bit 0 is Panel Control HW instance 0.
2668 * Bit 1 is Panel Control HW instance 1.
2669 */
2670 uint8_t panel_mask;
2671
2672 /**
2673 * Explicit padding to 4 byte boundary.
2674 */
2675 uint8_t pad[2];
2676 };
2677
2678 /**
2679 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
2680 */
2681 struct dmub_rb_cmd_abm_set_backlight {
2682 /**
2683 * Command header.
2684 */
2685 struct dmub_cmd_header header;
2686
2687 /**
2688 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
2689 */
2690 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
2691 };
2692
2693 /**
2694 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
2695 */
2696 struct dmub_cmd_abm_set_level_data {
2697 /**
2698 * Set current ABM operating/aggression level.
2699 */
2700 uint32_t level;
2701
2702 /**
2703 * ABM control version.
2704 */
2705 uint8_t version;
2706
2707 /**
2708 * Panel Control HW instance mask.
2709 * Bit 0 is Panel Control HW instance 0.
2710 * Bit 1 is Panel Control HW instance 1.
2711 */
2712 uint8_t panel_mask;
2713
2714 /**
2715 * Explicit padding to 4 byte boundary.
2716 */
2717 uint8_t pad[2];
2718 };
2719
2720 /**
2721 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
2722 */
2723 struct dmub_rb_cmd_abm_set_level {
2724 /**
2725 * Command header.
2726 */
2727 struct dmub_cmd_header header;
2728
2729 /**
2730 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
2731 */
2732 struct dmub_cmd_abm_set_level_data abm_set_level_data;
2733 };
2734
2735 /**
2736 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
2737 */
2738 struct dmub_cmd_abm_set_ambient_level_data {
2739 /**
2740 * Ambient light sensor reading from OS.
2741 */
2742 uint32_t ambient_lux;
2743
2744 /**
2745 * ABM control version.
2746 */
2747 uint8_t version;
2748
2749 /**
2750 * Panel Control HW instance mask.
2751 * Bit 0 is Panel Control HW instance 0.
2752 * Bit 1 is Panel Control HW instance 1.
2753 */
2754 uint8_t panel_mask;
2755
2756 /**
2757 * Explicit padding to 4 byte boundary.
2758 */
2759 uint8_t pad[2];
2760 };
2761
2762 /**
2763 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
2764 */
2765 struct dmub_rb_cmd_abm_set_ambient_level {
2766 /**
2767 * Command header.
2768 */
2769 struct dmub_cmd_header header;
2770
2771 /**
2772 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
2773 */
2774 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
2775 };
2776
2777 /**
2778 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
2779 */
2780 struct dmub_cmd_abm_set_pwm_frac_data {
2781 /**
2782 * Enable/disable fractional duty cycle for backlight PWM.
2783 * TODO: Convert to uint8_t.
2784 */
2785 uint32_t fractional_pwm;
2786
2787 /**
2788 * ABM control version.
2789 */
2790 uint8_t version;
2791
2792 /**
2793 * Panel Control HW instance mask.
2794 * Bit 0 is Panel Control HW instance 0.
2795 * Bit 1 is Panel Control HW instance 1.
2796 */
2797 uint8_t panel_mask;
2798
2799 /**
2800 * Explicit padding to 4 byte boundary.
2801 */
2802 uint8_t pad[2];
2803 };
2804
2805 /**
2806 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
2807 */
2808 struct dmub_rb_cmd_abm_set_pwm_frac {
2809 /**
2810 * Command header.
2811 */
2812 struct dmub_cmd_header header;
2813
2814 /**
2815 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
2816 */
2817 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
2818 };
2819
2820 /**
2821 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
2822 */
2823 struct dmub_cmd_abm_init_config_data {
2824 /**
2825 * Location of indirect buffer used to pass init data to ABM.
2826 */
2827 union dmub_addr src;
2828
2829 /**
2830 * Indirect buffer length.
2831 */
2832 uint16_t bytes;
2833
2834
2835 /**
2836 * ABM control version.
2837 */
2838 uint8_t version;
2839
2840 /**
2841 * Panel Control HW instance mask.
2842 * Bit 0 is Panel Control HW instance 0.
2843 * Bit 1 is Panel Control HW instance 1.
2844 */
2845 uint8_t panel_mask;
2846
2847 /**
2848 * Explicit padding to 4 byte boundary.
2849 */
2850 uint8_t pad[2];
2851 };
2852
2853 /**
2854 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
2855 */
2856 struct dmub_rb_cmd_abm_init_config {
2857 /**
2858 * Command header.
2859 */
2860 struct dmub_cmd_header header;
2861
2862 /**
2863 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
2864 */
2865 struct dmub_cmd_abm_init_config_data abm_init_config_data;
2866 };
2867
2868 /**
2869 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
2870 */
2871
2872 struct dmub_cmd_abm_pause_data {
2873
2874 /**
2875 * Panel Control HW instance mask.
2876 * Bit 0 is Panel Control HW instance 0.
2877 * Bit 1 is Panel Control HW instance 1.
2878 */
2879 uint8_t panel_mask;
2880
2881 /**
2882 * OTG hw instance
2883 */
2884 uint8_t otg_inst;
2885
2886 /**
2887 * Enable or disable ABM pause
2888 */
2889 uint8_t enable;
2890
2891 /**
2892 * Explicit padding to 4 byte boundary.
2893 */
2894 uint8_t pad[1];
2895 };
2896
2897 /**
2898 * Definition of a DMUB_CMD__ABM_PAUSE command.
2899 */
2900 struct dmub_rb_cmd_abm_pause {
2901 /**
2902 * Command header.
2903 */
2904 struct dmub_cmd_header header;
2905
2906 /**
2907 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
2908 */
2909 struct dmub_cmd_abm_pause_data abm_pause_data;
2910 };
2911
2912 /**
2913 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
2914 */
2915 struct dmub_cmd_query_feature_caps_data {
2916 /**
2917 * DMUB feature capabilities.
2918 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
2919 */
2920 struct dmub_feature_caps feature_caps;
2921 };
2922
2923 /**
2924 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
2925 */
2926 struct dmub_rb_cmd_query_feature_caps {
2927 /**
2928 * Command header.
2929 */
2930 struct dmub_cmd_header header;
2931 /**
2932 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
2933 */
2934 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
2935 };
2936
2937 /**
2938 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
2939 */
2940 struct dmub_cmd_visual_confirm_color_data {
2941 /**
2942 * DMUB feature capabilities.
2943 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
2944 */
2945 struct dmub_visual_confirm_color visual_confirm_color;
2946 };
2947
2948 /**
2949 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
2950 */
2951 struct dmub_rb_cmd_get_visual_confirm_color {
2952 /**
2953 * Command header.
2954 */
2955 struct dmub_cmd_header header;
2956 /**
2957 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
2958 */
2959 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
2960 };
2961
2962 struct dmub_optc_state {
2963 uint32_t v_total_max;
2964 uint32_t v_total_min;
2965 uint32_t tg_inst;
2966 };
2967
2968 struct dmub_rb_cmd_drr_update {
2969 struct dmub_cmd_header header;
2970 struct dmub_optc_state dmub_optc_state_req;
2971 };
2972
2973 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
2974 uint32_t pix_clk_100hz;
2975 uint8_t max_ramp_step;
2976 uint8_t pipes;
2977 uint8_t min_refresh_in_hz;
2978 uint8_t padding[1];
2979 };
2980
2981 struct dmub_cmd_fw_assisted_mclk_switch_config {
2982 uint8_t fams_enabled;
2983 uint8_t visual_confirm_enabled;
2984 uint8_t padding[2];
2985 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS];
2986 };
2987
2988 struct dmub_rb_cmd_fw_assisted_mclk_switch {
2989 struct dmub_cmd_header header;
2990 struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
2991 };
2992
2993 /**
2994 * enum dmub_cmd_panel_cntl_type - Panel control command.
2995 */
2996 enum dmub_cmd_panel_cntl_type {
2997 /**
2998 * Initializes embedded panel hardware blocks.
2999 */
3000 DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
3001 /**
3002 * Queries backlight info for the embedded panel.
3003 */
3004 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
3005 };
3006
3007 /**
3008 * struct dmub_cmd_panel_cntl_data - Panel control data.
3009 */
3010 struct dmub_cmd_panel_cntl_data {
3011 uint32_t inst; /**< panel instance */
3012 uint32_t current_backlight; /* in/out */
3013 uint32_t bl_pwm_cntl; /* in/out */
3014 uint32_t bl_pwm_period_cntl; /* in/out */
3015 uint32_t bl_pwm_ref_div1; /* in/out */
3016 uint8_t is_backlight_on : 1; /* in/out */
3017 uint8_t is_powered_on : 1; /* in/out */
3018 uint8_t padding[3];
3019 uint32_t bl_pwm_ref_div2; /* in/out */
3020 uint8_t reserved[4];
3021 };
3022
3023 /**
3024 * struct dmub_rb_cmd_panel_cntl - Panel control command.
3025 */
3026 struct dmub_rb_cmd_panel_cntl {
3027 struct dmub_cmd_header header; /**< header */
3028 struct dmub_cmd_panel_cntl_data data; /**< payload */
3029 };
3030
3031 /**
3032 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3033 */
3034 struct dmub_cmd_lvtma_control_data {
3035 uint8_t uc_pwr_action; /**< LVTMA_ACTION */
3036 uint8_t reserved_0[3]; /**< For future use */
3037 uint8_t panel_inst; /**< LVTMA control instance */
3038 uint8_t reserved_1[3]; /**< For future use */
3039 };
3040
3041 /**
3042 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3043 */
3044 struct dmub_rb_cmd_lvtma_control {
3045 /**
3046 * Command header.
3047 */
3048 struct dmub_cmd_header header;
3049 /**
3050 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3051 */
3052 struct dmub_cmd_lvtma_control_data data;
3053 };
3054
3055 /**
3056 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
3057 */
3058 struct dmub_rb_cmd_transmitter_query_dp_alt_data {
3059 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
3060 uint8_t is_usb; /**< is phy is usb */
3061 uint8_t is_dp_alt_disable; /**< is dp alt disable */
3062 uint8_t is_dp4; /**< is dp in 4 lane */
3063 };
3064
3065 /**
3066 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
3067 */
3068 struct dmub_rb_cmd_transmitter_query_dp_alt {
3069 struct dmub_cmd_header header; /**< header */
3070 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */
3071 };
3072
3073 /**
3074 * Maximum number of bytes a chunk sent to DMUB for parsing
3075 */
3076 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
3077
3078 /**
3079 * Represent a chunk of CEA blocks sent to DMUB for parsing
3080 */
3081 struct dmub_cmd_send_edid_cea {
3082 uint16_t offset; /**< offset into the CEA block */
3083 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */
3084 uint16_t cea_total_length; /**< total length of the CEA block */
3085 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
3086 uint8_t pad[3]; /**< padding and for future expansion */
3087 };
3088
3089 /**
3090 * Result of VSDB parsing from CEA block
3091 */
3092 struct dmub_cmd_edid_cea_amd_vsdb {
3093 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */
3094 uint8_t freesync_supported; /**< 1 if Freesync is supported */
3095 uint16_t amd_vsdb_version; /**< AMD VSDB version */
3096 uint16_t min_frame_rate; /**< Maximum frame rate */
3097 uint16_t max_frame_rate; /**< Minimum frame rate */
3098 };
3099
3100 /**
3101 * Result of sending a CEA chunk
3102 */
3103 struct dmub_cmd_edid_cea_ack {
3104 uint16_t offset; /**< offset of the chunk into the CEA block */
3105 uint8_t success; /**< 1 if this sending of chunk succeeded */
3106 uint8_t pad; /**< padding and for future expansion */
3107 };
3108
3109 /**
3110 * Specify whether the result is an ACK/NACK or the parsing has finished
3111 */
3112 enum dmub_cmd_edid_cea_reply_type {
3113 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
3114 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */
3115 };
3116
3117 /**
3118 * Definition of a DMUB_CMD__EDID_CEA command.
3119 */
3120 struct dmub_rb_cmd_edid_cea {
3121 struct dmub_cmd_header header; /**< Command header */
3122 union dmub_cmd_edid_cea_data {
3123 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
3124 struct dmub_cmd_edid_cea_output { /**< output with results */
3125 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
3126 union {
3127 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
3128 struct dmub_cmd_edid_cea_ack ack;
3129 };
3130 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */
3131 } data; /**< Command data */
3132
3133 };
3134
3135 /**
3136 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.
3137 */
3138 struct dmub_cmd_cable_id_input {
3139 uint8_t phy_inst; /**< phy inst for cable id data */
3140 };
3141
3142 /**
3143 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.
3144 */
3145 struct dmub_cmd_cable_id_output {
3146 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */
3147 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */
3148 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */
3149 uint8_t RESERVED :2; /**< reserved means not defined */
3150 };
3151
3152 /**
3153 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command
3154 */
3155 struct dmub_rb_cmd_get_usbc_cable_id {
3156 struct dmub_cmd_header header; /**< Command header */
3157 /**
3158 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.
3159 */
3160 union dmub_cmd_cable_id_data {
3161 struct dmub_cmd_cable_id_input input; /**< Input */
3162 struct dmub_cmd_cable_id_output output; /**< Output */
3163 uint8_t output_raw; /**< Raw data output */
3164 } data;
3165 };
3166
3167 /**
3168 * union dmub_rb_cmd - DMUB inbox command.
3169 */
3170 union dmub_rb_cmd {
3171 /**
3172 * Elements shared with all commands.
3173 */
3174 struct dmub_rb_cmd_common cmd_common;
3175 /**
3176 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
3177 */
3178 struct dmub_rb_cmd_read_modify_write read_modify_write;
3179 /**
3180 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
3181 */
3182 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
3183 /**
3184 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
3185 */
3186 struct dmub_rb_cmd_burst_write burst_write;
3187 /**
3188 * Definition of a DMUB_CMD__REG_REG_WAIT command.
3189 */
3190 struct dmub_rb_cmd_reg_wait reg_wait;
3191 /**
3192 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
3193 */
3194 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
3195 /**
3196 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
3197 */
3198 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
3199 /**
3200 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
3201 */
3202 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
3203 /**
3204 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
3205 */
3206 struct dmub_rb_cmd_dpphy_init dpphy_init;
3207 /**
3208 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
3209 */
3210 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
3211 /**
3212 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command.
3213 */
3214 struct dmub_rb_cmd_domain_control domain_control;
3215 /**
3216 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
3217 */
3218 struct dmub_rb_cmd_psr_set_version psr_set_version;
3219 /**
3220 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
3221 */
3222 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
3223 /**
3224 * Definition of a DMUB_CMD__PSR_ENABLE command.
3225 */
3226 struct dmub_rb_cmd_psr_enable psr_enable;
3227 /**
3228 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
3229 */
3230 struct dmub_rb_cmd_psr_set_level psr_set_level;
3231 /**
3232 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
3233 */
3234 struct dmub_rb_cmd_psr_force_static psr_force_static;
3235 /**
3236 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
3237 */
3238 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
3239 /**
3240 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
3241 */
3242 struct dmub_rb_cmd_update_cursor_info update_cursor_info;
3243 /**
3244 * Definition of a DMUB_CMD__HW_LOCK command.
3245 * Command is used by driver and FW.
3246 */
3247 struct dmub_rb_cmd_lock_hw lock_hw;
3248 /**
3249 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3250 */
3251 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
3252 /**
3253 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3254 */
3255 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt;
3256 /**
3257 * Definition of a DMUB_CMD__PLAT_54186_WA command.
3258 */
3259 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
3260 /**
3261 * Definition of a DMUB_CMD__MALL command.
3262 */
3263 struct dmub_rb_cmd_mall mall;
3264 /**
3265 * Definition of a DMUB_CMD__CAB command.
3266 */
3267 struct dmub_rb_cmd_cab_for_ss cab;
3268
3269 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2;
3270
3271 /**
3272 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
3273 */
3274 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
3275
3276 /**
3277 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
3278 */
3279 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
3280
3281 /**
3282 * Definition of DMUB_CMD__PANEL_CNTL commands.
3283 */
3284 struct dmub_rb_cmd_panel_cntl panel_cntl;
3285 /**
3286 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
3287 */
3288 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
3289
3290 /**
3291 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
3292 */
3293 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
3294
3295 /**
3296 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
3297 */
3298 struct dmub_rb_cmd_abm_set_level abm_set_level;
3299
3300 /**
3301 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3302 */
3303 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
3304
3305 /**
3306 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
3307 */
3308 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
3309
3310 /**
3311 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
3312 */
3313 struct dmub_rb_cmd_abm_init_config abm_init_config;
3314
3315 /**
3316 * Definition of a DMUB_CMD__ABM_PAUSE command.
3317 */
3318 struct dmub_rb_cmd_abm_pause abm_pause;
3319
3320 /**
3321 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
3322 */
3323 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
3324
3325 /**
3326 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
3327 */
3328 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
3329
3330 /**
3331 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
3332 */
3333 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
3334
3335 /**
3336 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3337 */
3338 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
3339 struct dmub_rb_cmd_drr_update drr_update;
3340 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
3341
3342 /**
3343 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3344 */
3345 struct dmub_rb_cmd_lvtma_control lvtma_control;
3346 /**
3347 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
3348 */
3349 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;
3350 /**
3351 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
3352 */
3353 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;
3354 /**
3355 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
3356 */
3357 struct dmub_rb_cmd_set_config_access set_config_access;
3358 /**
3359 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
3360 */
3361 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;
3362 /**
3363 * Definition of a DMUB_CMD__EDID_CEA command.
3364 */
3365 struct dmub_rb_cmd_edid_cea edid_cea;
3366 /**
3367 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.
3368 */
3369 struct dmub_rb_cmd_get_usbc_cable_id cable_id;
3370
3371 /**
3372 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
3373 */
3374 struct dmub_rb_cmd_query_hpd_state query_hpd;
3375 /**
3376 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
3377 */
3378 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;
3379 };
3380
3381 /**
3382 * union dmub_rb_out_cmd - Outbox command
3383 */
3384 union dmub_rb_out_cmd {
3385 /**
3386 * Parameters common to every command.
3387 */
3388 struct dmub_rb_cmd_common cmd_common;
3389 /**
3390 * AUX reply command.
3391 */
3392 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
3393 /**
3394 * HPD notify command.
3395 */
3396 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
3397 /**
3398 * SET_CONFIG reply command.
3399 */
3400 struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
3401 };
3402 #pragma pack(pop)
3403
3404
3405 //==============================================================================
3406 //</DMUB_CMD>===================================================================
3407 //==============================================================================
3408 //< DMUB_RB>====================================================================
3409 //==============================================================================
3410
3411 #if defined(__cplusplus)
3412 extern "C" {
3413 #endif
3414
3415 /**
3416 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
3417 */
3418 struct dmub_rb_init_params {
3419 void *ctx; /**< Caller provided context pointer */
3420 void *base_address; /**< CPU base address for ring's data */
3421 uint32_t capacity; /**< Ringbuffer capacity in bytes */
3422 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
3423 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
3424 };
3425
3426 /**
3427 * struct dmub_rb - Inbox or outbox DMUB ringbuffer
3428 */
3429 struct dmub_rb {
3430 void *base_address; /**< CPU address for the ring's data */
3431 uint32_t rptr; /**< Read pointer for consumer in bytes */
3432 uint32_t wrpt; /**< Write pointer for producer in bytes */
3433 uint32_t capacity; /**< Ringbuffer capacity in bytes */
3434
3435 void *ctx; /**< Caller provided context pointer */
3436 void *dmub; /**< Pointer to the DMUB interface */
3437 };
3438
3439 /**
3440 * @brief Checks if the ringbuffer is empty.
3441 *
3442 * @param rb DMUB Ringbuffer
3443 * @return true if empty
3444 * @return false otherwise
3445 */
dmub_rb_empty(struct dmub_rb * rb)3446 static inline bool dmub_rb_empty(struct dmub_rb *rb)
3447 {
3448 return (rb->wrpt == rb->rptr);
3449 }
3450
3451 /**
3452 * @brief Checks if the ringbuffer is full
3453 *
3454 * @param rb DMUB Ringbuffer
3455 * @return true if full
3456 * @return false otherwise
3457 */
dmub_rb_full(struct dmub_rb * rb)3458 static inline bool dmub_rb_full(struct dmub_rb *rb)
3459 {
3460 uint32_t data_count;
3461
3462 if (rb->wrpt >= rb->rptr)
3463 data_count = rb->wrpt - rb->rptr;
3464 else
3465 data_count = rb->capacity - (rb->rptr - rb->wrpt);
3466
3467 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
3468 }
3469
3470 /**
3471 * @brief Pushes a command into the ringbuffer
3472 *
3473 * @param rb DMUB ringbuffer
3474 * @param cmd The command to push
3475 * @return true if the ringbuffer was not full
3476 * @return false otherwise
3477 */
dmub_rb_push_front(struct dmub_rb * rb,const union dmub_rb_cmd * cmd)3478 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
3479 const union dmub_rb_cmd *cmd)
3480 {
3481 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt);
3482 const uint64_t *src = (const uint64_t *)cmd;
3483 uint8_t i;
3484
3485 if (dmub_rb_full(rb))
3486 return false;
3487
3488 // copying data
3489 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
3490 *dst++ = *src++;
3491
3492 rb->wrpt += DMUB_RB_CMD_SIZE;
3493
3494 if (rb->wrpt >= rb->capacity)
3495 rb->wrpt %= rb->capacity;
3496
3497 return true;
3498 }
3499
3500 /**
3501 * @brief Pushes a command into the DMUB outbox ringbuffer
3502 *
3503 * @param rb DMUB outbox ringbuffer
3504 * @param cmd Outbox command
3505 * @return true if not full
3506 * @return false otherwise
3507 */
dmub_rb_out_push_front(struct dmub_rb * rb,const union dmub_rb_out_cmd * cmd)3508 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
3509 const union dmub_rb_out_cmd *cmd)
3510 {
3511 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
3512 const uint8_t *src = (const uint8_t *)cmd;
3513
3514 if (dmub_rb_full(rb))
3515 return false;
3516
3517 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
3518
3519 rb->wrpt += DMUB_RB_CMD_SIZE;
3520
3521 if (rb->wrpt >= rb->capacity)
3522 rb->wrpt %= rb->capacity;
3523
3524 return true;
3525 }
3526
3527 /**
3528 * @brief Returns the next unprocessed command in the ringbuffer.
3529 *
3530 * @param rb DMUB ringbuffer
3531 * @param cmd The command to return
3532 * @return true if not empty
3533 * @return false otherwise
3534 */
dmub_rb_front(struct dmub_rb * rb,union dmub_rb_cmd ** cmd)3535 static inline bool dmub_rb_front(struct dmub_rb *rb,
3536 union dmub_rb_cmd **cmd)
3537 {
3538 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
3539
3540 if (dmub_rb_empty(rb))
3541 return false;
3542
3543 *cmd = (union dmub_rb_cmd *)rb_cmd;
3544
3545 return true;
3546 }
3547
3548 /**
3549 * @brief Determines the next ringbuffer offset.
3550 *
3551 * @param rb DMUB inbox ringbuffer
3552 * @param num_cmds Number of commands
3553 * @param next_rptr The next offset in the ringbuffer
3554 */
dmub_rb_get_rptr_with_offset(struct dmub_rb * rb,uint32_t num_cmds,uint32_t * next_rptr)3555 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
3556 uint32_t num_cmds,
3557 uint32_t *next_rptr)
3558 {
3559 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
3560
3561 if (*next_rptr >= rb->capacity)
3562 *next_rptr %= rb->capacity;
3563 }
3564
3565 /**
3566 * @brief Returns a pointer to a command in the inbox.
3567 *
3568 * @param rb DMUB inbox ringbuffer
3569 * @param cmd The inbox command to return
3570 * @param rptr The ringbuffer offset
3571 * @return true if not empty
3572 * @return false otherwise
3573 */
dmub_rb_peek_offset(struct dmub_rb * rb,union dmub_rb_cmd ** cmd,uint32_t rptr)3574 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
3575 union dmub_rb_cmd **cmd,
3576 uint32_t rptr)
3577 {
3578 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
3579
3580 if (dmub_rb_empty(rb))
3581 return false;
3582
3583 *cmd = (union dmub_rb_cmd *)rb_cmd;
3584
3585 return true;
3586 }
3587
3588 /**
3589 * @brief Returns the next unprocessed command in the outbox.
3590 *
3591 * @param rb DMUB outbox ringbuffer
3592 * @param cmd The outbox command to return
3593 * @return true if not empty
3594 * @return false otherwise
3595 */
dmub_rb_out_front(struct dmub_rb * rb,union dmub_rb_out_cmd * cmd)3596 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
3597 union dmub_rb_out_cmd *cmd)
3598 {
3599 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);
3600 uint64_t *dst = (uint64_t *)cmd;
3601 uint8_t i;
3602
3603 if (dmub_rb_empty(rb))
3604 return false;
3605
3606 // copying data
3607 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
3608 *dst++ = *src++;
3609
3610 return true;
3611 }
3612
3613 /**
3614 * @brief Removes the front entry in the ringbuffer.
3615 *
3616 * @param rb DMUB ringbuffer
3617 * @return true if the command was removed
3618 * @return false if there were no commands
3619 */
dmub_rb_pop_front(struct dmub_rb * rb)3620 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
3621 {
3622 if (dmub_rb_empty(rb))
3623 return false;
3624
3625 rb->rptr += DMUB_RB_CMD_SIZE;
3626
3627 if (rb->rptr >= rb->capacity)
3628 rb->rptr %= rb->capacity;
3629
3630 return true;
3631 }
3632
3633 /**
3634 * @brief Flushes commands in the ringbuffer to framebuffer memory.
3635 *
3636 * Avoids a race condition where DMCUB accesses memory while
3637 * there are still writes in flight to framebuffer.
3638 *
3639 * @param rb DMUB ringbuffer
3640 */
dmub_rb_flush_pending(const struct dmub_rb * rb)3641 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
3642 {
3643 uint32_t rptr = rb->rptr;
3644 uint32_t wptr = rb->wrpt;
3645
3646 while (rptr != wptr) {
3647 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
3648 uint8_t i;
3649
3650 /* Don't remove this.
3651 * The contents need to actually be read from the ring buffer
3652 * for this function to be effective.
3653 */
3654 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
3655 (void)READ_ONCE(*data++);
3656
3657 rptr += DMUB_RB_CMD_SIZE;
3658 if (rptr >= rb->capacity)
3659 rptr %= rb->capacity;
3660 }
3661 }
3662
3663 /**
3664 * @brief Initializes a DMCUB ringbuffer
3665 *
3666 * @param rb DMUB ringbuffer
3667 * @param init_params initial configuration for the ringbuffer
3668 */
dmub_rb_init(struct dmub_rb * rb,struct dmub_rb_init_params * init_params)3669 static inline void dmub_rb_init(struct dmub_rb *rb,
3670 struct dmub_rb_init_params *init_params)
3671 {
3672 rb->base_address = init_params->base_address;
3673 rb->capacity = init_params->capacity;
3674 rb->rptr = init_params->read_ptr;
3675 rb->wrpt = init_params->write_ptr;
3676 }
3677
3678 /**
3679 * @brief Copies output data from in/out commands into the given command.
3680 *
3681 * @param rb DMUB ringbuffer
3682 * @param cmd Command to copy data into
3683 */
dmub_rb_get_return_data(struct dmub_rb * rb,union dmub_rb_cmd * cmd)3684 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
3685 union dmub_rb_cmd *cmd)
3686 {
3687 // Copy rb entry back into command
3688 uint8_t *rd_ptr = (rb->rptr == 0) ?
3689 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
3690 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
3691
3692 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
3693 }
3694
3695 #if defined(__cplusplus)
3696 }
3697 #endif
3698
3699 //==============================================================================
3700 //</DMUB_RB>====================================================================
3701 //==============================================================================
3702
3703 #endif /* _DMUB_CMD_H_ */
3704