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Searched refs:ebit (Results 1 – 5 of 5) sorted by relevance

/drivers/regulator/
Dda903x-regulator.c309 #define DA903x_LDO(_pmic, _id, min, max, step, vreg, shift, nbits, ereg, ebit) \ argument
326 .enable_bit = (ebit), \
329 #define DA903x_DVC(_pmic, _id, min, max, step, vreg, nbits, ureg, ubit, ereg, ebit) \ argument
348 .enable_bit = (ebit), \
351 #define DA9034_LDO(_id, min, max, step, vreg, shift, nbits, ereg, ebit) \ argument
352 DA903x_LDO(DA9034, _id, min, max, step, vreg, shift, nbits, ereg, ebit)
354 #define DA9030_LDO(_id, min, max, step, vreg, shift, nbits, ereg, ebit) \ argument
355 DA903x_LDO(DA9030, _id, min, max, step, vreg, shift, nbits, ereg, ebit)
357 #define DA9030_DVC(_id, min, max, step, vreg, nbits, ureg, ubit, ereg, ebit) \ argument
359 ereg, ebit)
[all …]
D88pm8607.c231 #define PM8606_PREG(ereg, ebit) \ argument
242 .enable_mask = (ebit), \
247 #define PM8607_DVC(vreg, ureg, ubit, ereg, ebit) \ argument
264 .enable_mask = 1 << (ebit), \
270 #define PM8607_LDO(_id, vreg, shift, ereg, ebit) \ argument
285 .enable_mask = 1 << (ebit), \
D88pm800-regulator.c86 #define PM800_BUCK(match, vreg, ereg, ebit, amax, volt_ranges, n_volt) \ argument
102 .enable_mask = 1 << (ebit), \
116 #define PM800_LDO(match, vreg, ereg, ebit, amax, ldo_volt_table) \ argument
130 .enable_mask = 1 << (ebit), \
/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
Dphy_lcn.c1037 u16 ebit = enable ? 1 : 0; in wlc_lcnphy_rx_gain_override_enable() local
1039 mod_phy_reg(pi, 0x4b0, (0x1 << 8), ebit << 8); in wlc_lcnphy_rx_gain_override_enable()
1041 mod_phy_reg(pi, 0x44c, (0x1 << 0), ebit << 0); in wlc_lcnphy_rx_gain_override_enable()
1044 mod_phy_reg(pi, 0x44c, (0x1 << 4), ebit << 4); in wlc_lcnphy_rx_gain_override_enable()
1045 mod_phy_reg(pi, 0x44c, (0x1 << 6), ebit << 6); in wlc_lcnphy_rx_gain_override_enable()
1046 mod_phy_reg(pi, 0x4b0, (0x1 << 5), ebit << 5); in wlc_lcnphy_rx_gain_override_enable()
1047 mod_phy_reg(pi, 0x4b0, (0x1 << 6), ebit << 6); in wlc_lcnphy_rx_gain_override_enable()
1049 mod_phy_reg(pi, 0x4b0, (0x1 << 12), ebit << 12); in wlc_lcnphy_rx_gain_override_enable()
1050 mod_phy_reg(pi, 0x4b0, (0x1 << 13), ebit << 13); in wlc_lcnphy_rx_gain_override_enable()
1051 mod_phy_reg(pi, 0x4b0, (0x1 << 5), ebit << 5); in wlc_lcnphy_rx_gain_override_enable()
[all …]
/drivers/staging/qlge/
Dqlge.h2259 int qlge_wait_reg_rdy(struct qlge_adapter *qdev, u32 reg, u32 bit, u32 ebit);