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Searched refs:fp_horiz_regs (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/nouveau/dispnv04/
Ddfp.c301 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
302 regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; in nv04_dfp_mode_set()
306 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay; in nv04_dfp_mode_set()
308 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1; in nv04_dfp_mode_set()
309 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1; in nv04_dfp_mode_set()
310 regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; in nv04_dfp_mode_set()
311 regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew; in nv04_dfp_mode_set()
312 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
396 regp->fp_horiz_regs[FP_VALID_START] += diff / 2; in nv04_dfp_mode_set()
397 regp->fp_horiz_regs[FP_VALID_END] -= diff / 2; in nv04_dfp_mode_set()
Dtvmodesnv17.c572 regs->fp_horiz_regs[FP_VALID_START] = hmargin; in nv17_ctv_update_rescaler()
573 regs->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - hmargin - 1; in nv17_ctv_update_rescaler()
583 regs->fp_horiz_regs[FP_VALID_START]); in nv17_ctv_update_rescaler()
585 regs->fp_horiz_regs[FP_VALID_END]); in nv17_ctv_update_rescaler()
Dtvnv17.c533 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; in nv17_tv_mode_set()
534 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; in nv17_tv_mode_set()
535 regs->fp_horiz_regs[FP_SYNC_START] = in nv17_tv_mode_set()
537 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; in nv17_tv_mode_set()
538 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay + in nv17_tv_mode_set()
Ddisp.h54 uint32_t fp_horiz_regs[7]; member
Dhw.c430 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); in nv_save_state_ramdac()
508 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); in nv_load_state_ramdac()