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Searched refs:gpu (Results 1 – 25 of 94) sorted by relevance

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/drivers/gpu/drm/etnaviv/
Detnaviv_gpu.c39 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
41 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
45 *value = gpu->identity.model; in etnaviv_gpu_get_param()
49 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
53 *value = gpu->identity.features; in etnaviv_gpu_get_param()
57 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
61 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
65 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
69 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
73 *value = gpu->identity.minor_features4; in etnaviv_gpu_get_param()
[all …]
Detnaviv_buffer.c89 static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu, in etnaviv_cmd_select_pipe() argument
94 lockdep_assert_held(&gpu->lock); in etnaviv_cmd_select_pipe()
102 if (gpu->exec_state == ETNA_PIPE_2D) in etnaviv_cmd_select_pipe()
104 else if (gpu->exec_state == ETNA_PIPE_3D) in etnaviv_cmd_select_pipe()
115 static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu, in etnaviv_buffer_dump() argument
121 dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n", in etnaviv_buffer_dump()
123 &gpu->mmu_context->cmdbuf_mapping) + in etnaviv_buffer_dump()
151 static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu, in etnaviv_buffer_reserve() argument
158 &gpu->mmu_context->cmdbuf_mapping) + in etnaviv_buffer_reserve()
162 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu) in etnaviv_buffer_init() argument
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Detnaviv_sched.c28 dev_dbg(submit->gpu->dev, "skipping bad job\n"); in etnaviv_sched_run_job()
37 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_timedout_job() local
42 drm_sched_stop(&gpu->sched, sched_job); in etnaviv_sched_timedout_job()
56 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
57 change = dma_addr - gpu->hangcheck_dma_addr; in etnaviv_sched_timedout_job()
58 if (gpu->completed_fence != gpu->hangcheck_fence || in etnaviv_sched_timedout_job()
60 gpu->hangcheck_dma_addr = dma_addr; in etnaviv_sched_timedout_job()
61 gpu->hangcheck_fence = gpu->completed_fence; in etnaviv_sched_timedout_job()
70 etnaviv_gpu_recover_hang(gpu); in etnaviv_sched_timedout_job()
72 drm_sched_resubmit_jobs(&gpu->sched); in etnaviv_sched_timedout_job()
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Detnaviv_perfmon.c18 u32 (*sample)(struct etnaviv_gpu *gpu,
40 static u32 perf_reg_read(struct etnaviv_gpu *gpu, in perf_reg_read() argument
44 gpu_write(gpu, domain->profile_config, signal->data); in perf_reg_read()
46 return gpu_read(gpu, domain->profile_read); in perf_reg_read()
49 static inline void pipe_select(struct etnaviv_gpu *gpu, u32 clock, unsigned pipe) in pipe_select() argument
54 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_select()
57 static u32 pipe_perf_reg_read(struct etnaviv_gpu *gpu, in pipe_perf_reg_read() argument
61 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_perf_reg_read()
65 for (i = 0; i < gpu->identity.pixel_pipes; i++) { in pipe_perf_reg_read()
66 pipe_select(gpu, clock, i); in pipe_perf_reg_read()
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Detnaviv_drv.c37 struct etnaviv_gpu *g = priv->gpu[i]; in load_gpu()
44 priv->gpu[i] = NULL; in load_gpu()
67 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_open() local
70 if (gpu) { in etnaviv_open()
71 sched = &gpu->sched; in etnaviv_open()
94 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_postclose() local
96 if (gpu) in etnaviv_postclose()
130 static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m) in etnaviv_mmu_show() argument
135 seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev)); in etnaviv_mmu_show()
142 mutex_lock(&gpu->lock); in etnaviv_mmu_show()
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Detnaviv_iommu_v2.c165 static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_nonsec() argument
172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
175 if (gpu->mmu_context) in etnaviv_iommuv2_restore_nonsec()
176 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv2_restore_nonsec()
177 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv2_restore_nonsec()
179 prefetch = etnaviv_buffer_config_mmuv2(gpu, in etnaviv_iommuv2_restore_nonsec()
182 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_nonsec()
184 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_nonsec()
186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
189 static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_sec() argument
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Detnaviv_gpu.h85 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
152 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() argument
154 writel(data, gpu->mmio + reg); in gpu_write()
157 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() argument
159 return readl(gpu->mmio + reg); in gpu_read()
162 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
164 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
165 bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
168 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
171 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu);
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/drivers/gpu/drm/msm/
Dmsm_gpu.c26 static int enable_pwrrail(struct msm_gpu *gpu) in enable_pwrrail() argument
28 struct drm_device *dev = gpu->dev; in enable_pwrrail()
31 if (gpu->gpu_reg) { in enable_pwrrail()
32 ret = regulator_enable(gpu->gpu_reg); in enable_pwrrail()
39 if (gpu->gpu_cx) { in enable_pwrrail()
40 ret = regulator_enable(gpu->gpu_cx); in enable_pwrrail()
50 static int disable_pwrrail(struct msm_gpu *gpu) in disable_pwrrail() argument
52 if (gpu->gpu_cx) in disable_pwrrail()
53 regulator_disable(gpu->gpu_cx); in disable_pwrrail()
54 if (gpu->gpu_reg) in disable_pwrrail()
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Dmsm_gpu_devfreq.c22 struct msm_gpu *gpu = dev_to_gpu(dev); in msm_devfreq_target() local
23 struct msm_gpu_devfreq *df = &gpu->devfreq; in msm_devfreq_target()
36 if (gpu->funcs->gpu_set_freq) { in msm_devfreq_target()
38 gpu->funcs->gpu_set_freq(gpu, opp, df->suspended); in msm_devfreq_target()
41 clk_set_rate(gpu->core_clk, *freq); in msm_devfreq_target()
49 static unsigned long get_freq(struct msm_gpu *gpu) in get_freq() argument
51 if (gpu->funcs->gpu_get_freq) in get_freq()
52 return gpu->funcs->gpu_get_freq(gpu); in get_freq()
54 return clk_get_rate(gpu->core_clk); in get_freq()
57 static void get_raw_dev_status(struct msm_gpu *gpu, in get_raw_dev_status() argument
[all …]
Dmsm_gpu.h48 int (*get_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
50 int (*set_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
52 int (*hw_init)(struct msm_gpu *gpu);
53 int (*pm_suspend)(struct msm_gpu *gpu);
54 int (*pm_resume)(struct msm_gpu *gpu);
55 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
56 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
58 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
59 void (*recover)(struct msm_gpu *gpu);
60 void (*destroy)(struct msm_gpu *gpu);
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Dmsm_debugfs.c36 struct msm_gpu *gpu = priv->gpu; in msm_gpu_show() local
39 ret = mutex_lock_interruptible(&gpu->lock); in msm_gpu_show()
43 drm_printf(&p, "%s Status:\n", gpu->name); in msm_gpu_show()
44 gpu->funcs->show(gpu, show_priv->state, &p); in msm_gpu_show()
46 mutex_unlock(&gpu->lock); in msm_gpu_show()
56 struct msm_gpu *gpu = priv->gpu; in msm_gpu_release() local
58 mutex_lock(&gpu->lock); in msm_gpu_release()
59 gpu->funcs->gpu_state_put(show_priv->state); in msm_gpu_release()
60 mutex_unlock(&gpu->lock); in msm_gpu_release()
71 struct msm_gpu *gpu = priv->gpu; in msm_gpu_open() local
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/drivers/gpu/drm/msm/adreno/
Da4xx_gpu.c22 static void a4xx_dump(struct msm_gpu *gpu);
23 static bool a4xx_idle(struct msm_gpu *gpu);
25 static void a4xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a4xx_submit() argument
37 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a4xx_submit()
69 adreno_flush(gpu, ring, REG_A4XX_CP_RB_WPTR); in a4xx_submit()
76 static void a4xx_enable_hwcg(struct msm_gpu *gpu) in a4xx_enable_hwcg() argument
78 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a4xx_enable_hwcg()
81 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
83 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
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Da5xx_gpu.c17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr() argument
23 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in update_shadow_rptr()
33 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument
36 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
46 update_shadow_rptr(gpu, ring); in a5xx_flush()
63 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
66 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit_in_rb() argument
78 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a5xx_submit_in_rb()
112 a5xx_flush(gpu, ring, true); in a5xx_submit_in_rb()
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Da3xx_gpu.c28 static void a3xx_dump(struct msm_gpu *gpu);
29 static bool a3xx_idle(struct msm_gpu *gpu);
31 static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a3xx_submit() argument
43 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a3xx_submit()
82 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_submit()
85 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init() argument
87 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
108 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_me_init()
109 return a3xx_idle(gpu); in a3xx_me_init()
112 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init() argument
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Da5xx_power.c103 static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq) in _get_mvolts() argument
105 struct drm_device *dev = gpu->dev; in _get_mvolts()
122 static void a530_lm_setup(struct msm_gpu *gpu) in a530_lm_setup() argument
124 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a530_lm_setup()
130 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a530_lm_setup()
134 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007); in a530_lm_setup()
135 gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); in a530_lm_setup()
136 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); in a530_lm_setup()
139 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); in a530_lm_setup()
141 gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage); in a530_lm_setup()
[all …]
Dadreno_gpu.h50 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
148 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu) in adreno_is_a2xx() argument
150 return (gpu->revn < 300); in adreno_is_a2xx()
153 static inline bool adreno_is_a20x(struct adreno_gpu *gpu) in adreno_is_a20x() argument
155 return (gpu->revn < 210); in adreno_is_a20x()
158 static inline bool adreno_is_a225(struct adreno_gpu *gpu) in adreno_is_a225() argument
160 return gpu->revn == 225; in adreno_is_a225()
163 static inline bool adreno_is_a305(struct adreno_gpu *gpu) in adreno_is_a305() argument
165 return gpu->revn == 305; in adreno_is_a305()
168 static inline bool adreno_is_a306(struct adreno_gpu *gpu) in adreno_is_a306() argument
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Da2xx_gpu.c10 static void a2xx_dump(struct msm_gpu *gpu);
11 static bool a2xx_idle(struct msm_gpu *gpu);
13 static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a2xx_submit() argument
25 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a2xx_submit()
51 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_submit()
54 static bool a2xx_me_init(struct msm_gpu *gpu) in a2xx_me_init() argument
56 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
97 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_me_init()
98 return a2xx_idle(gpu); in a2xx_me_init()
101 static int a2xx_hw_init(struct msm_gpu *gpu) in a2xx_hw_init() argument
[all …]
Da6xx_gpu.c18 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle() argument
20 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_check_idle()
28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
32 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
36 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle() argument
39 if (!adreno_idle(gpu, ring)) in a6xx_idle()
42 if (spin_until(_a6xx_check_idle(gpu))) { in a6xx_idle()
44 gpu->name, __builtin_return_address(0), in a6xx_idle()
45 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle()
[all …]
Da5xx_preempt.c25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
61 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
63 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
66 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); in get_next_ring()
79 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer() local
80 struct drm_device *dev = gpu->dev; in a5xx_preempt_timer()
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Da5xx_debugfs.c14 static void pfp_print(struct msm_gpu *gpu, struct drm_printer *p) in pfp_print() argument
21 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i); in pfp_print()
23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
27 static void me_print(struct msm_gpu *gpu, struct drm_printer *p) in me_print() argument
34 gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i); in me_print()
36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
40 static void meq_print(struct msm_gpu *gpu, struct drm_printer *p) in meq_print() argument
45 gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); in meq_print()
49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
53 static void roq_print(struct msm_gpu *gpu, struct drm_printer *p) in roq_print() argument
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Dadreno_gpu.c30 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt() argument
33 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt()
85 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev); in zap_shader_load_mdt()
90 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); in zap_shader_load_mdt()
140 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) { in zap_shader_load_mdt()
176 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) in adreno_zap_shader_load() argument
178 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_zap_shader_load()
179 struct platform_device *pdev = gpu->pdev; in adreno_zap_shader_load()
191 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); in adreno_zap_shader_load()
200 adreno_iommu_create_address_space(struct msm_gpu *gpu, in adreno_iommu_create_address_space() argument
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Da6xx_gpu_state.c120 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init() argument
123 dumper->ptr = msm_gem_kernel_new(gpu->dev, in a6xx_crashdumper_init()
124 SZ_1M, MSM_BO_WC, gpu->aspace, in a6xx_crashdumper_init()
133 static int a6xx_crashdumper_run(struct msm_gpu *gpu, in a6xx_crashdumper_run() argument
136 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_crashdumper_run()
150 gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE_LO, dumper->iova); in a6xx_crashdumper_run()
152 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
154 ret = gpu_poll_timeout(gpu, REG_A6XX_CP_CRASH_DUMP_STATUS, val, in a6xx_crashdumper_run()
157 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
163 static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, in debugbus_read() argument
[all …]
Dadreno_device.c411 struct msm_gpu *gpu = NULL; in adreno_load_gpu() local
416 gpu = dev_to_gpu(&pdev->dev); in adreno_load_gpu()
418 if (!gpu) { in adreno_load_gpu()
423 adreno_gpu = to_adreno_gpu(gpu); in adreno_load_gpu()
448 mutex_lock(&gpu->lock); in adreno_load_gpu()
449 ret = msm_gpu_hw_init(gpu); in adreno_load_gpu()
450 mutex_unlock(&gpu->lock); in adreno_load_gpu()
459 if (gpu->funcs->debugfs_init) { in adreno_load_gpu()
460 gpu->funcs->debugfs_init(gpu, dev->primary); in adreno_load_gpu()
461 gpu->funcs->debugfs_init(gpu, dev->render); in adreno_load_gpu()
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Da5xx_gpu.h52 void a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor);
135 int a5xx_power_init(struct msm_gpu *gpu);
136 void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
138 static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, in spin_usecs() argument
143 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
154 bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
155 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
157 void a5xx_preempt_init(struct msm_gpu *gpu);
158 void a5xx_preempt_hw_init(struct msm_gpu *gpu);
159 void a5xx_preempt_trigger(struct msm_gpu *gpu);
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/drivers/gpu/drm/amd/amdkfd/
Dkfd_topology.c107 return top_dev->gpu; in kfd_device_by_id()
118 if (top_dev->gpu && top_dev->gpu->pdev == pdev) { in kfd_device_by_pci_dev()
119 device = top_dev->gpu; in kfd_device_by_pci_dev()
136 if (top_dev->gpu && top_dev->gpu->adev == adev) { in kfd_device_by_adev()
137 device = top_dev->gpu; in kfd_device_by_adev()
296 if (iolink->gpu && kfd_devcgroup_check_permission(iolink->gpu)) in iolink_show()
336 if (mem->gpu && kfd_devcgroup_check_permission(mem->gpu)) in mem_show()
368 if (cache->gpu && kfd_devcgroup_check_permission(cache->gpu)) in kfd_cache_show()
450 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu)) in node_show()
459 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu)) in node_show()
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