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Searched refs:h_back_porch (Results 1 – 9 of 9) sorted by relevance

/drivers/video/fbdev/core/
Dfbcvt.c49 u32 h_back_porch; member
264 mode->left_margin = cvt->h_back_porch; in fb_cvt_convert_to_mode()
358 cvt.h_back_porch = cvt.hblank/2 + cvt.h_margin; in fb_find_mode_cvt()
359 cvt.h_front_porch = cvt.hblank - cvt.hsync - cvt.h_back_porch + in fb_find_mode_cvt()
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_encoder_phys_vid.c76 timing->h_back_porch = mode->htotal - mode->hsync_end; in drm_mode_to_intf_timing_params()
96 timing->h_back_porch += timing->h_front_porch; in drm_mode_to_intf_timing_params()
111 timing->h_back_porch = timing->h_back_porch >> 1; in drm_mode_to_intf_timing_params()
121 timing->h_back_porch + timing->h_front_porch + in get_horizontal_total()
Ddpu_hw_intf.c115 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + in dpu_hw_intf_setup_timing_engine()
125 hsync_start_x = p->h_back_porch + p->hsync_pulse_width; in dpu_hw_intf_setup_timing_engine()
174 display_v_start += p->hsync_pulse_width + p->h_back_porch; in dpu_hw_intf_setup_timing_engine()
Ddpu_hw_intf.h23 u32 h_back_porch; member
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_hpo_dp_stream_encoder.c197 uint32_t h_back_porch; in dcn31_hpo_dp_stream_enc_set_stream_attribute() local
349 h_back_porch = h_blank - hw_crtc_timing.h_front_porch - in dcn31_hpo_dp_stream_enc_set_stream_attribute()
353 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; in dcn31_hpo_dp_stream_enc_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.c257 uint32_t h_back_porch; in enc1_stream_encoder_dp_set_stream_attribute() local
430 h_back_porch = h_blank - hw_crtc_timing.h_front_porch - in enc1_stream_encoder_dp_set_stream_attribute()
434 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; in enc1_stream_encoder_dp_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.c279 uint32_t h_back_porch; in dce110_stream_encoder_dp_set_stream_attribute() local
465 h_back_porch = h_blank - hw_crtc_timing.h_front_porch - in dce110_stream_encoder_dp_set_stream_attribute()
469 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; in dce110_stream_encoder_dp_set_stream_attribute()
/drivers/gpu/drm/tegra/
Dhdmi.c1212 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey; in tegra_hdmi_encoder_enable() local
1239 h_back_porch = mode->htotal - mode->hsync_end; in tegra_hdmi_encoder_enable()
1267 pulse_start = 1 + h_sync_width + h_back_porch - 10; in tegra_hdmi_encoder_enable()
1319 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch + in tegra_hdmi_encoder_enable()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_timing_generator.c1119 uint32_t h_back_porch, hsync_offset, h_sync_start; in dce110_timing_generator_validate_timing() local
1158 h_back_porch = h_blank - (h_sync_start - in dce110_timing_generator_validate_timing()
1163 if (h_back_porch < tg110->min_h_back_porch) in dce110_timing_generator_validate_timing()