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Searched refs:hsync_end_x (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4_dsi_encoder.c48 uint32_t hsync_start_x, hsync_end_x; in mdp4_dsi_encoder_mode_set() local
64 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dsi_encoder_mode_set()
78 MDP4_DSI_DISPLAY_HCTRL_END(hsync_end_x)); in mdp4_dsi_encoder_mode_set()
Dmdp4_dtv_encoder.c47 uint32_t hsync_start_x, hsync_end_x; in mdp4_dtv_encoder_mode_set() local
67 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dtv_encoder_mode_set()
81 MDP4_DTV_DISPLAY_HCTRL_END(hsync_end_x)); in mdp4_dtv_encoder_mode_set()
Dmdp4_lcdc_encoder.c222 uint32_t hsync_start_x, hsync_end_x; in mdp4_lcdc_encoder_mode_set() local
242 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_lcdc_encoder_mode_set()
256 MDP4_LCDC_DISPLAY_HCTRL_END(hsync_end_x)); in mdp4_lcdc_encoder_mode_set()
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_intf.c97 u32 hsync_start_x, hsync_end_x; in dpu_hw_intf_setup_timing_engine() local
126 hsync_end_x = hsync_period - p->h_front_porch - 1; in dpu_hw_intf_setup_timing_engine()
155 display_hctl = (hsync_end_x << 16) | hsync_start_x; in dpu_hw_intf_setup_timing_engine()
/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_encoder.c41 uint32_t hsync_start_x, hsync_end_x; in mdp5_vid_encoder_mode_set() local
85 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp5_vid_encoder_mode_set()
111 MDP5_INTF_DISPLAY_HCTL_END(hsync_end_x)); in mdp5_vid_encoder_mode_set()
/drivers/gpu/drm/msm/dp/
Ddp_catalog.c815 u32 hsync_start_x, hsync_end_x; in dp_catalog_panel_tpg_enable() local
834 hsync_end_x = hsync_period - (drm_mode->hsync_start - in dp_catalog_panel_tpg_enable()
841 display_hctl = (hsync_end_x << 16) | hsync_start_x; in dp_catalog_panel_tpg_enable()