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Searched refs:i915_mmio_reg_offset (Results 1 – 25 of 46) sorted by relevance

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/drivers/gpu/drm/i915/gvt/
Dinterrupt.c157 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) in regbase_to_irq_info()
335 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) in update_upstream_irq()
337 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); in update_upstream_irq()
364 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); in update_upstream_irq()
370 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
372 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
454 reg_base = i915_mmio_reg_offset(info->reg_base); in propagate_event()
512 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & in gen8_check_pending_irq()
523 reg_base = i915_mmio_reg_offset(info->reg_base); in gen8_check_pending_irq()
529 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) in gen8_check_pending_irq()
Dedid.c383 if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_read()
385 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_read()
413 if (offset == i915_mmio_reg_offset(PCH_GMBUS0)) in intel_gvt_i2c_handle_gmbus_write()
415 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1)) in intel_gvt_i2c_handle_gmbus_write()
417 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_write()
419 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_write()
Dscheduler.c92 i915_mmio_reg_offset(EU_PERF_CNTL0), in sr_oa_regs()
93 i915_mmio_reg_offset(EU_PERF_CNTL1), in sr_oa_regs()
94 i915_mmio_reg_offset(EU_PERF_CNTL2), in sr_oa_regs()
95 i915_mmio_reg_offset(EU_PERF_CNTL3), in sr_oa_regs()
96 i915_mmio_reg_offset(EU_PERF_CNTL4), in sr_oa_regs()
97 i915_mmio_reg_offset(EU_PERF_CNTL5), in sr_oa_regs()
98 i915_mmio_reg_offset(EU_PERF_CNTL6), in sr_oa_regs()
114 i915_mmio_reg_offset(GEN8_OACTXCONTROL); in sr_oa_regs()
274 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
278 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
[all …]
Dmmio_context.c227 *cs++ = i915_mmio_reg_offset(mmio->reg); in restore_context_mmio_for_inhibit()
257 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit()
284 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); in restore_render_mocs_l3cc_for_inhibit()
540 i915_mmio_reg_offset(mmio->reg), in switch_mmio()
Dhandlers.c161 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
164 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
778 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) { in force_nonpriv_write()
796 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) in ddi_buf_ctl_mmio_write()
878 end = i915_mmio_reg_offset(i915_end); in calc_index()
1073 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) in trigger_aux_channel_interrupt()
1076 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) in trigger_aux_channel_interrupt()
1079 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) in trigger_aux_channel_interrupt()
1082 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) in trigger_aux_channel_interrupt()
1953 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) || in mmio_read_from_hw()
[all …]
Dgvt.h462 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
466 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
/drivers/gpu/drm/i915/gt/
Dintel_lrc.c1184 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1192 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1193 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1198 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1199 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1212 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_restore_scratch()
1228 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_cmd_buf_wa()
1236 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_cmd_buf_wa()
1237 *cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0)); in gen12_emit_cmd_buf_wa()
1251 *cs++ = i915_mmio_reg_offset(GEN12_STATE_ACK_DEBUG); in dg2_emit_rcs_hang_wabb()
[all …]
Dselftest_lrc.c304 i915_mmio_reg_offset(RING_START(engine->mmio_base)), in live_lrc_fixed()
309 i915_mmio_reg_offset(RING_CTL(engine->mmio_base)), in live_lrc_fixed()
314 i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)), in live_lrc_fixed()
319 i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)), in live_lrc_fixed()
324 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), in live_lrc_fixed()
329 i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)), in live_lrc_fixed()
334 i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(engine->mmio_base)), in live_lrc_fixed()
339 i915_mmio_reg_offset(RING_INDIRECT_CTX(engine->mmio_base)), in live_lrc_fixed()
344 i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(engine->mmio_base)), in live_lrc_fixed()
349 i915_mmio_reg_offset(RING_CTX_TIMESTAMP(engine->mmio_base)), in live_lrc_fixed()
[all …]
Dselftest_workarounds.c161 *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i)); in read_nonprivs()
188 return i915_mmio_reg_offset(reg); in get_whitelist_reg()
469 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in whitelist_writable_count()
524 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in check_dirty_whitelist()
882 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in read_whitelisted_registers()
918 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in scrub_whitelisted_registers()
977 u32 offset = i915_mmio_reg_offset(reg); in find_reg()
981 i915_mmio_reg_offset(tbl->reg) == offset) in find_reg()
1005 i915_mmio_reg_offset(reg), a, b); in result_eq()
1027 i915_mmio_reg_offset(reg), a); in result_neq()
[all …]
Dintel_workarounds.c89 unsigned int addr = i915_mmio_reg_offset(wa->reg); in _wa_add()
117 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { in _wa_add()
119 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { in _wa_add()
126 i915_mmio_reg_offset(wa_->reg), in _wa_add()
145 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == in _wa_add()
146 i915_mmio_reg_offset(wa_[1].reg)); in _wa_add()
147 if (i915_mmio_reg_offset(wa_[1].reg) > in _wa_add()
148 i915_mmio_reg_offset(wa_[0].reg)) in _wa_add()
849 *cs++ = i915_mmio_reg_offset(wa->reg); in intel_engine_emit_ctx_wa()
1608 name, from, i915_mmio_reg_offset(wa->reg), in wa_verify()
[all …]
Dintel_ring_submission.c664 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); in load_pd_dir()
668 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
673 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
678 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); in load_pd_dir()
726 *cs++ = i915_mmio_reg_offset( in mi_set_context()
781 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
788 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
823 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); in remap_l3_slice()
Dselftest_rps.c102 *cs++ = i915_mmio_reg_offset(CS_GPR(i)); in create_spin_counter()
104 *cs++ = i915_mmio_reg_offset(CS_GPR(i)) + 4; in create_spin_counter()
109 *cs++ = i915_mmio_reg_offset(CS_GPR(INC)); in create_spin_counter()
124 *cs++ = i915_mmio_reg_offset(CS_GPR(COUNT)); in create_spin_counter()
207 i915_mmio_reg_offset(BXT_RP_STATE_CAP), in show_pstate_limits()
212 i915_mmio_reg_offset(GEN9_RP_STATE_LIMITS), in show_pstate_limits()
Dgen8_engine_cs.c211 *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset; in gen12_emit_aux_table_inv()
219 *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset; in gen12_emit_aux_table_inv()
457 *cs++ = i915_mmio_reg_offset(RING_PREDICATE_RESULT(0)); in __gen125_emit_bb_start()
Dselftest_mocs.c150 u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); in read_l3cc_table()
195 u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); in check_l3cc_table()
Dgen7_renderclear.c400 batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); in emit_batch()
405 batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1)); in emit_batch()
Dselftest_rc6.c147 *cs++ = i915_mmio_reg_offset(GEN8_RC6_CTX_INFO); in __live_rc6_ctx()
Dintel_rc6.c759 i = (i915_mmio_reg_offset(reg) - in intel_rc6_residency_ns()
760 i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32); in intel_rc6_residency_ns()
/drivers/gpu/drm/i915/
Di915_reg_defs.h109 static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg) in i915_mmio_reg_offset() function
116 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); in i915_mmio_reg_equal()
Dintel_uncore.h314 u32 offset = i915_mmio_reg_offset(reg); \
324 u32 offset = i915_mmio_reg_offset(reg); \
481 readl(base + i915_mmio_reg_offset(reg))
483 writel(value, base + i915_mmio_reg_offset(reg))
Di915_perf.c1627 *cs++ = i915_mmio_reg_offset(reg) + 4 * d; in save_restore_register()
1706 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4; in alloc_noa_wait()
1709 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base)); in alloc_noa_wait()
1710 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)); in alloc_noa_wait()
1724 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4; in alloc_noa_wait()
1727 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base)); in alloc_noa_wait()
1728 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)); in alloc_noa_wait()
1747 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE)); in alloc_noa_wait()
1748 *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE)); in alloc_noa_wait()
1766 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)); in alloc_noa_wait()
[all …]
Di915_ioctl.c55 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); in i915_reg_read_ioctl()
Dintel_uncore.c1700 i915_mmio_reg_offset(reg))) in __unclaimed_reg_debug()
1714 i915_mmio_reg_offset(reg)); in __unclaimed_previous_reg_debug()
1791 u32 offset = i915_mmio_reg_offset(reg); \
1846 return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); in fwtable_reg_read_fw_domains()
1895 u32 offset = i915_mmio_reg_offset(reg); \
1934 return __fwtable_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); in fwtable_reg_write_fw_domains()
2004 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) + uncore->gsi_offset; in __fw_domain_init()
2005 d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack) + uncore->gsi_offset; in __fw_domain_init()
/drivers/gpu/drm/i915/display/
Dintel_dsb.c161 if (reg_val != i915_mmio_reg_offset(reg)) { in intel_dsb_indexed_reg_write()
173 i915_mmio_reg_offset(reg); in intel_dsb_indexed_reg_write()
226 i915_mmio_reg_offset(reg); in intel_dsb_reg_write()
/drivers/gpu/drm/i915/gt/uc/
Dintel_uc.c400 i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET), in uc_init_wopcm()
403 i915_mmio_reg_offset(GUC_WOPCM_SIZE), in uc_init_wopcm()
/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_client_blt.c163 *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base)); in prepare_blit()
205 *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); in prepare_blit()

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