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Searched refs:icl_port_dplls (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c3160 &crtc_state->icl_port_dplls[port_dpll_id]; in icl_set_active_port_dpll()
3202 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_combo_phy_dpll()
3234 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_combo_phy_dpll()
3292 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()
3296 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()
3303 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; in icl_compute_tc_phy_dplls()
3325 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
3329 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
3339 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; in icl_get_tc_phy_dplls()
3357 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
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Dintel_display_types.h1120 } icl_port_dplls[ICL_PORT_DPLL_COUNT]; member
Dintel_ddi.c3462 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; in intel_ddi_get_clock()
3532 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; in icl_ddi_tc_get_clock()
Dintel_display.c5192 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, in intel_crtc_prepare_cleared_state()
5193 sizeof(saved_state->icl_port_dplls)); in intel_crtc_prepare_cleared_state()