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Searched refs:ih_rb_base (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvega10_ih.c53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega10_ih_init_register_offset()
66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in vega10_ih_init_register_offset()
77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); in vega10_ih_init_register_offset()
217 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in vega10_ih_enable_ring()
Dvega20_ih.c56 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega20_ih_init_register_offset()
69 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in vega20_ih_init_register_offset()
80 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); in vega20_ih_init_register_offset()
221 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in vega20_ih_enable_ring()
Dnavi10_ih.c55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in navi10_ih_init_register_offset()
68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in navi10_ih_init_register_offset()
79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); in navi10_ih_init_register_offset()
272 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in navi10_ih_enable_ring()
Dih_v6_0.c54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_0_init_register_offset()
67 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1); in ih_v6_0_init_register_offset()
246 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in ih_v6_0_enable_ring()
Damdgpu_ih.h34 uint32_t ih_rb_base; member