| /drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | init.c | 42 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \
43 init->offset, init_exec(init) ? \
44 '0' + (init->nested - 1) : ' ', ##args); \
47 if (init->subdev->debug >= NV_DBG_TRACE) \
59 init_exec(struct nvbios_init *init) in init_exec() argument
61 return (init->execute == 1) || ((init->execute & 5) == 5); in init_exec()
65 init_exec_set(struct nvbios_init *init, bool exec) in init_exec_set() argument
67 if (exec) init->execute &= 0xfd; in init_exec_set()
68 else init->execute |= 0x02; in init_exec_set()
72 init_exec_inv(struct nvbios_init *init) in init_exec_inv() argument
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | base.c | 30 nvkm_devinit_mmio(struct nvkm_devinit *init, u32 addr) in nvkm_devinit_mmio() argument
32 if (init->func->mmio) in nvkm_devinit_mmio()
33 addr = init->func->mmio(init, addr); in nvkm_devinit_mmio()
38 nvkm_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 khz) in nvkm_devinit_pll_set() argument
40 return init->func->pll_set(init, type, khz); in nvkm_devinit_pll_set()
44 nvkm_devinit_meminit(struct nvkm_devinit *init) in nvkm_devinit_meminit() argument
46 if (init->func->meminit) in nvkm_devinit_meminit()
47 init->func->meminit(init); in nvkm_devinit_meminit()
51 nvkm_devinit_disable(struct nvkm_devinit *init) in nvkm_devinit_disable() argument
53 if (init && init->func->disable) in nvkm_devinit_disable()
[all …]
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| D | gm200.c | 32 pmu_code(struct nv50_devinit *init, u32 pmu, u32 img, u32 len, bool sec) in pmu_code() argument
34 struct nvkm_device *device = init->base.subdev.device; in pmu_code()
52 pmu_data(struct nv50_devinit *init, u32 pmu, u32 img, u32 len) in pmu_data() argument
54 struct nvkm_device *device = init->base.subdev.device; in pmu_data()
64 pmu_args(struct nv50_devinit *init, u32 argp, u32 argi) in pmu_args() argument
66 struct nvkm_device *device = init->base.subdev.device; in pmu_args()
73 pmu_exec(struct nv50_devinit *init, u32 init_addr) in pmu_exec() argument
75 struct nvkm_device *device = init->base.subdev.device; in pmu_exec()
82 pmu_load(struct nv50_devinit *init, u8 type, bool post, in pmu_load() argument
85 struct nvkm_subdev *subdev = &init->base.subdev; in pmu_load()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/therm/ |
| D | gf100.c | 28 #define pack_for_each_init(init, pack, head) \ argument
29 for (pack = head; pack && pack->init; pack++) \
30 for (init = pack->init; init && init->count; init++)
37 const struct nvkm_therm_clkgate_init *init; in gf100_clkgate_init() local
40 pack_for_each_init(init, pack, p) { in gf100_clkgate_init()
41 next = init->addr + init->count * 8; in gf100_clkgate_init()
42 addr = init->addr; in gf100_clkgate_init()
45 init->addr, init->count, init->data); in gf100_clkgate_init()
48 addr, init->data); in gf100_clkgate_init()
49 nvkm_wr32(device, addr, init->data); in gf100_clkgate_init()
|
| /drivers/clk/qcom/ |
| D | gcc-ipq8074.c | 401 .hw.init = &(struct clk_init_data){
415 .hw.init = &(struct clk_init_data){
429 .clkr.hw.init = &(struct clk_init_data){
445 .hw.init = &(struct clk_init_data){
461 .clkr.hw.init = &(struct clk_init_data){
477 .hw.init = &(struct clk_init_data){
493 .clkr.hw.init = &(struct clk_init_data){
510 .hw.init = &(struct clk_init_data){
526 .clkr.hw.init = &(struct clk_init_data){
539 .hw.init = &(struct clk_init_data){
[all …]
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| D | gcc-apq8084.c | 109 .clkr.hw.init = &(struct clk_init_data){
120 .hw.init = &(struct clk_init_data){
132 .clkr.hw.init = &(struct clk_init_data){
144 .clkr.hw.init = &(struct clk_init_data){
156 .clkr.hw.init = &(struct clk_init_data){
172 .clkr.hw.init = &(struct clk_init_data){
183 .hw.init = &(struct clk_init_data){
199 .clkr.hw.init = &(struct clk_init_data){
210 .hw.init = &(struct clk_init_data){
231 .clkr.hw.init = &(struct clk_init_data){
[all …]
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| D | gcc-sc8280xp.c | 117 .hw.init = &(const struct clk_init_data) {
138 .clkr.hw.init = &(const struct clk_init_data) {
154 .hw.init = &(const struct clk_init_data) {
169 .hw.init = &(const struct clk_init_data) {
184 .hw.init = &(const struct clk_init_data) {
199 .hw.init = &(const struct clk_init_data) {
214 .hw.init = &(const struct clk_init_data) {
452 .hw.init = &(const struct clk_init_data) {
467 .hw.init = &(const struct clk_init_data) {
556 .hw.init = &(const struct clk_init_data) {
[all …]
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| D | gcc-msm8998.c | 41 .hw.init = &(struct clk_init_data){
55 .clkr.hw.init = &(struct clk_init_data){
68 .clkr.hw.init = &(struct clk_init_data){
81 .clkr.hw.init = &(struct clk_init_data){
94 .clkr.hw.init = &(struct clk_init_data){
112 .hw.init = &(struct clk_init_data){
126 .clkr.hw.init = &(struct clk_init_data){
139 .clkr.hw.init = &(struct clk_init_data){
152 .clkr.hw.init = &(struct clk_init_data){
165 .clkr.hw.init = &(struct clk_init_data){
[all …]
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| D | mmcc-apq8084.c | 223 .clkr.hw.init = &(struct clk_init_data){
234 .hw.init = &(struct clk_init_data){
250 .clkr.hw.init = &(struct clk_init_data){
261 .hw.init = &(struct clk_init_data){
276 .clkr.hw.init = &(struct clk_init_data){
292 .clkr.hw.init = &(struct clk_init_data){
307 .clkr.hw.init = &(struct clk_init_data){
319 .clkr.hw.init = &(struct clk_init_data){
344 .clkr.hw.init = &(struct clk_init_data){
368 .clkr.hw.init = &(struct clk_init_data){
[all …]
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| D | gcc-msm8996.c | 39 .hw.init = &(struct clk_init_data){
55 .hw.init = &(struct clk_init_data){
69 .hw.init = &(struct clk_init_data){
82 .clkr.hw.init = &(struct clk_init_data){
97 .hw.init = &(struct clk_init_data){
114 .hw.init = &(struct clk_init_data){
132 .hw.init = &(struct clk_init_data){
146 .clkr.hw.init = &(struct clk_init_data){
261 .clkr.hw.init = &(struct clk_init_data){
279 .clkr.hw.init = &(struct clk_init_data){
[all …]
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| D | gcc-sm8250.c | 41 .hw.init = &(struct clk_init_data){
64 .clkr.hw.init = &(struct clk_init_data){
80 .hw.init = &(struct clk_init_data){
97 .hw.init = &(struct clk_init_data){
199 .clkr.hw.init = &(struct clk_init_data){
223 .clkr.hw.init = &(struct clk_init_data){
237 .clkr.hw.init = &(struct clk_init_data){
251 .clkr.hw.init = &(struct clk_init_data){
271 .clkr.hw.init = &(struct clk_init_data){
285 .clkr.hw.init = &(struct clk_init_data){
[all …]
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| D | gcc-qcs404.c | 280 .hw.init = &(struct clk_init_data){
295 .hw.init = &(struct clk_init_data){
311 .hw.init = &(struct clk_init_data){
328 .hw.init = &(struct clk_init_data){
344 .hw.init = &(struct clk_init_data){
375 .hw.init = &(struct clk_init_data){
390 .hw.init = &(struct clk_init_data){
407 .clkr.hw.init = &(struct clk_init_data){
418 .hw.init = &(struct clk_init_data){
440 .clkr.hw.init = &(struct clk_init_data){
[all …]
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| D | gcc-msm8976.c | 63 .clkr.hw.init = &(struct clk_init_data){
76 .hw.init = &(struct clk_init_data){
96 .clkr.hw.init = &(struct clk_init_data){
109 .hw.init = &(struct clk_init_data){
133 .clkr.hw.init = &(struct clk_init_data) {
146 .hw.init = &(struct clk_init_data){
180 .clkr.hw.init = &(struct clk_init_data){
193 .hw.init = &(struct clk_init_data){
211 .clkr.hw.init = &(struct clk_init_data){
224 .hw.init = &(struct clk_init_data){
[all …]
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| D | gcc-msm8974.c | 65 .clkr.hw.init = &(struct clk_init_data){
76 .hw.init = &(struct clk_init_data){
88 .clkr.hw.init = &(struct clk_init_data){
100 .clkr.hw.init = &(struct clk_init_data){
112 .clkr.hw.init = &(struct clk_init_data){
128 .clkr.hw.init = &(struct clk_init_data){
139 .hw.init = &(struct clk_init_data){
155 .clkr.hw.init = &(struct clk_init_data){
166 .hw.init = &(struct clk_init_data){
185 .clkr.hw.init = &(struct clk_init_data){
[all …]
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| D | gcc-sm8450.c | 44 .hw.init = &(struct clk_init_data){
67 .clkr.hw.init = &(struct clk_init_data){
83 .hw.init = &(struct clk_init_data){
100 .hw.init = &(struct clk_init_data){
224 .hw.init = &(struct clk_init_data){
241 .hw.init = &(struct clk_init_data){
253 .hw.init = &(struct clk_init_data){
270 .hw.init = &(struct clk_init_data){
285 .hw.init = &(struct clk_init_data){
300 .hw.init = &(struct clk_init_data){
[all …]
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| D | gcc-sc8180x.c | 55 .hw.init = &(struct clk_init_data){
81 .clkr.hw.init = &(struct clk_init_data){
97 .hw.init = &(struct clk_init_data){
116 .hw.init = &(struct clk_init_data){
135 .hw.init = &(struct clk_init_data){
277 .clkr.hw.init = &(struct clk_init_data){
300 .clkr.hw.init = &(struct clk_init_data){
326 .clkr.hw.init = &(struct clk_init_data){
350 .clkr.hw.init = &(struct clk_init_data){
365 .clkr.hw.init = &(struct clk_init_data){
[all …]
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| D | gcc-sm8150.c | 43 .hw.init = &(struct clk_init_data){
70 .clkr.hw.init = &(struct clk_init_data){
86 .hw.init = &(struct clk_init_data){
104 .hw.init = &(struct clk_init_data){
241 .clkr.hw.init = &(struct clk_init_data){
264 .clkr.hw.init = &(struct clk_init_data){
290 .clkr.hw.init = &(struct clk_init_data){
314 .clkr.hw.init = &(struct clk_init_data){
329 .clkr.hw.init = &(struct clk_init_data){
344 .clkr.hw.init = &(struct clk_init_data){
[all …]
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| D | gcc-mdm9607.c | 43 .hw.init = &(struct clk_init_data)
58 .clkr.hw.init = &(struct clk_init_data)
85 .clkr.hw.init = &(struct clk_init_data){
98 .hw.init = &(struct clk_init_data){
126 .hw.init = &(struct clk_init_data)
141 .clkr.hw.init = &(struct clk_init_data)
188 .clkr.hw.init = &(struct clk_init_data){
204 .clkr.hw.init = &(struct clk_init_data){
217 .hw.init = &(struct clk_init_data){
249 .clkr.hw.init = &(struct clk_init_data){
[all …]
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| D | gcc-msm8994.c | 39 .hw.init = &(struct clk_init_data){
53 .clkr.hw.init = &(struct clk_init_data){
69 .hw.init = &(struct clk_init_data){
84 .clkr.hw.init = &(struct clk_init_data){
132 .clkr.hw.init = &(struct clk_init_data){
152 .clkr.hw.init = &(struct clk_init_data){
171 .clkr.hw.init = &(struct clk_init_data){
209 .clkr.hw.init = &(struct clk_init_data){
222 .clkr.hw.init = &(struct clk_init_data){
249 .clkr.hw.init = &(struct clk_init_data){
[all …]
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| /drivers/clk/socfpga/ |
| D | clk-periph-s10.c | 106 struct clk_init_data init; in s10_register_periph() local
117 init.name = name; in s10_register_periph()
118 init.ops = &peri_c_clk_ops; in s10_register_periph()
119 init.flags = clks->flags; in s10_register_periph()
121 init.num_parents = clks->num_parents; in s10_register_periph()
122 init.parent_names = parent_name ? &parent_name : NULL; in s10_register_periph()
123 if (init.parent_names == NULL) in s10_register_periph()
124 init.parent_data = clks->parent_data; in s10_register_periph()
126 periph_clk->hw.hw.init = &init; in s10_register_periph()
142 struct clk_init_data init; in n5x_register_periph() local
[all …]
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| D | clk-pll-s10.c | 195 struct clk_init_data init; in s10_register_pll() local
206 init.ops = &clk_boot_ops; in s10_register_pll()
208 init.ops = &clk_pll_ops; in s10_register_pll()
210 init.name = name; in s10_register_pll()
211 init.flags = clks->flags; in s10_register_pll()
213 init.num_parents = clks->num_parents; in s10_register_pll()
214 init.parent_names = NULL; in s10_register_pll()
215 init.parent_data = clks->parent_data; in s10_register_pll()
216 pll_clk->hw.hw.init = &init; in s10_register_pll()
235 struct clk_init_data init; in agilex_register_pll() local
[all …]
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| /drivers/gpu/drm/r128/ |
| D | r128_ioc32.c | 67 drm_r128_init_t init; in compat_r128_init() local
72 init.func = init32.func; in compat_r128_init()
73 init.sarea_priv_offset = init32.sarea_priv_offset; in compat_r128_init()
74 init.is_pci = init32.is_pci; in compat_r128_init()
75 init.cce_mode = init32.cce_mode; in compat_r128_init()
76 init.cce_secure = init32.cce_secure; in compat_r128_init()
77 init.ring_size = init32.ring_size; in compat_r128_init()
78 init.usec_timeout = init32.usec_timeout; in compat_r128_init()
79 init.fb_bpp = init32.fb_bpp; in compat_r128_init()
80 init.front_offset = init32.front_offset; in compat_r128_init()
[all …]
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| /drivers/clk/ |
| D | clk-versaclock5.c | 944 struct clk_init_data init; in vc5_probe() local
997 memset(&init, 0, sizeof(init)); in vc5_probe()
1001 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); in vc5_probe()
1009 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); in vc5_probe()
1014 parent_names[init.num_parents++] = in vc5_probe()
1018 if (!init.num_parents) in vc5_probe()
1029 init.name = kasprintf(GFP_KERNEL, "%pOFn.mux", client->dev.of_node); in vc5_probe()
1030 if (!init.name) { in vc5_probe()
1035 init.ops = &vc5_mux_ops; in vc5_probe()
1036 init.flags = 0; in vc5_probe()
[all …]
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| /drivers/gpu/drm/i915/ |
| D | i915_module.c | 48 int (*init)(void); member
51 { .init = i915_check_nomodeset },
52 { .init = i915_active_module_init,
54 { .init = i915_context_module_init,
56 { .init = i915_gem_context_module_init,
58 { .init = i915_objects_module_init,
60 { .init = i915_request_module_init,
62 { .init = i915_scheduler_module_init,
64 { .init = i915_vma_module_init,
66 { .init = i915_vma_resource_module_init,
[all …]
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| /drivers/clk/stm32/ |
| D | clk-stm32mp13.c | 646 .hw.init = CLK_HW_INIT("tim2_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
651 .hw.init = CLK_HW_INIT("tim3_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
656 .hw.init = CLK_HW_INIT("tim4_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
661 .hw.init = CLK_HW_INIT("tim5_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
666 .hw.init = CLK_HW_INIT("tim6_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
671 .hw.init = CLK_HW_INIT("tim7_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
676 .hw.init = CLK_HW_INIT("tim1_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
681 .hw.init = CLK_HW_INIT("tim8_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
686 .hw.init = CLK_HW_INIT("tim12_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
691 .hw.init = CLK_HW_INIT("tim13_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
[all …]
|