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Searched refs:irq_ena (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/armada/
Darmada_crtc.c229 if (dcrtc->irq_ena & mask) { in armada_drm_crtc_disable_irq()
230 dcrtc->irq_ena &= ~mask; in armada_drm_crtc_disable_irq()
231 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_disable_irq()
237 if ((dcrtc->irq_ena & mask) != mask) { in armada_drm_crtc_enable_irq()
238 dcrtc->irq_ena |= mask; in armada_drm_crtc_enable_irq()
239 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_enable_irq()
273 if (stat & dcrtc->irq_ena & DUMB_FRAMEDONE) { in armada_drm_crtc_irq()
319 v = stat & dcrtc->irq_ena; in armada_drm_irq()
937 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; in armada_drm_crtc_create()
949 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_create()
Darmada_crtc.h63 uint32_t irq_ena; member
/drivers/clocksource/
Dtimer-ti-dm.c127 int irq_ena; /* irq enable */ member
217 timer->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET; in __omap_dm_timer_init_regs()
224 timer->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET - OMAP_TIMER_V2_FUNC_OFFSET; in __omap_dm_timer_init_regs()
285 dmtimer_write(timer, timer->irq_ena, value); in __omap_dm_timer_int_enable()
310 dmtimer_write(timer, timer->irq_ena, timer->context.tier); in omap_timer_restore_context()
322 timer->context.tier = dmtimer_read(timer, timer->irq_ena); in omap_timer_save_context()
962 l = dmtimer_read(timer, timer->irq_ena) & ~mask; in omap_dm_timer_set_int_disable()
Dtimer-ti-dm-systimer.c41 u8 irq_ena; member
399 t->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET; in dmtimer_systimer_setup()
404 t->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET; in dmtimer_systimer_setup()
531 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena); in omap_clockevent_unidle()
585 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena); in dmtimer_clkevt_init_common()