Home
last modified time | relevance | path

Searched refs:irq_mask (Results 1 – 25 of 465) sorted by relevance

12345678910>>...19

/drivers/gpio/
Dgpio-104-idi-48.c67 unsigned char irq_mask[6]; member
116 idi48gpio->irq_mask[boundary] &= ~mask; in idi_48_irq_mask()
120 if (idi48gpio->irq_mask[boundary]) in idi_48_irq_mask()
143 prev_irq_mask = idi48gpio->irq_mask[boundary]; in idi_48_irq_unmask()
146 idi48gpio->irq_mask[boundary] |= mask; in idi_48_irq_unmask()
173 .irq_mask = idi_48_irq_mask,
185 unsigned long irq_mask; in idi_48_irq_handler() local
204 irq_mask = idi48gpio->irq_mask[boundary]; in idi_48_irq_handler()
206 for_each_set_bit(bit_num, &irq_mask, 8) { in idi_48_irq_handler()
Dgpio-104-dio-48e.c80 unsigned char irq_mask; member
165 dio48egpio->irq_mask &= ~BIT(0); in dio48e_irq_mask()
167 dio48egpio->irq_mask &= ~BIT(1); in dio48e_irq_mask()
170 if (!dio48egpio->irq_mask) in dio48e_irq_mask()
190 if (!dio48egpio->irq_mask) { in dio48e_irq_unmask()
198 dio48egpio->irq_mask |= BIT(0); in dio48e_irq_unmask()
200 dio48egpio->irq_mask |= BIT(1); in dio48e_irq_unmask()
222 .irq_mask = dio48e_irq_mask,
233 const unsigned long irq_mask = dio48egpio->irq_mask; in dio48e_irq_handler() local
236 for_each_set_bit(gpio, &irq_mask, 2) in dio48e_irq_handler()
Dgpio-pcie-idio-24.c138 unsigned long irq_mask; member
384 idio24gpio->irq_mask &= ~BIT(bit_offset); in idio_24_irq_mask()
385 new_irq_mask = idio24gpio->irq_mask >> bank_offset * 8; in idio_24_irq_mask()
413 prev_irq_mask = idio24gpio->irq_mask >> bank_offset * 8; in idio_24_irq_unmask()
414 idio24gpio->irq_mask |= BIT(bit_offset); in idio_24_irq_unmask()
443 .irq_mask = idio_24_irq_mask,
453 unsigned long irq_mask; in idio_24_irq_handler() local
468 irq_mask = idio24gpio->irq_mask & irq_status; in idio_24_irq_handler()
470 for_each_set_bit(gpio, &irq_mask, chip->ngpio - 24) in idio_24_irq_handler()
Dgpio-104-idio-16.c71 unsigned long irq_mask; member
181 idio16gpio->irq_mask &= ~BIT(offset); in idio_16_irq_mask()
184 if (!idio16gpio->irq_mask) { in idio_16_irq_mask()
198 const unsigned long prev_irq_mask = idio16gpio->irq_mask; in idio_16_irq_unmask()
202 idio16gpio->irq_mask |= BIT(offset); in idio_16_irq_unmask()
226 .irq_mask = idio_16_irq_mask,
239 for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio) in idio_16_irq_handler()
Dgpio-pci-idio-16.c57 unsigned long irq_mask; member
197 idio16gpio->irq_mask &= ~mask; in idio_16_irq_mask()
199 if (!idio16gpio->irq_mask) { in idio_16_irq_mask()
213 const unsigned long prev_irq_mask = idio16gpio->irq_mask; in idio_16_irq_unmask()
216 idio16gpio->irq_mask |= mask; in idio_16_irq_unmask()
240 .irq_mask = idio_16_irq_mask,
262 for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio) in idio_16_irq_handler()
Dgpio-max732x.c150 uint8_t irq_mask; member
323 if (chip->irq_mask == chip->irq_mask_cur) in max732x_irq_update_mask()
326 chip->irq_mask = chip->irq_mask_cur; in max732x_irq_update_mask()
335 msg = (chip->irq_mask << 8) | chip->reg_out[0]; in max732x_irq_update_mask()
340 msg = chip->irq_mask | chip->reg_out[0]; in max732x_irq_update_mask()
370 chip->irq_mask_cur = chip->irq_mask; in max732x_irq_bus_lock()
434 .irq_mask = max732x_irq_mask,
456 trigger &= chip->irq_mask; in max732x_irq_pending()
462 cur_stat &= chip->irq_mask; in max732x_irq_pending()
Dgpio-ws16c48.c63 unsigned long irq_mask; member
237 port_state = ws16c48gpio->irq_mask >> (8*port); in ws16c48_irq_ack()
268 ws16c48gpio->irq_mask &= ~mask; in ws16c48_irq_mask()
270 port_state = ws16c48gpio->irq_mask >> (8 * port); in ws16c48_irq_mask()
301 ws16c48gpio->irq_mask |= mask; in ws16c48_irq_unmask()
302 port_state = ws16c48gpio->irq_mask >> (8 * port); in ws16c48_irq_unmask()
365 .irq_mask = ws16c48_irq_mask,
Dgpio-pxa.c67 unsigned long irq_mask; member
388 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; in update_edge_detect()
389 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; in update_edge_detect()
390 grer |= c->irq_edge_rise & c->irq_mask; in update_edge_detect()
391 gfer |= c->irq_edge_fall & c->irq_mask; in update_edge_detect()
452 gedr = gedr & c->irq_mask; in pxa_gpio_demux_handler()
500 b->irq_mask &= ~GPIO_bit(gpio); in pxa_mask_muxed_gpio()
525 c->irq_mask |= GPIO_bit(gpio); in pxa_unmask_muxed_gpio()
532 .irq_mask = pxa_mask_muxed_gpio,
/drivers/thermal/intel/
Dintel_bxt_pmic_thermal.c33 u8 irq_mask; member
53 .irq_mask = 0x01,
62 .irq_mask = 0x10,
74 .irq_mask = 0x02,
83 .irq_mask = 0x20,
95 .irq_mask = 0x04,
104 .irq_mask = 0x40,
116 .irq_mask = 0x10,
173 mask = td->maps[i].trip_config[j].irq_mask; in pmic_thermal_irq_handler()
/drivers/video/fbdev/omap2/omapfb/dss/
Ddispc-compat.c514 u32 irq_mask; in dispc_mgr_enable_digit_out() local
525 irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT) | in dispc_mgr_enable_digit_out()
529 irq_mask); in dispc_mgr_enable_digit_out()
531 DSSERR("failed to register %x isr\n", irq_mask); in dispc_mgr_enable_digit_out()
542 irq_mask); in dispc_mgr_enable_digit_out()
544 DSSERR("failed to unregister %x isr\n", irq_mask); in dispc_mgr_enable_digit_out()
551 u32 irq_mask; in dispc_mgr_disable_digit_out() local
562 irq_mask = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_DIGIT); in dispc_mgr_disable_digit_out()
565 if (!irq_mask) { in dispc_mgr_disable_digit_out()
571 irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT); in dispc_mgr_disable_digit_out()
[all …]
/drivers/gpu/drm/omapdrm/
Domap_irq.c23 u32 irqmask = priv->irq_mask; in omap_irq_update()
92 priv->irq_mask |= framedone_irq; in omap_irq_enable_framedone()
94 priv->irq_mask &= ~framedone_irq; in omap_irq_enable_framedone()
123 priv->irq_mask |= dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_enable_vblank()
149 priv->irq_mask &= ~dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_disable_vblank()
177 irqstatus &= priv->irq_mask & mask; in omap_irq_fifo_underflow()
267 priv->irq_mask = DISPC_IRQ_OCP_ERR; in omap_drm_irq_install()
273 priv->irq_mask |= omap_underflow_irqs[i]; in omap_drm_irq_install()
277 priv->irq_mask |= dispc_mgr_get_sync_lost_irq(priv->dispc, i); in omap_drm_irq_install()
/drivers/gpu/drm/i915/gt/
Dgen2_engine_cs.c297 i915->irq_mask &= ~engine->irq_enable_mask; in gen2_irq_enable()
298 intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); in gen2_irq_enable()
306 i915->irq_mask |= engine->irq_enable_mask; in gen2_irq_disable()
307 intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); in gen2_irq_disable()
312 engine->i915->irq_mask &= ~engine->irq_enable_mask; in gen3_irq_enable()
313 intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); in gen3_irq_enable()
319 engine->i915->irq_mask |= engine->irq_enable_mask; in gen3_irq_disable()
320 intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); in gen3_irq_disable()
/drivers/gpu/drm/tidss/
Dtidss_irq.c23 dispc_set_irqenable(tidss->dispc, tidss->irq_mask); in tidss_irq_update()
35 tidss->irq_mask |= DSS_IRQ_VP_VSYNC_EVEN(hw_videoport) | in tidss_irq_enable_vblank()
50 tidss->irq_mask &= ~(DSS_IRQ_VP_VSYNC_EVEN(hw_videoport) | in tidss_irq_disable_vblank()
120 tidss->irq_mask = DSS_IRQ_DEVICE_OCP_ERR; in tidss_irq_postinstall()
125 tidss->irq_mask |= DSS_IRQ_VP_SYNC_LOST(tcrtc->hw_videoport); in tidss_irq_postinstall()
127 tidss->irq_mask |= DSS_IRQ_VP_FRAME_DONE(tcrtc->hw_videoport); in tidss_irq_postinstall()
/drivers/i2c/busses/
Di2c-cht-wc.c50 u8 irq_mask; member
72 reg &= ~adap->irq_mask; in cht_wc_i2c_adap_thread_handler()
233 if (adap->irq_mask != adap->old_irq_mask) { in cht_wc_i2c_irq_sync_unlock()
235 adap->irq_mask); in cht_wc_i2c_irq_sync_unlock()
237 adap->old_irq_mask = adap->irq_mask; in cht_wc_i2c_irq_sync_unlock()
249 adap->irq_mask &= ~CHT_WC_EXTCHGRIRQ_CLIENT_IRQ; in cht_wc_i2c_irq_enable()
256 adap->irq_mask |= CHT_WC_EXTCHGRIRQ_CLIENT_IRQ; in cht_wc_i2c_irq_disable()
412 adap->old_irq_mask = adap->irq_mask = ~CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK; in cht_wc_i2c_adap_i2c_probe()
418 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, ~adap->irq_mask); in cht_wc_i2c_adap_i2c_probe()
422 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, adap->irq_mask); in cht_wc_i2c_adap_i2c_probe()
Di2c-nomadik.c447 u32 mcr, irq_mask; in read_i2c() local
463 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | in read_i2c()
467 irq_mask |= I2C_IT_MTD; in read_i2c()
469 irq_mask |= I2C_IT_MTDWS; in read_i2c()
471 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); in read_i2c()
473 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, in read_i2c()
516 u32 mcr, irq_mask; in write_i2c() local
533 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); in write_i2c()
539 irq_mask |= I2C_IT_TXFNE; in write_i2c()
547 irq_mask |= I2C_IT_MTD; in write_i2c()
[all …]
/drivers/irqchip/
Dexynos-combiner.c31 unsigned int irq_mask; member
78 status &= chip_data->irq_mask; in combiner_handle_cascade_irq()
109 .irq_mask = combiner_mask_irq,
129 combiner_data->irq_mask = 0xff << ((combiner_nr % 4) << 3); in combiner_init_one()
133 writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR); in combiner_init_one()
231 writel_relaxed(combiner_data[i].irq_mask, in combiner_resume()
Dirq-ingenic-tcu.c30 uint32_t irq_reg, irq_mask; in ingenic_tcu_intc_cascade() local
35 regmap_read(map, TCU_REG_TMR, &irq_mask); in ingenic_tcu_intc_cascade()
39 irq_reg &= ~irq_mask; in ingenic_tcu_intc_cascade()
142 ct->chip.irq_mask = ingenic_tcu_gc_mask_disable_reg; in ingenic_tcu_irq_init()
Dirq-bcm2836.c59 .irq_mask = bcm2836_arm_irqchip_mask_timer_irq,
75 .irq_mask = bcm2836_arm_irqchip_mask_pmu_irq,
89 .irq_mask = bcm2836_arm_irqchip_mask_gpu_irq,
196 .irq_mask = bcm2836_arm_irqchip_dummy_op,
/drivers/gpu/drm/arm/
Dmalidp_hw.c947 .irq_mask = MALIDP_DE_IRQ_UNDERRUN |
957 .irq_mask = MALIDP500_SE_IRQ_CONF_MODE |
966 .irq_mask = MALIDP500_DE_IRQ_CONF_VALID,
999 .irq_mask = MALIDP_DE_IRQ_UNDERRUN |
1007 .irq_mask = MALIDP550_SE_IRQ_EOW,
1014 .irq_mask = MALIDP550_DC_IRQ_CONF_VALID |
1047 .irq_mask = MALIDP_DE_IRQ_UNDERRUN |
1061 .irq_mask = MALIDP550_SE_IRQ_EOW,
1068 .irq_mask = MALIDP550_DC_IRQ_CONF_VALID |
1206 if (!(status & de->irq_mask)) in malidp_de_irq()
[all …]
/drivers/mfd/
Ducb1x00-core.c303 ucb->irq_mask); in ucb1x00_irq_update()
306 ucb->irq_mask); in ucb1x00_irq_update()
320 ucb->irq_mask &= ~mask; in ucb1x00_irq_mask()
331 ucb->irq_mask |= mask; in ucb1x00_irq_unmask()
351 if (ucb->irq_mask & mask) { in ucb1x00_irq_set_type()
353 ucb->irq_mask); in ucb1x00_irq_set_type()
355 ucb->irq_mask); in ucb1x00_irq_set_type()
384 .irq_mask = ucb1x00_irq_mask,
714 ucb->irq_mask); in ucb1x00_resume()
716 ucb->irq_mask); in ucb1x00_resume()
/drivers/clocksource/
Dtimer-mediatek-cpux.c51 const unsigned long *irq_mask = cpumask_bits(cpu_possible_mask); in mtk_cpux_set_irq() local
57 val |= *irq_mask; in mtk_cpux_set_irq()
59 val &= ~(*irq_mask); in mtk_cpux_set_irq()
/drivers/media/pci/solo6x10/
Dsolo6x10.h191 u32 irq_mask; member
291 dev->irq_mask |= mask; in solo_irq_on()
292 solo_reg_write(dev, SOLO_IRQ_MASK, dev->irq_mask); in solo_irq_on()
297 dev->irq_mask &= ~mask; in solo_irq_off()
298 solo_reg_write(dev, SOLO_IRQ_MASK, dev->irq_mask); in solo_irq_off()
/drivers/gpu/drm/vmwgfx/
Dvmwgfx_irq.c95 masked_status = status & READ_ONCE(dev_priv->irq_mask); in vmw_irq_handler()
248 dev_priv->irq_mask |= flag; in vmw_generic_waiter_add()
249 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_add()
259 dev_priv->irq_mask &= ~flag; in vmw_generic_waiter_remove()
260 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_remove()
/drivers/ata/
Dpata_cmd64x.c242 int irq_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; in cmd64x_sff_irq_check() local
249 return irq_stat & irq_mask; in cmd64x_sff_irq_check()
282 int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0; in cmd648_sff_irq_check() local
285 return mrdmode & irq_mask; in cmd648_sff_irq_check()
299 int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0; in cmd648_sff_irq_clear() local
307 outb(mrdmode | irq_mask, base + 1); in cmd648_sff_irq_clear()
/drivers/crypto/qat/qat_common/
Dadf_transport.c64 bank->irq_mask |= (1 << ring); in adf_enable_ring_irq()
67 bank->irq_mask); in adf_enable_ring_irq()
77 bank->irq_mask &= ~(1 << ring); in adf_disable_ring_irq()
80 bank->irq_mask); in adf_disable_ring_irq()
335 empty_rings = ~empty_rings & bank->irq_mask; in adf_ring_response_handler()
350 bank->irq_mask); in adf_response_handler()
391 u32 irq_mask = BIT(num_rings_per_bank) - 1; in adf_init_bank() local
449 csr_ops->write_csr_int_flag(csr_addr, bank_num, irq_mask); in adf_init_bank()

12345678910>>...19