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Searched refs:ixDIDT_SQ_CTRL0 (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu7_powertune.c142 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ…
143 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ…
144 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
145 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ…
146 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ…
147 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ…
148 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ…
149 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ…
284 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ…
285 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ…
[all …]
Dvega10_powertune.c211 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL…
212 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFF…
213 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTR…
214 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__D…
215 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_SQ_CTRL0__DID…
216 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_SQ_CTRL0__DI…
217 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_SQ_CT…
218 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_CTRL0…
219 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_SQ_CTRL0__DIDT_…
220 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_SQ_CTRL0__DI…
[all …]
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h2507 #define ixDIDT_SQ_CTRL0 0x0 macro
Dgfx_7_2_d.h2532 #define ixDIDT_SQ_CTRL0 0x0 macro
Dgfx_8_1_d.h2755 #define ixDIDT_SQ_CTRL0 0x0 macro
Dgfx_8_0_d.h2777 #define ixDIDT_SQ_CTRL0 0x0 macro
/drivers/gpu/drm/amd/pm/legacy-dpm/
Dkv_dpm.c466 data = RREG32_DIDT(ixDIDT_SQ_CTRL0); in kv_do_enable_didt()
471 WREG32_DIDT(ixDIDT_SQ_CTRL0, data); in kv_do_enable_didt()
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h7142 #define ixDIDT_SQ_CTRL0 … macro
Dgc_9_2_1_offset.h7389 #define ixDIDT_SQ_CTRL0 … macro
Dgc_9_4_2_offset.h30 #define ixDIDT_SQ_CTRL0 … macro
Dgc_9_1_offset.h7350 #define ixDIDT_SQ_CTRL0 … macro
Dgc_10_1_0_offset.h11205 #define ixDIDT_SQ_CTRL0 … macro
Dgc_10_3_0_offset.h13455 #define ixDIDT_SQ_CTRL0 … macro