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Searched refs:ixDIDT_TD_CTRL0 (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu7_powertune.c185 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD…
186 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD…
187 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD…
188 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD…
189 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD…
190 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD…
191 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD…
192 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__UNUSED_0_MASK, DIDT_TD…
327 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD…
328 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK, DIDT_TD…
[all …]
Dvega10_powertune.c223 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL…
224 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFF…
225 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTR…
226 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__D…
227 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TD_CTRL0__DID…
228 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TD_CTRL0__DI…
229 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TD_CT…
230 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_CTRL0…
231 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TD_CTRL0__DIDT_…
232 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TD_CTRL0__DI…
[all …]
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h2519 #define ixDIDT_TD_CTRL0 0x40 macro
Dgfx_7_2_d.h2544 #define ixDIDT_TD_CTRL0 0x40 macro
Dgfx_8_1_d.h2769 #define ixDIDT_TD_CTRL0 0x40 macro
Dgfx_8_0_d.h2791 #define ixDIDT_TD_CTRL0 0x40 macro
/drivers/gpu/drm/amd/pm/legacy-dpm/
Dkv_dpm.c484 data = RREG32_DIDT(ixDIDT_TD_CTRL0); in kv_do_enable_didt()
489 WREG32_DIDT(ixDIDT_TD_CTRL0, data); in kv_do_enable_didt()
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h7193 #define ixDIDT_TD_CTRL0 … macro
Dgc_9_2_1_offset.h7438 #define ixDIDT_TD_CTRL0 … macro
Dgc_9_4_2_offset.h87 #define ixDIDT_TD_CTRL0 … macro
Dgc_9_1_offset.h7400 #define ixDIDT_TD_CTRL0 … macro
Dgc_10_1_0_offset.h11271 #define ixDIDT_TD_CTRL0 … macro
Dgc_10_3_0_offset.h13521 #define ixDIDT_TD_CTRL0 … macro