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Searched refs:ixUVD_CGC_MEM_CTRL (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c603 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()
605 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v3_1_enable_mgcg()
612 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()
614 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v3_1_enable_mgcg()
Duvd_v4_2.c610 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
612 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v4_2_enable_mgcg()
619 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
621 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v4_2_enable_mgcg()
Duvd_v5_0.c769 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
771 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v5_0_enable_mgcg()
778 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
780 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v5_0_enable_mgcg()
Duvd_v6_0.c1429 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
1431 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v6_0_enable_mgcg()
1438 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
1440 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v6_0_enable_mgcg()
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h27 #define ixUVD_CGC_MEM_CTRL 0x00C0 macro
Duvd_4_2_d.h86 #define ixUVD_CGC_MEM_CTRL 0xc0 macro
Duvd_3_1_d.h88 #define ixUVD_CGC_MEM_CTRL 0xc0 macro
Duvd_5_0_d.h97 #define ixUVD_CGC_MEM_CTRL 0xc0 macro
Duvd_6_0_d.h113 #define ixUVD_CGC_MEM_CTRL 0xc0 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_4_0_0_offset.h1562 #define ixUVD_CGC_MEM_CTRL … macro
Dvcn_3_0_0_offset.h1509 #define ixUVD_CGC_MEM_CTRL … macro