1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Ingenic SoCs pinctrl driver
4 *
5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
6 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk>
7 * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
8 */
9
10 #include <linux/compiler.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/of.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinconf-generic.h>
21 #include <linux/platform_device.h>
22 #include <linux/property.h>
23 #include <linux/regmap.h>
24 #include <linux/seq_file.h>
25 #include <linux/slab.h>
26
27 #include "core.h"
28 #include "pinconf.h"
29 #include "pinmux.h"
30
31 #define GPIO_PIN 0x00
32 #define GPIO_MSK 0x20
33
34 #define JZ4730_GPIO_DATA 0x00
35 #define JZ4730_GPIO_GPDIR 0x04
36 #define JZ4730_GPIO_GPPUR 0x0c
37 #define JZ4730_GPIO_GPALR 0x10
38 #define JZ4730_GPIO_GPAUR 0x14
39 #define JZ4730_GPIO_GPIDLR 0x18
40 #define JZ4730_GPIO_GPIDUR 0x1c
41 #define JZ4730_GPIO_GPIER 0x20
42 #define JZ4730_GPIO_GPIMR 0x24
43 #define JZ4730_GPIO_GPFR 0x28
44
45 #define JZ4740_GPIO_DATA 0x10
46 #define JZ4740_GPIO_PULL_DIS 0x30
47 #define JZ4740_GPIO_FUNC 0x40
48 #define JZ4740_GPIO_SELECT 0x50
49 #define JZ4740_GPIO_DIR 0x60
50 #define JZ4740_GPIO_TRIG 0x70
51 #define JZ4740_GPIO_FLAG 0x80
52
53 #define JZ4770_GPIO_INT 0x10
54 #define JZ4770_GPIO_PAT1 0x30
55 #define JZ4770_GPIO_PAT0 0x40
56 #define JZ4770_GPIO_FLAG 0x50
57 #define JZ4770_GPIO_PEN 0x70
58
59 #define X1830_GPIO_PEL 0x110
60 #define X1830_GPIO_PEH 0x120
61 #define X1830_GPIO_SR 0x150
62 #define X1830_GPIO_SMT 0x160
63
64 #define X2000_GPIO_EDG 0x70
65 #define X2000_GPIO_PEPU 0x80
66 #define X2000_GPIO_PEPD 0x90
67 #define X2000_GPIO_SR 0xd0
68 #define X2000_GPIO_SMT 0xe0
69
70 #define REG_SET(x) ((x) + 0x4)
71 #define REG_CLEAR(x) ((x) + 0x8)
72
73 #define REG_PZ_BASE(x) ((x) * 7)
74 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0)
75
76 #define GPIO_PULL_DIS 0
77 #define GPIO_PULL_UP 1
78 #define GPIO_PULL_DOWN 2
79
80 #define PINS_PER_GPIO_CHIP 32
81 #define JZ4730_PINS_PER_PAIRED_REG 16
82
83 #define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \
84 { \
85 name, \
86 id##_pins, \
87 ARRAY_SIZE(id##_pins), \
88 funcs, \
89 }
90
91 #define INGENIC_PIN_GROUP(name, id, func) \
92 INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func))
93
94 enum jz_version {
95 ID_JZ4730,
96 ID_JZ4740,
97 ID_JZ4725B,
98 ID_JZ4750,
99 ID_JZ4755,
100 ID_JZ4760,
101 ID_JZ4770,
102 ID_JZ4775,
103 ID_JZ4780,
104 ID_X1000,
105 ID_X1500,
106 ID_X1830,
107 ID_X2000,
108 ID_X2100,
109 };
110
111 struct ingenic_chip_info {
112 unsigned int num_chips;
113 unsigned int reg_offset;
114 enum jz_version version;
115
116 const struct group_desc *groups;
117 unsigned int num_groups;
118
119 const struct function_desc *functions;
120 unsigned int num_functions;
121
122 const u32 *pull_ups, *pull_downs;
123
124 const struct regmap_access_table *access_table;
125 };
126
127 struct ingenic_pinctrl {
128 struct device *dev;
129 struct regmap *map;
130 struct pinctrl_dev *pctl;
131 struct pinctrl_pin_desc *pdesc;
132
133 const struct ingenic_chip_info *info;
134 };
135
136 struct ingenic_gpio_chip {
137 struct ingenic_pinctrl *jzpc;
138 struct gpio_chip gc;
139 unsigned int irq, reg_base;
140 };
141
142 static const unsigned long enabled_socs =
143 IS_ENABLED(CONFIG_MACH_JZ4730) << ID_JZ4730 |
144 IS_ENABLED(CONFIG_MACH_JZ4740) << ID_JZ4740 |
145 IS_ENABLED(CONFIG_MACH_JZ4725B) << ID_JZ4725B |
146 IS_ENABLED(CONFIG_MACH_JZ4750) << ID_JZ4750 |
147 IS_ENABLED(CONFIG_MACH_JZ4755) << ID_JZ4755 |
148 IS_ENABLED(CONFIG_MACH_JZ4760) << ID_JZ4760 |
149 IS_ENABLED(CONFIG_MACH_JZ4770) << ID_JZ4770 |
150 IS_ENABLED(CONFIG_MACH_JZ4775) << ID_JZ4775 |
151 IS_ENABLED(CONFIG_MACH_JZ4780) << ID_JZ4780 |
152 IS_ENABLED(CONFIG_MACH_X1000) << ID_X1000 |
153 IS_ENABLED(CONFIG_MACH_X1500) << ID_X1500 |
154 IS_ENABLED(CONFIG_MACH_X1830) << ID_X1830 |
155 IS_ENABLED(CONFIG_MACH_X2000) << ID_X2000 |
156 IS_ENABLED(CONFIG_MACH_X2100) << ID_X2100;
157
158 static bool
is_soc_or_above(const struct ingenic_pinctrl * jzpc,enum jz_version version)159 is_soc_or_above(const struct ingenic_pinctrl *jzpc, enum jz_version version)
160 {
161 return (enabled_socs >> version) &&
162 (!(enabled_socs & GENMASK(version - 1, 0))
163 || jzpc->info->version >= version);
164 }
165
166 static const u32 jz4730_pull_ups[4] = {
167 0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff,
168 };
169
170 static const u32 jz4730_pull_downs[4] = {
171 0x00000df0, 0x0dff0000, 0x00000000, 0x00000000,
172 };
173
174 static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, };
175 static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, };
176 static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, };
177 static int jz4730_uart1_data_pins[] = { 0x18, 0x19, };
178 static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, };
179 static int jz4730_uart3_data_pins[] = { 0x10, 0x15, };
180 static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, };
181 static int jz4730_lcd_8bit_pins[] = {
182 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
183 0x3a, 0x39, 0x38,
184 };
185 static int jz4730_lcd_16bit_pins[] = {
186 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
187 };
188 static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, };
189 static int jz4730_lcd_generic_pins[] = { 0x3b, };
190 static int jz4730_nand_cs1_pins[] = { 0x53, };
191 static int jz4730_nand_cs2_pins[] = { 0x54, };
192 static int jz4730_nand_cs3_pins[] = { 0x55, };
193 static int jz4730_nand_cs4_pins[] = { 0x56, };
194 static int jz4730_nand_cs5_pins[] = { 0x57, };
195 static int jz4730_pwm_pwm0_pins[] = { 0x5e, };
196 static int jz4730_pwm_pwm1_pins[] = { 0x5f, };
197
198 static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, };
199
200 static const struct group_desc jz4730_groups[] = {
201 INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
202 INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),
203 INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),
204 INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),
205 INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),
206 INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),
207 INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1),
208 INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs),
209 INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1),
210 INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1),
211 INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1),
212 INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1),
213 INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1),
214 INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1),
215 INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1),
216 INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1),
217 INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1),
218 INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1),
219 };
220
221 static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
222 static const char *jz4730_uart0_groups[] = { "uart0-data", };
223 static const char *jz4730_uart1_groups[] = { "uart1-data", };
224 static const char *jz4730_uart2_groups[] = { "uart2-data", };
225 static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
226 static const char *jz4730_lcd_groups[] = {
227 "lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic",
228 };
229 static const char *jz4730_nand_groups[] = {
230 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5",
231 };
232 static const char *jz4730_pwm0_groups[] = { "pwm0", };
233 static const char *jz4730_pwm1_groups[] = { "pwm1", };
234
235 static const struct function_desc jz4730_functions[] = {
236 { "mmc", jz4730_mmc_groups, ARRAY_SIZE(jz4730_mmc_groups), },
237 { "uart0", jz4730_uart0_groups, ARRAY_SIZE(jz4730_uart0_groups), },
238 { "uart1", jz4730_uart1_groups, ARRAY_SIZE(jz4730_uart1_groups), },
239 { "uart2", jz4730_uart2_groups, ARRAY_SIZE(jz4730_uart2_groups), },
240 { "uart3", jz4730_uart3_groups, ARRAY_SIZE(jz4730_uart3_groups), },
241 { "lcd", jz4730_lcd_groups, ARRAY_SIZE(jz4730_lcd_groups), },
242 { "nand", jz4730_nand_groups, ARRAY_SIZE(jz4730_nand_groups), },
243 { "pwm0", jz4730_pwm0_groups, ARRAY_SIZE(jz4730_pwm0_groups), },
244 { "pwm1", jz4730_pwm1_groups, ARRAY_SIZE(jz4730_pwm1_groups), },
245 };
246
247 static const struct ingenic_chip_info jz4730_chip_info = {
248 .num_chips = 4,
249 .reg_offset = 0x30,
250 .version = ID_JZ4730,
251 .groups = jz4730_groups,
252 .num_groups = ARRAY_SIZE(jz4730_groups),
253 .functions = jz4730_functions,
254 .num_functions = ARRAY_SIZE(jz4730_functions),
255 .pull_ups = jz4730_pull_ups,
256 .pull_downs = jz4730_pull_downs,
257 };
258
259 static const u32 jz4740_pull_ups[4] = {
260 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
261 };
262
263 static const u32 jz4740_pull_downs[4] = {
264 0x00000000, 0x00000000, 0x00000000, 0x00000000,
265 };
266
267 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
268 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
269 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
270 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
271 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
272 static int jz4740_lcd_8bit_pins[] = {
273 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
274 0x52, 0x53, 0x54,
275 };
276 static int jz4740_lcd_16bit_pins[] = {
277 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
278 };
279 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
280 static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, };
281 static int jz4740_lcd_generic_pins[] = { 0x55, };
282 static int jz4740_nand_cs1_pins[] = { 0x39, };
283 static int jz4740_nand_cs2_pins[] = { 0x3a, };
284 static int jz4740_nand_cs3_pins[] = { 0x3b, };
285 static int jz4740_nand_cs4_pins[] = { 0x3c, };
286 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
287 static int jz4740_pwm_pwm0_pins[] = { 0x77, };
288 static int jz4740_pwm_pwm1_pins[] = { 0x78, };
289 static int jz4740_pwm_pwm2_pins[] = { 0x79, };
290 static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
291 static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
292 static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
293 static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
294 static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
295
296 static const struct group_desc jz4740_groups[] = {
297 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
298 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
299 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),
300 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),
301 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),
302 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
303 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
304 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
305 INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0),
306 INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0),
307 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
308 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
309 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
310 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),
311 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),
312 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0),
313 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0),
314 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0),
315 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0),
316 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0),
317 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0),
318 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0),
319 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0),
320 };
321
322 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
323 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
324 static const char *jz4740_uart1_groups[] = { "uart1-data", };
325 static const char *jz4740_lcd_groups[] = {
326 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic",
327 };
328 static const char *jz4740_nand_groups[] = {
329 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
330 };
331 static const char *jz4740_pwm0_groups[] = { "pwm0", };
332 static const char *jz4740_pwm1_groups[] = { "pwm1", };
333 static const char *jz4740_pwm2_groups[] = { "pwm2", };
334 static const char *jz4740_pwm3_groups[] = { "pwm3", };
335 static const char *jz4740_pwm4_groups[] = { "pwm4", };
336 static const char *jz4740_pwm5_groups[] = { "pwm5", };
337 static const char *jz4740_pwm6_groups[] = { "pwm6", };
338 static const char *jz4740_pwm7_groups[] = { "pwm7", };
339
340 static const struct function_desc jz4740_functions[] = {
341 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
342 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
343 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
344 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
345 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
346 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
347 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
348 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
349 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
350 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
351 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
352 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
353 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
354 };
355
356 static const struct ingenic_chip_info jz4740_chip_info = {
357 .num_chips = 4,
358 .reg_offset = 0x100,
359 .version = ID_JZ4740,
360 .groups = jz4740_groups,
361 .num_groups = ARRAY_SIZE(jz4740_groups),
362 .functions = jz4740_functions,
363 .num_functions = ARRAY_SIZE(jz4740_functions),
364 .pull_ups = jz4740_pull_ups,
365 .pull_downs = jz4740_pull_downs,
366 };
367
368 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
369 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
370 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
371 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
372 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
373 static int jz4725b_lcd_8bit_pins[] = {
374 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
375 0x72, 0x73, 0x74,
376 };
377 static int jz4725b_lcd_16bit_pins[] = {
378 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
379 };
380 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
381 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
382 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
383 static int jz4725b_lcd_generic_pins[] = { 0x75, };
384 static int jz4725b_nand_cs1_pins[] = { 0x55, };
385 static int jz4725b_nand_cs2_pins[] = { 0x56, };
386 static int jz4725b_nand_cs3_pins[] = { 0x57, };
387 static int jz4725b_nand_cs4_pins[] = { 0x58, };
388 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
389 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
390 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
391 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
392 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
393 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
394 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
395 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
396
397 static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
398
399 static const struct group_desc jz4725b_groups[] = {
400 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),
401 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,
402 jz4725b_mmc0_4bit_funcs),
403 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),
404 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),
405 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),
406 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),
407 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),
408 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),
409 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),
410 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),
411 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),
412 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),
413 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),
414 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),
415 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),
416 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),
417 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),
418 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0),
419 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0),
420 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0),
421 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0),
422 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0),
423 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0),
424 };
425
426 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
427 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
428 static const char *jz4725b_uart_groups[] = { "uart-data", };
429 static const char *jz4725b_lcd_groups[] = {
430 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
431 "lcd-special", "lcd-generic",
432 };
433 static const char *jz4725b_nand_groups[] = {
434 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
435 "nand-cle-ale", "nand-fre-fwe",
436 };
437 static const char *jz4725b_pwm0_groups[] = { "pwm0", };
438 static const char *jz4725b_pwm1_groups[] = { "pwm1", };
439 static const char *jz4725b_pwm2_groups[] = { "pwm2", };
440 static const char *jz4725b_pwm3_groups[] = { "pwm3", };
441 static const char *jz4725b_pwm4_groups[] = { "pwm4", };
442 static const char *jz4725b_pwm5_groups[] = { "pwm5", };
443
444 static const struct function_desc jz4725b_functions[] = {
445 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
446 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
447 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
448 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
449 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
450 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
451 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
452 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
453 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
454 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
455 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
456 };
457
458 static const struct ingenic_chip_info jz4725b_chip_info = {
459 .num_chips = 4,
460 .reg_offset = 0x100,
461 .version = ID_JZ4725B,
462 .groups = jz4725b_groups,
463 .num_groups = ARRAY_SIZE(jz4725b_groups),
464 .functions = jz4725b_functions,
465 .num_functions = ARRAY_SIZE(jz4725b_functions),
466 .pull_ups = jz4740_pull_ups,
467 .pull_downs = jz4740_pull_downs,
468 };
469
470 static const u32 jz4750_pull_ups[6] = {
471 0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff,
472 };
473
474 static const u32 jz4750_pull_downs[6] = {
475 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
476 };
477
478 static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, };
479 static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, };
480 static int jz4750_uart1_data_pins[] = { 0x90, 0x91, };
481 static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, };
482 static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, };
483 static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, };
484 static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, };
485 static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, };
486 static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, };
487 static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, };
488 static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, };
489 static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, };
490 static int jz4750_i2c_pins[] = { 0x8c, 0x8d, };
491 static int jz4750_cim_pins[] = {
492 0x89, 0x8b, 0x8a, 0x88,
493 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
494 };
495 static int jz4750_lcd_8bit_pins[] = {
496 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
497 0x72, 0x73, 0x74,
498 };
499 static int jz4750_lcd_16bit_pins[] = {
500 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
501 };
502 static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, };
503 static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, };
504 static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
505 static int jz4750_lcd_generic_pins[] = { 0x75, };
506 static int jz4750_nand_cs1_pins[] = { 0x55, };
507 static int jz4750_nand_cs2_pins[] = { 0x56, };
508 static int jz4750_nand_cs3_pins[] = { 0x57, };
509 static int jz4750_nand_cs4_pins[] = { 0x58, };
510 static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
511 static int jz4750_pwm_pwm0_pins[] = { 0x94, };
512 static int jz4750_pwm_pwm1_pins[] = { 0x95, };
513 static int jz4750_pwm_pwm2_pins[] = { 0x96, };
514 static int jz4750_pwm_pwm3_pins[] = { 0x97, };
515 static int jz4750_pwm_pwm4_pins[] = { 0x98, };
516 static int jz4750_pwm_pwm5_pins[] = { 0x99, };
517
518 static const struct group_desc jz4750_groups[] = {
519 INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
520 INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
521 INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
522 INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
523 INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
524 INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
525 INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
526 INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
527 INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
528 INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
529 INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
530 INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
531 INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
532 INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
533 INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
534 INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
535 INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
536 INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1),
537 INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0),
538 INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0),
539 INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
540 INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
541 INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
542 INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
543 INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
544 INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0),
545 INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0),
546 INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0),
547 INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0),
548 INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0),
549 INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0),
550 };
551
552 static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
553 static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
554 static const char *jz4750_uart2_groups[] = { "uart2-data", };
555 static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
556 static const char *jz4750_mmc0_groups[] = {
557 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
558 };
559 static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
560 static const char *jz4750_i2c_groups[] = { "i2c-data", };
561 static const char *jz4750_cim_groups[] = { "cim-data", };
562 static const char *jz4750_lcd_groups[] = {
563 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
564 "lcd-special", "lcd-generic",
565 };
566 static const char *jz4750_nand_groups[] = {
567 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
568 };
569 static const char *jz4750_pwm0_groups[] = { "pwm0", };
570 static const char *jz4750_pwm1_groups[] = { "pwm1", };
571 static const char *jz4750_pwm2_groups[] = { "pwm2", };
572 static const char *jz4750_pwm3_groups[] = { "pwm3", };
573 static const char *jz4750_pwm4_groups[] = { "pwm4", };
574 static const char *jz4750_pwm5_groups[] = { "pwm5", };
575
576 static const struct function_desc jz4750_functions[] = {
577 { "uart0", jz4750_uart0_groups, ARRAY_SIZE(jz4750_uart0_groups), },
578 { "uart1", jz4750_uart1_groups, ARRAY_SIZE(jz4750_uart1_groups), },
579 { "uart2", jz4750_uart2_groups, ARRAY_SIZE(jz4750_uart2_groups), },
580 { "uart3", jz4750_uart3_groups, ARRAY_SIZE(jz4750_uart3_groups), },
581 { "mmc0", jz4750_mmc0_groups, ARRAY_SIZE(jz4750_mmc0_groups), },
582 { "mmc1", jz4750_mmc1_groups, ARRAY_SIZE(jz4750_mmc1_groups), },
583 { "i2c", jz4750_i2c_groups, ARRAY_SIZE(jz4750_i2c_groups), },
584 { "cim", jz4750_cim_groups, ARRAY_SIZE(jz4750_cim_groups), },
585 { "lcd", jz4750_lcd_groups, ARRAY_SIZE(jz4750_lcd_groups), },
586 { "nand", jz4750_nand_groups, ARRAY_SIZE(jz4750_nand_groups), },
587 { "pwm0", jz4750_pwm0_groups, ARRAY_SIZE(jz4750_pwm0_groups), },
588 { "pwm1", jz4750_pwm1_groups, ARRAY_SIZE(jz4750_pwm1_groups), },
589 { "pwm2", jz4750_pwm2_groups, ARRAY_SIZE(jz4750_pwm2_groups), },
590 { "pwm3", jz4750_pwm3_groups, ARRAY_SIZE(jz4750_pwm3_groups), },
591 { "pwm4", jz4750_pwm4_groups, ARRAY_SIZE(jz4750_pwm4_groups), },
592 { "pwm5", jz4750_pwm5_groups, ARRAY_SIZE(jz4750_pwm5_groups), },
593 };
594
595 static const struct ingenic_chip_info jz4750_chip_info = {
596 .num_chips = 6,
597 .reg_offset = 0x100,
598 .version = ID_JZ4750,
599 .groups = jz4750_groups,
600 .num_groups = ARRAY_SIZE(jz4750_groups),
601 .functions = jz4750_functions,
602 .num_functions = ARRAY_SIZE(jz4750_functions),
603 .pull_ups = jz4750_pull_ups,
604 .pull_downs = jz4750_pull_downs,
605 };
606
607 static const u32 jz4755_pull_ups[6] = {
608 0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00,
609 };
610
611 static const u32 jz4755_pull_downs[6] = {
612 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
613 };
614
615 static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, };
616 static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
617 static int jz4755_uart1_data_pins[] = { 0x97, 0x99, };
618 static int jz4755_uart2_data_pins[] = { 0x9f, };
619 static int jz4755_ssi_dt_b_pins[] = { 0x3b, };
620 static int jz4755_ssi_dt_f_pins[] = { 0xa1, };
621 static int jz4755_ssi_dr_b_pins[] = { 0x3c, };
622 static int jz4755_ssi_dr_f_pins[] = { 0xa2, };
623 static int jz4755_ssi_clk_b_pins[] = { 0x3a, };
624 static int jz4755_ssi_clk_f_pins[] = { 0xa0, };
625 static int jz4755_ssi_gpc_b_pins[] = { 0x3e, };
626 static int jz4755_ssi_gpc_f_pins[] = { 0xa4, };
627 static int jz4755_ssi_ce0_b_pins[] = { 0x3d, };
628 static int jz4755_ssi_ce0_f_pins[] = { 0xa3, };
629 static int jz4755_ssi_ce1_b_pins[] = { 0x3f, };
630 static int jz4755_ssi_ce1_f_pins[] = { 0xa5, };
631 static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, };
632 static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, };
633 static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, };
634 static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, };
635 static int jz4755_i2c_pins[] = { 0x8c, 0x8d, };
636 static int jz4755_cim_pins[] = {
637 0x89, 0x8b, 0x8a, 0x88,
638 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
639 };
640 static int jz4755_lcd_8bit_pins[] = {
641 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
642 0x72, 0x73, 0x74,
643 };
644 static int jz4755_lcd_16bit_pins[] = {
645 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
646 };
647 static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, };
648 static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, };
649 static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
650 static int jz4755_lcd_generic_pins[] = { 0x75, };
651 static int jz4755_nand_cs1_pins[] = { 0x55, };
652 static int jz4755_nand_cs2_pins[] = { 0x56, };
653 static int jz4755_nand_cs3_pins[] = { 0x57, };
654 static int jz4755_nand_cs4_pins[] = { 0x58, };
655 static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
656 static int jz4755_pwm_pwm0_pins[] = { 0x94, };
657 static int jz4755_pwm_pwm1_pins[] = { 0xab, };
658 static int jz4755_pwm_pwm2_pins[] = { 0x96, };
659 static int jz4755_pwm_pwm3_pins[] = { 0x97, };
660 static int jz4755_pwm_pwm4_pins[] = { 0x98, };
661 static int jz4755_pwm_pwm5_pins[] = { 0x99, };
662
663 static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, };
664 static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, };
665 static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, };
666
667 static const struct group_desc jz4755_groups[] = {
668 INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
669 INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
670 INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1),
671 INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
672 INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),
673 INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),
674 INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0),
675 INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0),
676 INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0),
677 INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0),
678 INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0),
679 INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0),
680 INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),
681 INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),
682 INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0),
683 INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0),
684 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
685 jz4755_mmc0_1bit_funcs),
686 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
687 jz4755_mmc0_4bit_funcs),
688 INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
689 INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
690 INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
691 INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
692 INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0),
693 INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0),
694 INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0),
695 INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
696 jz4755_lcd_24bit_funcs),
697 INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0),
698 INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0),
699 INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
700 INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
701 INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
702 INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),
703 INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),
704 INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0),
705 INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1),
706 INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0),
707 INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0),
708 INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0),
709 INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0),
710 };
711
712 static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
713 static const char *jz4755_uart1_groups[] = { "uart1-data", };
714 static const char *jz4755_uart2_groups[] = { "uart2-data", };
715 static const char *jz4755_ssi_groups[] = {
716 "ssi-dt-b", "ssi-dt-f",
717 "ssi-dr-b", "ssi-dr-f",
718 "ssi-clk-b", "ssi-clk-f",
719 "ssi-gpc-b", "ssi-gpc-f",
720 "ssi-ce0-b", "ssi-ce0-f",
721 "ssi-ce1-b", "ssi-ce1-f",
722 };
723 static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
724 static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
725 static const char *jz4755_i2c_groups[] = { "i2c-data", };
726 static const char *jz4755_cim_groups[] = { "cim-data", };
727 static const char *jz4755_lcd_groups[] = {
728 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
729 "lcd-special", "lcd-generic",
730 };
731 static const char *jz4755_nand_groups[] = {
732 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
733 };
734 static const char *jz4755_pwm0_groups[] = { "pwm0", };
735 static const char *jz4755_pwm1_groups[] = { "pwm1", };
736 static const char *jz4755_pwm2_groups[] = { "pwm2", };
737 static const char *jz4755_pwm3_groups[] = { "pwm3", };
738 static const char *jz4755_pwm4_groups[] = { "pwm4", };
739 static const char *jz4755_pwm5_groups[] = { "pwm5", };
740
741 static const struct function_desc jz4755_functions[] = {
742 { "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), },
743 { "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), },
744 { "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), },
745 { "ssi", jz4755_ssi_groups, ARRAY_SIZE(jz4755_ssi_groups), },
746 { "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), },
747 { "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), },
748 { "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), },
749 { "cim", jz4755_cim_groups, ARRAY_SIZE(jz4755_cim_groups), },
750 { "lcd", jz4755_lcd_groups, ARRAY_SIZE(jz4755_lcd_groups), },
751 { "nand", jz4755_nand_groups, ARRAY_SIZE(jz4755_nand_groups), },
752 { "pwm0", jz4755_pwm0_groups, ARRAY_SIZE(jz4755_pwm0_groups), },
753 { "pwm1", jz4755_pwm1_groups, ARRAY_SIZE(jz4755_pwm1_groups), },
754 { "pwm2", jz4755_pwm2_groups, ARRAY_SIZE(jz4755_pwm2_groups), },
755 { "pwm3", jz4755_pwm3_groups, ARRAY_SIZE(jz4755_pwm3_groups), },
756 { "pwm4", jz4755_pwm4_groups, ARRAY_SIZE(jz4755_pwm4_groups), },
757 { "pwm5", jz4755_pwm5_groups, ARRAY_SIZE(jz4755_pwm5_groups), },
758 };
759
760 static const struct ingenic_chip_info jz4755_chip_info = {
761 .num_chips = 6,
762 .reg_offset = 0x100,
763 .version = ID_JZ4755,
764 .groups = jz4755_groups,
765 .num_groups = ARRAY_SIZE(jz4755_groups),
766 .functions = jz4755_functions,
767 .num_functions = ARRAY_SIZE(jz4755_functions),
768 .pull_ups = jz4755_pull_ups,
769 .pull_downs = jz4755_pull_downs,
770 };
771
772 static const u32 jz4760_pull_ups[6] = {
773 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f,
774 };
775
776 static const u32 jz4760_pull_downs[6] = {
777 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
778 };
779
780 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
781 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
782 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
783 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
784 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
785 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
786 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
787 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
788 static int jz4760_ssi0_dt_a_pins[] = { 0x15, };
789 static int jz4760_ssi0_dt_b_pins[] = { 0x35, };
790 static int jz4760_ssi0_dt_d_pins[] = { 0x75, };
791 static int jz4760_ssi0_dt_e_pins[] = { 0x91, };
792 static int jz4760_ssi0_dr_a_pins[] = { 0x14, };
793 static int jz4760_ssi0_dr_b_pins[] = { 0x34, };
794 static int jz4760_ssi0_dr_d_pins[] = { 0x74, };
795 static int jz4760_ssi0_dr_e_pins[] = { 0x8e, };
796 static int jz4760_ssi0_clk_a_pins[] = { 0x12, };
797 static int jz4760_ssi0_clk_b_pins[] = { 0x3c, };
798 static int jz4760_ssi0_clk_d_pins[] = { 0x78, };
799 static int jz4760_ssi0_clk_e_pins[] = { 0x8f, };
800 static int jz4760_ssi0_gpc_b_pins[] = { 0x3e, };
801 static int jz4760_ssi0_gpc_d_pins[] = { 0x76, };
802 static int jz4760_ssi0_gpc_e_pins[] = { 0x93, };
803 static int jz4760_ssi0_ce0_a_pins[] = { 0x13, };
804 static int jz4760_ssi0_ce0_b_pins[] = { 0x3d, };
805 static int jz4760_ssi0_ce0_d_pins[] = { 0x79, };
806 static int jz4760_ssi0_ce0_e_pins[] = { 0x90, };
807 static int jz4760_ssi0_ce1_b_pins[] = { 0x3f, };
808 static int jz4760_ssi0_ce1_d_pins[] = { 0x77, };
809 static int jz4760_ssi0_ce1_e_pins[] = { 0x92, };
810 static int jz4760_ssi1_dt_b_9_pins[] = { 0x29, };
811 static int jz4760_ssi1_dt_b_21_pins[] = { 0x35, };
812 static int jz4760_ssi1_dt_d_12_pins[] = { 0x6c, };
813 static int jz4760_ssi1_dt_d_21_pins[] = { 0x75, };
814 static int jz4760_ssi1_dt_e_pins[] = { 0x91, };
815 static int jz4760_ssi1_dt_f_pins[] = { 0xa3, };
816 static int jz4760_ssi1_dr_b_6_pins[] = { 0x26, };
817 static int jz4760_ssi1_dr_b_20_pins[] = { 0x34, };
818 static int jz4760_ssi1_dr_d_13_pins[] = { 0x6d, };
819 static int jz4760_ssi1_dr_d_20_pins[] = { 0x74, };
820 static int jz4760_ssi1_dr_e_pins[] = { 0x8e, };
821 static int jz4760_ssi1_dr_f_pins[] = { 0xa0, };
822 static int jz4760_ssi1_clk_b_7_pins[] = { 0x27, };
823 static int jz4760_ssi1_clk_b_28_pins[] = { 0x3c, };
824 static int jz4760_ssi1_clk_d_pins[] = { 0x78, };
825 static int jz4760_ssi1_clk_e_7_pins[] = { 0x87, };
826 static int jz4760_ssi1_clk_e_15_pins[] = { 0x8f, };
827 static int jz4760_ssi1_clk_f_pins[] = { 0xa2, };
828 static int jz4760_ssi1_gpc_b_pins[] = { 0x3e, };
829 static int jz4760_ssi1_gpc_d_pins[] = { 0x76, };
830 static int jz4760_ssi1_gpc_e_pins[] = { 0x93, };
831 static int jz4760_ssi1_ce0_b_8_pins[] = { 0x28, };
832 static int jz4760_ssi1_ce0_b_29_pins[] = { 0x3d, };
833 static int jz4760_ssi1_ce0_d_pins[] = { 0x79, };
834 static int jz4760_ssi1_ce0_e_6_pins[] = { 0x86, };
835 static int jz4760_ssi1_ce0_e_16_pins[] = { 0x90, };
836 static int jz4760_ssi1_ce0_f_pins[] = { 0xa1, };
837 static int jz4760_ssi1_ce1_b_pins[] = { 0x3f, };
838 static int jz4760_ssi1_ce1_d_pins[] = { 0x77, };
839 static int jz4760_ssi1_ce1_e_pins[] = { 0x92, };
840 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
841 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
842 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
843 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
844 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
845 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
846 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
847 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
848 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
849 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
850 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
851 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
852 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
853 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
854 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
855 static int jz4760_nemc_8bit_data_pins[] = {
856 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
857 };
858 static int jz4760_nemc_16bit_data_pins[] = {
859 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
860 };
861 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
862 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
863 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
864 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
865 static int jz4760_nemc_wait_pins[] = { 0x1b, };
866 static int jz4760_nemc_cs1_pins[] = { 0x15, };
867 static int jz4760_nemc_cs2_pins[] = { 0x16, };
868 static int jz4760_nemc_cs3_pins[] = { 0x17, };
869 static int jz4760_nemc_cs4_pins[] = { 0x18, };
870 static int jz4760_nemc_cs5_pins[] = { 0x19, };
871 static int jz4760_nemc_cs6_pins[] = { 0x1a, };
872 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
873 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
874 static int jz4760_cim_pins[] = {
875 0x26, 0x27, 0x28, 0x29,
876 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
877 };
878 static int jz4760_lcd_8bit_pins[] = {
879 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c,
880 0x4d, 0x52, 0x53,
881 };
882 static int jz4760_lcd_16bit_pins[] = {
883 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
884 };
885 static int jz4760_lcd_18bit_pins[] = {
886 0x5a, 0x5b,
887 };
888 static int jz4760_lcd_24bit_pins[] = {
889 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
890 };
891 static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
892 static int jz4760_lcd_generic_pins[] = { 0x49, };
893 static int jz4760_pwm_pwm0_pins[] = { 0x80, };
894 static int jz4760_pwm_pwm1_pins[] = { 0x81, };
895 static int jz4760_pwm_pwm2_pins[] = { 0x82, };
896 static int jz4760_pwm_pwm3_pins[] = { 0x83, };
897 static int jz4760_pwm_pwm4_pins[] = { 0x84, };
898 static int jz4760_pwm_pwm5_pins[] = { 0x85, };
899 static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
900 static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
901 static int jz4760_otg_pins[] = { 0x8a, };
902
903 static u8 jz4760_uart3_data_funcs[] = { 0, 1, };
904 static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
905
906 static const struct group_desc jz4760_groups[] = {
907 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),
908 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),
909 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),
910 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),
911 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),
912 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),
913 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
914 jz4760_uart3_data_funcs),
915 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
916 INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2),
917 INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1),
918 INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1),
919 INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0),
920 INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1),
921 INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1),
922 INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1),
923 INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0),
924 INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2),
925 INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1),
926 INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1),
927 INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0),
928 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1),
929 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1),
930 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0),
931 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),
932 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),
933 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),
934 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),
935 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1),
936 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1),
937 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0),
938 INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2),
939 INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2),
940 INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2),
941 INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2),
942 INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1),
943 INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2),
944 INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2),
945 INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2),
946 INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2),
947 INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2),
948 INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1),
949 INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2),
950 INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2),
951 INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2),
952 INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2),
953 INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2),
954 INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1),
955 INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2),
956 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2),
957 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2),
958 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1),
959 INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),
960 INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),
961 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),
962 INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2),
963 INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1),
964 INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2),
965 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2),
966 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2),
967 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1),
968 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
969 jz4760_mmc0_1bit_a_funcs),
970 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
971 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),
972 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),
973 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),
974 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),
975 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),
976 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),
977 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),
978 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),
979 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),
980 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),
981 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),
982 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),
983 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),
984 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),
985 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),
986 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),
987 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),
988 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),
989 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),
990 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),
991 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),
992 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),
993 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),
994 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),
995 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),
996 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),
997 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
998 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
999 INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
1000 INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),
1001 INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),
1002 INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),
1003 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
1004 INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),
1005 INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),
1006 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0),
1007 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0),
1008 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0),
1009 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0),
1010 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0),
1011 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0),
1012 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0),
1013 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0),
1014 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1015 };
1016
1017 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1018 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1019 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1020 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1021 static const char *jz4760_ssi0_groups[] = {
1022 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1023 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1024 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1025 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1026 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1027 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1028 };
1029 static const char *jz4760_ssi1_groups[] = {
1030 "ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f",
1031 "ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f",
1032 "ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f",
1033 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1034 "ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f",
1035 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1036 };
1037 static const char *jz4760_mmc0_groups[] = {
1038 "mmc0-1bit-a", "mmc0-4bit-a",
1039 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1040 };
1041 static const char *jz4760_mmc1_groups[] = {
1042 "mmc1-1bit-d", "mmc1-4bit-d",
1043 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1044 };
1045 static const char *jz4760_mmc2_groups[] = {
1046 "mmc2-1bit-b", "mmc2-4bit-b",
1047 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1048 };
1049 static const char *jz4760_nemc_groups[] = {
1050 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1051 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1052 };
1053 static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
1054 static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
1055 static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
1056 static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
1057 static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
1058 static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
1059 static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
1060 static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
1061 static const char *jz4760_cim_groups[] = { "cim-data", };
1062 static const char *jz4760_lcd_groups[] = {
1063 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1064 "lcd-special", "lcd-generic",
1065 };
1066 static const char *jz4760_pwm0_groups[] = { "pwm0", };
1067 static const char *jz4760_pwm1_groups[] = { "pwm1", };
1068 static const char *jz4760_pwm2_groups[] = { "pwm2", };
1069 static const char *jz4760_pwm3_groups[] = { "pwm3", };
1070 static const char *jz4760_pwm4_groups[] = { "pwm4", };
1071 static const char *jz4760_pwm5_groups[] = { "pwm5", };
1072 static const char *jz4760_pwm6_groups[] = { "pwm6", };
1073 static const char *jz4760_pwm7_groups[] = { "pwm7", };
1074 static const char *jz4760_otg_groups[] = { "otg-vbus", };
1075
1076 static const struct function_desc jz4760_functions[] = {
1077 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
1078 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
1079 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
1080 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
1081 { "ssi0", jz4760_ssi0_groups, ARRAY_SIZE(jz4760_ssi0_groups), },
1082 { "ssi1", jz4760_ssi1_groups, ARRAY_SIZE(jz4760_ssi1_groups), },
1083 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
1084 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
1085 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
1086 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
1087 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
1088 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
1089 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
1090 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
1091 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
1092 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
1093 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
1094 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
1095 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
1096 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
1097 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
1098 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
1099 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
1100 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
1101 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
1102 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
1103 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
1104 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
1105 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
1106 };
1107
1108 static const struct ingenic_chip_info jz4760_chip_info = {
1109 .num_chips = 6,
1110 .reg_offset = 0x100,
1111 .version = ID_JZ4760,
1112 .groups = jz4760_groups,
1113 .num_groups = ARRAY_SIZE(jz4760_groups),
1114 .functions = jz4760_functions,
1115 .num_functions = ARRAY_SIZE(jz4760_functions),
1116 .pull_ups = jz4760_pull_ups,
1117 .pull_downs = jz4760_pull_downs,
1118 };
1119
1120 static const u32 jz4770_pull_ups[6] = {
1121 0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f,
1122 };
1123
1124 static const u32 jz4770_pull_downs[6] = {
1125 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0,
1126 };
1127
1128 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
1129 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
1130 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
1131 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
1132 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
1133 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
1134 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
1135 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
1136 static int jz4770_ssi0_dt_a_pins[] = { 0x15, };
1137 static int jz4770_ssi0_dt_b_pins[] = { 0x35, };
1138 static int jz4770_ssi0_dt_d_pins[] = { 0x75, };
1139 static int jz4770_ssi0_dt_e_pins[] = { 0x91, };
1140 static int jz4770_ssi0_dr_a_pins[] = { 0x14, };
1141 static int jz4770_ssi0_dr_b_pins[] = { 0x34, };
1142 static int jz4770_ssi0_dr_d_pins[] = { 0x74, };
1143 static int jz4770_ssi0_dr_e_pins[] = { 0x8e, };
1144 static int jz4770_ssi0_clk_a_pins[] = { 0x12, };
1145 static int jz4770_ssi0_clk_b_pins[] = { 0x3c, };
1146 static int jz4770_ssi0_clk_d_pins[] = { 0x78, };
1147 static int jz4770_ssi0_clk_e_pins[] = { 0x8f, };
1148 static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, };
1149 static int jz4770_ssi0_gpc_d_pins[] = { 0x76, };
1150 static int jz4770_ssi0_gpc_e_pins[] = { 0x93, };
1151 static int jz4770_ssi0_ce0_a_pins[] = { 0x13, };
1152 static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, };
1153 static int jz4770_ssi0_ce0_d_pins[] = { 0x79, };
1154 static int jz4770_ssi0_ce0_e_pins[] = { 0x90, };
1155 static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, };
1156 static int jz4770_ssi0_ce1_d_pins[] = { 0x77, };
1157 static int jz4770_ssi0_ce1_e_pins[] = { 0x92, };
1158 static int jz4770_ssi1_dt_b_pins[] = { 0x35, };
1159 static int jz4770_ssi1_dt_d_pins[] = { 0x75, };
1160 static int jz4770_ssi1_dt_e_pins[] = { 0x91, };
1161 static int jz4770_ssi1_dr_b_pins[] = { 0x34, };
1162 static int jz4770_ssi1_dr_d_pins[] = { 0x74, };
1163 static int jz4770_ssi1_dr_e_pins[] = { 0x8e, };
1164 static int jz4770_ssi1_clk_b_pins[] = { 0x3c, };
1165 static int jz4770_ssi1_clk_d_pins[] = { 0x78, };
1166 static int jz4770_ssi1_clk_e_pins[] = { 0x8f, };
1167 static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, };
1168 static int jz4770_ssi1_gpc_d_pins[] = { 0x76, };
1169 static int jz4770_ssi1_gpc_e_pins[] = { 0x93, };
1170 static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, };
1171 static int jz4770_ssi1_ce0_d_pins[] = { 0x79, };
1172 static int jz4770_ssi1_ce0_e_pins[] = { 0x90, };
1173 static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, };
1174 static int jz4770_ssi1_ce1_d_pins[] = { 0x77, };
1175 static int jz4770_ssi1_ce1_e_pins[] = { 0x92, };
1176 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
1177 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
1178 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1179 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1180 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
1181 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
1182 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
1183 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1184 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1185 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
1186 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
1187 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
1188 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1189 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1190 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
1191 static int jz4770_nemc_8bit_data_pins[] = {
1192 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1193 };
1194 static int jz4770_nemc_16bit_data_pins[] = {
1195 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1196 };
1197 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
1198 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
1199 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
1200 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
1201 static int jz4770_nemc_wait_pins[] = { 0x1b, };
1202 static int jz4770_nemc_cs1_pins[] = { 0x15, };
1203 static int jz4770_nemc_cs2_pins[] = { 0x16, };
1204 static int jz4770_nemc_cs3_pins[] = { 0x17, };
1205 static int jz4770_nemc_cs4_pins[] = { 0x18, };
1206 static int jz4770_nemc_cs5_pins[] = { 0x19, };
1207 static int jz4770_nemc_cs6_pins[] = { 0x1a, };
1208 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
1209 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
1210 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
1211 static int jz4770_cim_8bit_pins[] = {
1212 0x26, 0x27, 0x28, 0x29,
1213 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
1214 };
1215 static int jz4770_cim_12bit_pins[] = {
1216 0x32, 0x33, 0xb0, 0xb1,
1217 };
1218 static int jz4770_lcd_8bit_pins[] = {
1219 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
1220 0x48, 0x52, 0x53,
1221 };
1222 static int jz4770_lcd_16bit_pins[] = {
1223 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
1224 };
1225 static int jz4770_lcd_18bit_pins[] = {
1226 0x5a, 0x5b,
1227 };
1228 static int jz4770_lcd_24bit_pins[] = {
1229 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
1230 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
1231 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
1232 0x58, 0x59, 0x5a, 0x5b,
1233 };
1234 static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
1235 static int jz4770_lcd_generic_pins[] = { 0x49, };
1236 static int jz4770_pwm_pwm0_pins[] = { 0x80, };
1237 static int jz4770_pwm_pwm1_pins[] = { 0x81, };
1238 static int jz4770_pwm_pwm2_pins[] = { 0x82, };
1239 static int jz4770_pwm_pwm3_pins[] = { 0x83, };
1240 static int jz4770_pwm_pwm4_pins[] = { 0x84, };
1241 static int jz4770_pwm_pwm5_pins[] = { 0x85, };
1242 static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
1243 static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
1244 static int jz4770_mac_rmii_pins[] = {
1245 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
1246 };
1247 static int jz4770_mac_mii_pins[] = {
1248 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
1249 };
1250
1251 static const struct group_desc jz4770_groups[] = {
1252 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1253 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1254 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1255 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1256 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),
1257 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),
1258 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1259 jz4760_uart3_data_funcs),
1260 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1261 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),
1262 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),
1263 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),
1264 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1265 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),
1266 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),
1267 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),
1268 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1269 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),
1270 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),
1271 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),
1272 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1273 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),
1274 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),
1275 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1276 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),
1277 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),
1278 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),
1279 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1280 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),
1281 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),
1282 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1283 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),
1284 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),
1285 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1286 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),
1287 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),
1288 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1289 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),
1290 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),
1291 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1292 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),
1293 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),
1294 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1295 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),
1296 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),
1297 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1298 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),
1299 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),
1300 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1301 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1302 jz4760_mmc0_1bit_a_funcs),
1303 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1304 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1305 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1306 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),
1307 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1308 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1309 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1310 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1311 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),
1312 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1313 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1314 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1315 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1316 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),
1317 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),
1318 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),
1319 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1320 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1321 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1322 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1323 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1324 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1325 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1326 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1327 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1328 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1329 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1330 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1331 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1332 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1333 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),
1334 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1335 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1336 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1337 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1338 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1339 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1340 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1341 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
1342 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
1343 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
1344 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
1345 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
1346 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
1347 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
1348 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
1349 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
1350 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
1351 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1352 };
1353
1354 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1355 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1356 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1357 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1358 static const char *jz4770_ssi0_groups[] = {
1359 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1360 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1361 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1362 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1363 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1364 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1365 };
1366 static const char *jz4770_ssi1_groups[] = {
1367 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1368 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1369 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1370 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1371 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1372 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1373 };
1374 static const char *jz4770_mmc0_groups[] = {
1375 "mmc0-1bit-a", "mmc0-4bit-a",
1376 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1377 };
1378 static const char *jz4770_mmc1_groups[] = {
1379 "mmc1-1bit-d", "mmc1-4bit-d",
1380 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1381 };
1382 static const char *jz4770_mmc2_groups[] = {
1383 "mmc2-1bit-b", "mmc2-4bit-b",
1384 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1385 };
1386 static const char *jz4770_nemc_groups[] = {
1387 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1388 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1389 };
1390 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
1391 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
1392 static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
1393 static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
1394 static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
1395 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
1396 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
1397 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
1398 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
1399 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
1400 static const char *jz4770_lcd_groups[] = {
1401 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1402 "lcd-special", "lcd-generic",
1403 };
1404 static const char *jz4770_pwm0_groups[] = { "pwm0", };
1405 static const char *jz4770_pwm1_groups[] = { "pwm1", };
1406 static const char *jz4770_pwm2_groups[] = { "pwm2", };
1407 static const char *jz4770_pwm3_groups[] = { "pwm3", };
1408 static const char *jz4770_pwm4_groups[] = { "pwm4", };
1409 static const char *jz4770_pwm5_groups[] = { "pwm5", };
1410 static const char *jz4770_pwm6_groups[] = { "pwm6", };
1411 static const char *jz4770_pwm7_groups[] = { "pwm7", };
1412 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
1413
1414 static const struct function_desc jz4770_functions[] = {
1415 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
1416 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
1417 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
1418 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
1419 { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), },
1420 { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), },
1421 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
1422 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
1423 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
1424 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
1425 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1426 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1427 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1428 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1429 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1430 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1431 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1432 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1433 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
1434 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
1435 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1436 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1437 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1438 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1439 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1440 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1441 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1442 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1443 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
1444 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
1445 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
1446 };
1447
1448 static const struct ingenic_chip_info jz4770_chip_info = {
1449 .num_chips = 6,
1450 .reg_offset = 0x100,
1451 .version = ID_JZ4770,
1452 .groups = jz4770_groups,
1453 .num_groups = ARRAY_SIZE(jz4770_groups),
1454 .functions = jz4770_functions,
1455 .num_functions = ARRAY_SIZE(jz4770_functions),
1456 .pull_ups = jz4770_pull_ups,
1457 .pull_downs = jz4770_pull_downs,
1458 };
1459
1460 static const u32 jz4775_pull_ups[7] = {
1461 0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0,
1462 };
1463
1464 static const u32 jz4775_pull_downs[7] = {
1465 0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00,
1466 };
1467
1468 static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, };
1469 static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
1470 static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, };
1471 static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
1472 static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, };
1473 static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, };
1474 static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, };
1475 static int jz4775_ssi_dt_a_pins[] = { 0x13, };
1476 static int jz4775_ssi_dt_d_pins[] = { 0x75, };
1477 static int jz4775_ssi_dr_a_pins[] = { 0x14, };
1478 static int jz4775_ssi_dr_d_pins[] = { 0x74, };
1479 static int jz4775_ssi_clk_a_pins[] = { 0x12, };
1480 static int jz4775_ssi_clk_d_pins[] = { 0x78, };
1481 static int jz4775_ssi_gpc_pins[] = { 0x76, };
1482 static int jz4775_ssi_ce0_a_pins[] = { 0x17, };
1483 static int jz4775_ssi_ce0_d_pins[] = { 0x79, };
1484 static int jz4775_ssi_ce1_pins[] = { 0x77, };
1485 static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
1486 static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
1487 static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, };
1488 static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1489 static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1490 static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
1491 static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
1492 static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1493 static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1494 static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
1495 static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
1496 static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1497 static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1498 static int jz4775_nemc_8bit_data_pins[] = {
1499 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1500 };
1501 static int jz4775_nemc_16bit_data_pins[] = {
1502 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1,
1503 };
1504 static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, };
1505 static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
1506 static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, };
1507 static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
1508 static int jz4775_nemc_wait_pins[] = { 0x1b, };
1509 static int jz4775_nemc_cs1_pins[] = { 0x15, };
1510 static int jz4775_nemc_cs2_pins[] = { 0x16, };
1511 static int jz4775_nemc_cs3_pins[] = { 0x17, };
1512 static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, };
1513 static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, };
1514 static int jz4775_i2c2_pins[] = { 0x80, 0x83, };
1515 static int jz4775_i2s_data_tx_pins[] = { 0xa3, };
1516 static int jz4775_i2s_data_rx_pins[] = { 0xa2, };
1517 static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, };
1518 static int jz4775_i2s_sysclk_pins[] = { 0x83, };
1519 static int jz4775_dmic_pins[] = { 0xaa, 0xab, };
1520 static int jz4775_cim_pins[] = {
1521 0x26, 0x27, 0x28, 0x29,
1522 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
1523 };
1524 static int jz4775_lcd_8bit_pins[] = {
1525 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
1526 0x48, 0x52, 0x53,
1527 };
1528 static int jz4775_lcd_16bit_pins[] = {
1529 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
1530 };
1531 static int jz4775_lcd_18bit_pins[] = {
1532 0x5a, 0x5b,
1533 };
1534 static int jz4775_lcd_24bit_pins[] = {
1535 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
1536 };
1537 static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
1538 static int jz4775_lcd_generic_pins[] = { 0x49, };
1539 static int jz4775_pwm_pwm0_pins[] = { 0x80, };
1540 static int jz4775_pwm_pwm1_pins[] = { 0x81, };
1541 static int jz4775_pwm_pwm2_pins[] = { 0x82, };
1542 static int jz4775_pwm_pwm3_pins[] = { 0x83, };
1543 static int jz4775_mac_rmii_pins[] = {
1544 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
1545 };
1546 static int jz4775_mac_mii_pins[] = {
1547 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
1548 };
1549 static int jz4775_mac_rgmii_pins[] = {
1550 0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4,
1551 0xad, 0xae, 0xa7, 0xa6,
1552 };
1553 static int jz4775_mac_gmii_pins[] = {
1554 0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a,
1555 0xa8, 0x28, 0x24, 0xaf,
1556 };
1557 static int jz4775_otg_pins[] = { 0x8a, };
1558
1559 static u8 jz4775_uart3_data_funcs[] = { 0, 1, };
1560 static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, };
1561 static u8 jz4775_mac_rgmii_funcs[] = {
1562 0, 1, 1, 0, 0, 0, 1, 1, 0, 0,
1563 0, 0, 0, 0,
1564 };
1565 static u8 jz4775_mac_gmii_funcs[] = {
1566 1, 1, 1, 1, 1, 1, 1, 1,
1567 0, 1, 1, 0,
1568 };
1569
1570 static const struct group_desc jz4775_groups[] = {
1571 INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0),
1572 INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0),
1573 INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0),
1574 INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0),
1575 INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2),
1576 INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1),
1577 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data,
1578 jz4775_uart3_data_funcs),
1579 INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2),
1580 INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1),
1581 INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2),
1582 INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1),
1583 INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2),
1584 INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1),
1585 INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1),
1586 INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2),
1587 INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1),
1588 INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1),
1589 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1),
1590 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1),
1591 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1),
1592 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0),
1593 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0),
1594 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0),
1595 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0),
1596 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1),
1597 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1),
1598 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0),
1599 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0),
1600 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2),
1601 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2),
1602 INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0),
1603 INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1),
1604 INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0),
1605 INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0),
1606 INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0),
1607 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0),
1608 INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0),
1609 INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0),
1610 INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0),
1611 INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0),
1612 INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0),
1613 INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0),
1614 INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1),
1615 INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1),
1616 INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1),
1617 INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1),
1618 INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2),
1619 INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1),
1620 INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0),
1621 INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0),
1622 INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0),
1623 INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0),
1624 INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0),
1625 INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0),
1626 INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1),
1627 INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0),
1628 INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0),
1629 INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0),
1630 INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0),
1631 INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0),
1632 INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii,
1633 jz4775_mac_mii_funcs),
1634 INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii,
1635 jz4775_mac_rgmii_funcs),
1636 INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii,
1637 jz4775_mac_gmii_funcs),
1638 INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0),
1639 };
1640
1641 static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1642 static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1643 static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", };
1644 static const char *jz4775_uart3_groups[] = { "uart3-data", };
1645 static const char *jz4775_ssi_groups[] = {
1646 "ssi-dt-a", "ssi-dt-d",
1647 "ssi-dr-a", "ssi-dr-d",
1648 "ssi-clk-a", "ssi-clk-d",
1649 "ssi-gpc",
1650 "ssi-ce0-a", "ssi-ce0-d",
1651 "ssi-ce1",
1652 };
1653 static const char *jz4775_mmc0_groups[] = {
1654 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1655 "mmc0-1bit-e", "mmc0-4bit-e",
1656 };
1657 static const char *jz4775_mmc1_groups[] = {
1658 "mmc1-1bit-d", "mmc1-4bit-d",
1659 "mmc1-1bit-e", "mmc1-4bit-e",
1660 };
1661 static const char *jz4775_mmc2_groups[] = {
1662 "mmc2-1bit-b", "mmc2-4bit-b",
1663 "mmc2-1bit-e", "mmc2-4bit-e",
1664 };
1665 static const char *jz4775_nemc_groups[] = {
1666 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1667 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1668 };
1669 static const char *jz4775_cs1_groups[] = { "nemc-cs1", };
1670 static const char *jz4775_cs2_groups[] = { "nemc-cs2", };
1671 static const char *jz4775_cs3_groups[] = { "nemc-cs3", };
1672 static const char *jz4775_i2c0_groups[] = { "i2c0-data", };
1673 static const char *jz4775_i2c1_groups[] = { "i2c1-data", };
1674 static const char *jz4775_i2c2_groups[] = { "i2c2-data", };
1675 static const char *jz4775_i2s_groups[] = {
1676 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1677 };
1678 static const char *jz4775_dmic_groups[] = { "dmic", };
1679 static const char *jz4775_cim_groups[] = { "cim-data", };
1680 static const char *jz4775_lcd_groups[] = {
1681 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1682 "lcd-special", "lcd-generic",
1683 };
1684 static const char *jz4775_pwm0_groups[] = { "pwm0", };
1685 static const char *jz4775_pwm1_groups[] = { "pwm1", };
1686 static const char *jz4775_pwm2_groups[] = { "pwm2", };
1687 static const char *jz4775_pwm3_groups[] = { "pwm3", };
1688 static const char *jz4775_mac_groups[] = {
1689 "mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii",
1690 };
1691 static const char *jz4775_otg_groups[] = { "otg-vbus", };
1692
1693 static const struct function_desc jz4775_functions[] = {
1694 { "uart0", jz4775_uart0_groups, ARRAY_SIZE(jz4775_uart0_groups), },
1695 { "uart1", jz4775_uart1_groups, ARRAY_SIZE(jz4775_uart1_groups), },
1696 { "uart2", jz4775_uart2_groups, ARRAY_SIZE(jz4775_uart2_groups), },
1697 { "uart3", jz4775_uart3_groups, ARRAY_SIZE(jz4775_uart3_groups), },
1698 { "ssi", jz4775_ssi_groups, ARRAY_SIZE(jz4775_ssi_groups), },
1699 { "mmc0", jz4775_mmc0_groups, ARRAY_SIZE(jz4775_mmc0_groups), },
1700 { "mmc1", jz4775_mmc1_groups, ARRAY_SIZE(jz4775_mmc1_groups), },
1701 { "mmc2", jz4775_mmc2_groups, ARRAY_SIZE(jz4775_mmc2_groups), },
1702 { "nemc", jz4775_nemc_groups, ARRAY_SIZE(jz4775_nemc_groups), },
1703 { "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), },
1704 { "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), },
1705 { "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), },
1706 { "i2c0", jz4775_i2c0_groups, ARRAY_SIZE(jz4775_i2c0_groups), },
1707 { "i2c1", jz4775_i2c1_groups, ARRAY_SIZE(jz4775_i2c1_groups), },
1708 { "i2c2", jz4775_i2c2_groups, ARRAY_SIZE(jz4775_i2c2_groups), },
1709 { "i2s", jz4775_i2s_groups, ARRAY_SIZE(jz4775_i2s_groups), },
1710 { "dmic", jz4775_dmic_groups, ARRAY_SIZE(jz4775_dmic_groups), },
1711 { "cim", jz4775_cim_groups, ARRAY_SIZE(jz4775_cim_groups), },
1712 { "lcd", jz4775_lcd_groups, ARRAY_SIZE(jz4775_lcd_groups), },
1713 { "pwm0", jz4775_pwm0_groups, ARRAY_SIZE(jz4775_pwm0_groups), },
1714 { "pwm1", jz4775_pwm1_groups, ARRAY_SIZE(jz4775_pwm1_groups), },
1715 { "pwm2", jz4775_pwm2_groups, ARRAY_SIZE(jz4775_pwm2_groups), },
1716 { "pwm3", jz4775_pwm3_groups, ARRAY_SIZE(jz4775_pwm3_groups), },
1717 { "mac", jz4775_mac_groups, ARRAY_SIZE(jz4775_mac_groups), },
1718 { "otg", jz4775_otg_groups, ARRAY_SIZE(jz4775_otg_groups), },
1719 };
1720
1721 static const struct ingenic_chip_info jz4775_chip_info = {
1722 .num_chips = 7,
1723 .reg_offset = 0x100,
1724 .version = ID_JZ4775,
1725 .groups = jz4775_groups,
1726 .num_groups = ARRAY_SIZE(jz4775_groups),
1727 .functions = jz4775_functions,
1728 .num_functions = ARRAY_SIZE(jz4775_functions),
1729 .pull_ups = jz4775_pull_ups,
1730 .pull_downs = jz4775_pull_downs,
1731 };
1732
1733 static const u32 jz4780_pull_ups[6] = {
1734 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f,
1735 };
1736
1737 static const u32 jz4780_pull_downs[6] = {
1738 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
1739 };
1740
1741 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
1742 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
1743 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
1744 static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, };
1745 static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, };
1746 static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, };
1747 static int jz4780_ssi0_dt_b_pins[] = { 0x3d, };
1748 static int jz4780_ssi0_dt_d_pins[] = { 0x79, };
1749 static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, };
1750 static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, };
1751 static int jz4780_ssi0_dr_b_pins[] = { 0x34, };
1752 static int jz4780_ssi0_dr_d_pins[] = { 0x74, };
1753 static int jz4780_ssi0_clk_a_pins[] = { 0x12, };
1754 static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, };
1755 static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, };
1756 static int jz4780_ssi0_clk_d_pins[] = { 0x78, };
1757 static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, };
1758 static int jz4780_ssi0_gpc_d_pins[] = { 0x76, };
1759 static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, };
1760 static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, };
1761 static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, };
1762 static int jz4780_ssi0_ce0_d_pins[] = { 0x77, };
1763 static int jz4780_ssi0_ce1_b_pins[] = { 0x35, };
1764 static int jz4780_ssi0_ce1_d_pins[] = { 0x75, };
1765 static int jz4780_ssi1_dt_b_pins[] = { 0x3d, };
1766 static int jz4780_ssi1_dt_d_pins[] = { 0x79, };
1767 static int jz4780_ssi1_dr_b_pins[] = { 0x34, };
1768 static int jz4780_ssi1_dr_d_pins[] = { 0x74, };
1769 static int jz4780_ssi1_clk_b_pins[] = { 0x3c, };
1770 static int jz4780_ssi1_clk_d_pins[] = { 0x78, };
1771 static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, };
1772 static int jz4780_ssi1_gpc_d_pins[] = { 0x76, };
1773 static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, };
1774 static int jz4780_ssi1_ce0_d_pins[] = { 0x77, };
1775 static int jz4780_ssi1_ce1_b_pins[] = { 0x35, };
1776 static int jz4780_ssi1_ce1_d_pins[] = { 0x75, };
1777 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
1778 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
1779 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
1780 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
1781 static int jz4780_i2s_data_tx_pins[] = { 0x87, };
1782 static int jz4780_i2s_data_rx_pins[] = { 0x86, };
1783 static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, };
1784 static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, };
1785 static int jz4780_i2s_sysclk_pins[] = { 0x85, };
1786 static int jz4780_dmic_pins[] = { 0x32, 0x33, };
1787 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
1788
1789 static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };
1790
1791 static const struct group_desc jz4780_groups[] = {
1792 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1793 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1794 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1795 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1796 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),
1797 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),
1798 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1799 jz4760_uart3_data_funcs),
1800 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1801 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),
1802 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),
1803 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),
1804 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),
1805 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),
1806 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),
1807 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1808 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),
1809 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),
1810 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),
1811 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),
1812 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1813 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),
1814 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),
1815 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),
1816 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),
1817 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1818 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),
1819 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),
1820 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1821 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),
1822 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),
1823 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),
1824 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),
1825 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1826 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),
1827 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),
1828 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1829 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),
1830 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),
1831 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1832 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),
1833 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),
1834 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1835 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),
1836 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),
1837 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1838 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),
1839 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),
1840 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1841 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),
1842 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),
1843 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1844 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),
1845 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),
1846 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1847 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1848 jz4760_mmc0_1bit_a_funcs),
1849 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1850 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),
1851 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1852 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1853 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1854 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1855 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1856 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1857 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1858 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1859 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1860 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1861 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),
1862 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1863 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1864 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1865 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1866 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1867 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1868 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1869 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1870 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1871 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1872 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1873 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1874 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1875 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1876 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),
1877 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),
1878 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),
1879 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),
1880 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),
1881 INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,
1882 jz4780_i2s_clk_txrx_funcs),
1883 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),
1884 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),
1885 INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1),
1886 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),
1887 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),
1888 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1889 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1890 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1891 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1892 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1893 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1894 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1895 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
1896 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
1897 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
1898 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
1899 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
1900 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
1901 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
1902 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
1903 };
1904
1905 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1906 static const char *jz4780_uart4_groups[] = { "uart4-data", };
1907 static const char *jz4780_ssi0_groups[] = {
1908 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1909 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1910 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
1911 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1912 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1913 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1914 };
1915 static const char *jz4780_ssi1_groups[] = {
1916 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1917 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1918 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1919 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1920 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1921 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1922 };
1923 static const char *jz4780_mmc0_groups[] = {
1924 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1925 "mmc0-1bit-e", "mmc0-4bit-e",
1926 };
1927 static const char *jz4780_mmc1_groups[] = {
1928 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
1929 };
1930 static const char *jz4780_mmc2_groups[] = {
1931 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
1932 };
1933 static const char *jz4780_nemc_groups[] = {
1934 "nemc-data", "nemc-cle-ale", "nemc-addr",
1935 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1936 };
1937 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
1938 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
1939 static const char *jz4780_i2s_groups[] = {
1940 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1941 };
1942 static const char *jz4780_dmic_groups[] = { "dmic", };
1943 static const char *jz4780_cim_groups[] = { "cim-data", };
1944 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
1945
1946 static const struct function_desc jz4780_functions[] = {
1947 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
1948 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
1949 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
1950 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
1951 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
1952 { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), },
1953 { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), },
1954 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
1955 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
1956 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
1957 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
1958 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1959 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1960 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1961 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1962 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1963 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1964 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1965 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1966 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
1967 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
1968 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
1969 { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), },
1970 { "dmic", jz4780_dmic_groups, ARRAY_SIZE(jz4780_dmic_groups), },
1971 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
1972 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1973 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1974 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1975 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1976 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1977 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1978 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1979 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1980 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
1981 { "hdmi-ddc", jz4780_hdmi_ddc_groups,
1982 ARRAY_SIZE(jz4780_hdmi_ddc_groups), },
1983 };
1984
1985 static const struct ingenic_chip_info jz4780_chip_info = {
1986 .num_chips = 6,
1987 .reg_offset = 0x100,
1988 .version = ID_JZ4780,
1989 .groups = jz4780_groups,
1990 .num_groups = ARRAY_SIZE(jz4780_groups),
1991 .functions = jz4780_functions,
1992 .num_functions = ARRAY_SIZE(jz4780_functions),
1993 .pull_ups = jz4780_pull_ups,
1994 .pull_downs = jz4780_pull_downs,
1995 };
1996
1997 static const u32 x1000_pull_ups[4] = {
1998 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,
1999 };
2000
2001 static const u32 x1000_pull_downs[4] = {
2002 0x00000000, 0x02000000, 0x02000000, 0x00000000,
2003 };
2004
2005 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
2006 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
2007 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
2008 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
2009 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
2010 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
2011 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
2012 static int x1000_sfc_data_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, };
2013 static int x1000_sfc_clk_pins[] = { 0x1a, };
2014 static int x1000_sfc_ce_pins[] = { 0x1b, };
2015 static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
2016 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
2017 static int x1000_ssi_dt_d_pins[] = { 0x62, };
2018 static int x1000_ssi_dr_a_23_pins[] = { 0x17, };
2019 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };
2020 static int x1000_ssi_dr_d_pins[] = { 0x63, };
2021 static int x1000_ssi_clk_a_24_pins[] = { 0x18, };
2022 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };
2023 static int x1000_ssi_clk_d_pins[] = { 0x60, };
2024 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };
2025 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };
2026 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };
2027 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };
2028 static int x1000_ssi_ce0_d_pins[] = { 0x61, };
2029 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };
2030 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };
2031 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
2032 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
2033 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
2034 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
2035 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
2036 static int x1000_emc_8bit_data_pins[] = {
2037 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2038 };
2039 static int x1000_emc_16bit_data_pins[] = {
2040 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2041 };
2042 static int x1000_emc_addr_pins[] = {
2043 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2044 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
2045 };
2046 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };
2047 static int x1000_emc_wait_pins[] = { 0x34, };
2048 static int x1000_emc_cs1_pins[] = { 0x32, };
2049 static int x1000_emc_cs2_pins[] = { 0x33, };
2050 static int x1000_i2c0_pins[] = { 0x38, 0x37, };
2051 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
2052 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
2053 static int x1000_i2c2_pins[] = { 0x61, 0x60, };
2054 static int x1000_i2s_data_tx_pins[] = { 0x24, };
2055 static int x1000_i2s_data_rx_pins[] = { 0x23, };
2056 static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
2057 static int x1000_i2s_sysclk_pins[] = { 0x20, };
2058 static int x1000_dmic_if0_pins[] = { 0x35, 0x36, };
2059 static int x1000_dmic_if1_pins[] = { 0x25, };
2060 static int x1000_cim_pins[] = {
2061 0x08, 0x09, 0x0a, 0x0b,
2062 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
2063 };
2064 static int x1000_lcd_8bit_pins[] = {
2065 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2066 0x30, 0x31, 0x32, 0x33, 0x34,
2067 };
2068 static int x1000_lcd_16bit_pins[] = {
2069 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2070 };
2071 static int x1000_pwm_pwm0_pins[] = { 0x59, };
2072 static int x1000_pwm_pwm1_pins[] = { 0x5a, };
2073 static int x1000_pwm_pwm2_pins[] = { 0x5b, };
2074 static int x1000_pwm_pwm3_pins[] = { 0x26, };
2075 static int x1000_pwm_pwm4_pins[] = { 0x58, };
2076 static int x1000_mac_pins[] = {
2077 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
2078 };
2079
2080 static const struct group_desc x1000_groups[] = {
2081 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),
2082 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),
2083 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),
2084 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),
2085 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
2086 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
2087 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
2088 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2089 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2090 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2091 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
2092 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
2093 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
2094 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),
2095 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),
2096 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),
2097 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),
2098 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),
2099 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),
2100 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),
2101 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),
2102 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),
2103 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),
2104 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),
2105 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),
2106 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),
2107 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),
2108 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),
2109 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),
2110 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),
2111 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),
2112 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),
2113 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),
2114 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),
2115 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),
2116 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),
2117 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),
2118 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),
2119 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),
2120 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),
2121 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),
2122 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),
2123 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),
2124 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
2125 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
2126 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
2127 INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0),
2128 INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1),
2129 INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
2130 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
2131 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
2132 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0),
2133 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1),
2134 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1),
2135 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2),
2136 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0),
2137 INGENIC_PIN_GROUP("mac", x1000_mac, 1),
2138 };
2139
2140 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2141 static const char *x1000_uart1_groups[] = {
2142 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
2143 };
2144 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2145 static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2146 static const char *x1000_ssi_groups[] = {
2147 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
2148 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
2149 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
2150 "ssi-gpc-a-20", "ssi-gpc-a-31",
2151 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
2152 "ssi-ce1-a-21", "ssi-ce1-a-30",
2153 };
2154 static const char *x1000_mmc0_groups[] = {
2155 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
2156 };
2157 static const char *x1000_mmc1_groups[] = {
2158 "mmc1-1bit", "mmc1-4bit",
2159 };
2160 static const char *x1000_emc_groups[] = {
2161 "emc-8bit-data", "emc-16bit-data",
2162 "emc-addr", "emc-rd-we", "emc-wait",
2163 };
2164 static const char *x1000_cs1_groups[] = { "emc-cs1", };
2165 static const char *x1000_cs2_groups[] = { "emc-cs2", };
2166 static const char *x1000_i2c0_groups[] = { "i2c0-data", };
2167 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2168 static const char *x1000_i2c2_groups[] = { "i2c2-data", };
2169 static const char *x1000_i2s_groups[] = {
2170 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2171 };
2172 static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2173 static const char *x1000_cim_groups[] = { "cim-data", };
2174 static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", };
2175 static const char *x1000_pwm0_groups[] = { "pwm0", };
2176 static const char *x1000_pwm1_groups[] = { "pwm1", };
2177 static const char *x1000_pwm2_groups[] = { "pwm2", };
2178 static const char *x1000_pwm3_groups[] = { "pwm3", };
2179 static const char *x1000_pwm4_groups[] = { "pwm4", };
2180 static const char *x1000_mac_groups[] = { "mac", };
2181
2182 static const struct function_desc x1000_functions[] = {
2183 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
2184 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
2185 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
2186 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
2187 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), },
2188 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
2189 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
2190 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), },
2191 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
2192 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
2193 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
2194 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
2195 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
2196 { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), },
2197 { "dmic", x1000_dmic_groups, ARRAY_SIZE(x1000_dmic_groups), },
2198 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
2199 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
2200 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
2201 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
2202 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
2203 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
2204 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
2205 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
2206 };
2207
2208 static const struct regmap_range x1000_access_ranges[] = {
2209 regmap_reg_range(0x000, 0x400 - 4),
2210 regmap_reg_range(0x700, 0x800 - 4),
2211 };
2212
2213 /* shared with X1500 */
2214 static const struct regmap_access_table x1000_access_table = {
2215 .yes_ranges = x1000_access_ranges,
2216 .n_yes_ranges = ARRAY_SIZE(x1000_access_ranges),
2217 };
2218
2219 static const struct ingenic_chip_info x1000_chip_info = {
2220 .num_chips = 4,
2221 .reg_offset = 0x100,
2222 .version = ID_X1000,
2223 .groups = x1000_groups,
2224 .num_groups = ARRAY_SIZE(x1000_groups),
2225 .functions = x1000_functions,
2226 .num_functions = ARRAY_SIZE(x1000_functions),
2227 .pull_ups = x1000_pull_ups,
2228 .pull_downs = x1000_pull_downs,
2229 .access_table = &x1000_access_table,
2230 };
2231
2232 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
2233 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
2234 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
2235 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
2236 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };
2237 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
2238 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
2239 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };
2240 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };
2241 static int x1500_i2c0_pins[] = { 0x38, 0x37, };
2242 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
2243 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
2244 static int x1500_i2c2_pins[] = { 0x61, 0x60, };
2245 static int x1500_i2s_data_tx_pins[] = { 0x24, };
2246 static int x1500_i2s_data_rx_pins[] = { 0x23, };
2247 static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
2248 static int x1500_i2s_sysclk_pins[] = { 0x20, };
2249 static int x1500_dmic_if0_pins[] = { 0x35, 0x36, };
2250 static int x1500_dmic_if1_pins[] = { 0x25, };
2251 static int x1500_cim_pins[] = {
2252 0x08, 0x09, 0x0a, 0x0b,
2253 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
2254 };
2255 static int x1500_pwm_pwm0_pins[] = { 0x59, };
2256 static int x1500_pwm_pwm1_pins[] = { 0x5a, };
2257 static int x1500_pwm_pwm2_pins[] = { 0x5b, };
2258 static int x1500_pwm_pwm3_pins[] = { 0x26, };
2259 static int x1500_pwm_pwm4_pins[] = { 0x58, };
2260
2261 static const struct group_desc x1500_groups[] = {
2262 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),
2263 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),
2264 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),
2265 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),
2266 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
2267 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
2268 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
2269 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2270 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2271 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2272 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
2273 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
2274 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
2275 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),
2276 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),
2277 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),
2278 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),
2279 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
2280 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
2281 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
2282 INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0),
2283 INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1),
2284 INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
2285 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0),
2286 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1),
2287 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1),
2288 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2),
2289 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0),
2290 };
2291
2292 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2293 static const char *x1500_uart1_groups[] = {
2294 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
2295 };
2296 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2297 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
2298 static const char *x1500_i2c0_groups[] = { "i2c0-data", };
2299 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2300 static const char *x1500_i2c2_groups[] = { "i2c2-data", };
2301 static const char *x1500_i2s_groups[] = {
2302 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2303 };
2304 static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2305 static const char *x1500_cim_groups[] = { "cim-data", };
2306 static const char *x1500_pwm0_groups[] = { "pwm0", };
2307 static const char *x1500_pwm1_groups[] = { "pwm1", };
2308 static const char *x1500_pwm2_groups[] = { "pwm2", };
2309 static const char *x1500_pwm3_groups[] = { "pwm3", };
2310 static const char *x1500_pwm4_groups[] = { "pwm4", };
2311
2312 static const struct function_desc x1500_functions[] = {
2313 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
2314 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
2315 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
2316 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
2317 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
2318 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
2319 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
2320 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
2321 { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), },
2322 { "dmic", x1500_dmic_groups, ARRAY_SIZE(x1500_dmic_groups), },
2323 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
2324 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
2325 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
2326 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
2327 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
2328 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
2329 };
2330
2331 static const struct ingenic_chip_info x1500_chip_info = {
2332 .num_chips = 4,
2333 .reg_offset = 0x100,
2334 .version = ID_X1500,
2335 .groups = x1500_groups,
2336 .num_groups = ARRAY_SIZE(x1500_groups),
2337 .functions = x1500_functions,
2338 .num_functions = ARRAY_SIZE(x1500_functions),
2339 .pull_ups = x1000_pull_ups,
2340 .pull_downs = x1000_pull_downs,
2341 .access_table = &x1000_access_table,
2342 };
2343
2344 static const u32 x1830_pull_ups[4] = {
2345 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
2346 };
2347
2348 static const u32 x1830_pull_downs[4] = {
2349 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
2350 };
2351
2352 static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
2353 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
2354 static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
2355 static int x1830_sfc_data_pins[] = { 0x17, 0x18, 0x1a, 0x19, };
2356 static int x1830_sfc_clk_pins[] = { 0x1b, };
2357 static int x1830_sfc_ce_pins[] = { 0x1c, };
2358 static int x1830_ssi0_dt_pins[] = { 0x4c, };
2359 static int x1830_ssi0_dr_pins[] = { 0x4b, };
2360 static int x1830_ssi0_clk_pins[] = { 0x4f, };
2361 static int x1830_ssi0_gpc_pins[] = { 0x4d, };
2362 static int x1830_ssi0_ce0_pins[] = { 0x50, };
2363 static int x1830_ssi0_ce1_pins[] = { 0x4e, };
2364 static int x1830_ssi1_dt_c_pins[] = { 0x53, };
2365 static int x1830_ssi1_dt_d_pins[] = { 0x62, };
2366 static int x1830_ssi1_dr_c_pins[] = { 0x54, };
2367 static int x1830_ssi1_dr_d_pins[] = { 0x63, };
2368 static int x1830_ssi1_clk_c_pins[] = { 0x57, };
2369 static int x1830_ssi1_clk_d_pins[] = { 0x66, };
2370 static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
2371 static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
2372 static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
2373 static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
2374 static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
2375 static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
2376 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
2377 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
2378 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };
2379 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
2380 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
2381 static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
2382 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
2383 static int x1830_i2s_data_tx_pins[] = { 0x53, };
2384 static int x1830_i2s_data_rx_pins[] = { 0x54, };
2385 static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, };
2386 static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, };
2387 static int x1830_i2s_sysclk_pins[] = { 0x57, };
2388 static int x1830_dmic_if0_pins[] = { 0x48, 0x59, };
2389 static int x1830_dmic_if1_pins[] = { 0x5a, };
2390 static int x1830_lcd_tft_8bit_pins[] = {
2391 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
2392 0x68, 0x73, 0x72, 0x69,
2393 };
2394 static int x1830_lcd_tft_24bit_pins[] = {
2395 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71,
2396 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b,
2397 };
2398 static int x1830_lcd_slcd_8bit_pins[] = {
2399 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d,
2400 0x69, 0x72, 0x73, 0x7b, 0x7a,
2401 };
2402 static int x1830_lcd_slcd_16bit_pins[] = {
2403 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79,
2404 };
2405 static int x1830_pwm_pwm0_b_pins[] = { 0x31, };
2406 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };
2407 static int x1830_pwm_pwm1_b_pins[] = { 0x32, };
2408 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };
2409 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };
2410 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };
2411 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };
2412 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };
2413 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };
2414 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };
2415 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };
2416 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };
2417 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };
2418 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };
2419 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };
2420 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };
2421 static int x1830_mac_pins[] = {
2422 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
2423 };
2424
2425 static const struct group_desc x1830_groups[] = {
2426 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
2427 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
2428 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
2429 INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1),
2430 INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1),
2431 INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1),
2432 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
2433 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
2434 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
2435 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),
2436 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),
2437 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),
2438 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),
2439 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),
2440 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),
2441 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),
2442 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),
2443 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),
2444 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),
2445 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),
2446 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),
2447 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),
2448 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),
2449 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),
2450 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),
2451 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),
2452 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),
2453 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),
2454 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),
2455 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),
2456 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),
2457 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),
2458 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),
2459 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
2460 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
2461 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
2462 INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2),
2463 INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2),
2464 INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0),
2465 INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0),
2466 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
2467 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),
2468 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),
2469 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),
2470 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),
2471 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),
2472 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),
2473 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),
2474 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),
2475 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),
2476 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),
2477 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),
2478 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),
2479 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),
2480 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),
2481 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),
2482 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),
2483 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),
2484 INGENIC_PIN_GROUP("mac", x1830_mac, 0),
2485 };
2486
2487 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2488 static const char *x1830_uart1_groups[] = { "uart1-data", };
2489 static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2490 static const char *x1830_ssi0_groups[] = {
2491 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
2492 };
2493 static const char *x1830_ssi1_groups[] = {
2494 "ssi1-dt-c", "ssi1-dt-d",
2495 "ssi1-dr-c", "ssi1-dr-d",
2496 "ssi1-clk-c", "ssi1-clk-d",
2497 "ssi1-gpc-c", "ssi1-gpc-d",
2498 "ssi1-ce0-c", "ssi1-ce0-d",
2499 "ssi1-ce1-c", "ssi1-ce1-d",
2500 };
2501 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
2502 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2503 static const char *x1830_i2c0_groups[] = { "i2c0-data", };
2504 static const char *x1830_i2c1_groups[] = { "i2c1-data", };
2505 static const char *x1830_i2c2_groups[] = { "i2c2-data", };
2506 static const char *x1830_i2s_groups[] = {
2507 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
2508 };
2509 static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2510 static const char *x1830_lcd_groups[] = {
2511 "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit",
2512 };
2513 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
2514 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
2515 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
2516 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
2517 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
2518 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
2519 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
2520 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
2521 static const char *x1830_mac_groups[] = { "mac", };
2522
2523 static const struct function_desc x1830_functions[] = {
2524 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), },
2525 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), },
2526 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), },
2527 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), },
2528 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), },
2529 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), },
2530 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), },
2531 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
2532 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
2533 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
2534 { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), },
2535 { "dmic", x1830_dmic_groups, ARRAY_SIZE(x1830_dmic_groups), },
2536 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), },
2537 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
2538 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },
2539 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), },
2540 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), },
2541 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2542 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2543 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2544 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2545 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
2546 };
2547
2548 static const struct regmap_range x1830_access_ranges[] = {
2549 regmap_reg_range(0x0000, 0x4000 - 4),
2550 regmap_reg_range(0x7000, 0x8000 - 4),
2551 };
2552
2553 static const struct regmap_access_table x1830_access_table = {
2554 .yes_ranges = x1830_access_ranges,
2555 .n_yes_ranges = ARRAY_SIZE(x1830_access_ranges),
2556 };
2557
2558 static const struct ingenic_chip_info x1830_chip_info = {
2559 .num_chips = 4,
2560 .reg_offset = 0x1000,
2561 .version = ID_X1830,
2562 .groups = x1830_groups,
2563 .num_groups = ARRAY_SIZE(x1830_groups),
2564 .functions = x1830_functions,
2565 .num_functions = ARRAY_SIZE(x1830_functions),
2566 .pull_ups = x1830_pull_ups,
2567 .pull_downs = x1830_pull_downs,
2568 .access_table = &x1830_access_table,
2569 };
2570
2571 static const u32 x2000_pull_ups[5] = {
2572 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f,
2573 };
2574
2575 static const u32 x2000_pull_downs[5] = {
2576 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f,
2577 };
2578
2579 static int x2000_uart0_data_pins[] = { 0x77, 0x78, };
2580 static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, };
2581 static int x2000_uart1_data_pins[] = { 0x57, 0x58, };
2582 static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, };
2583 static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, };
2584 static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, };
2585 static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, };
2586 static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, };
2587 static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, };
2588 static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, };
2589 static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, };
2590 static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, };
2591 static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, };
2592 static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, };
2593 static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, };
2594 static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, };
2595 static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, };
2596 static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, };
2597 static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, };
2598 static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, };
2599 static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, };
2600 static int x2000_sfc_data_if0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, };
2601 static int x2000_sfc_data_if0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, };
2602 static int x2000_sfc_data_if1_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
2603 static int x2000_sfc_clk_d_pins[] = { 0x71, };
2604 static int x2000_sfc_clk_e_pins[] = { 0x90, };
2605 static int x2000_sfc_ce_d_pins[] = { 0x72, };
2606 static int x2000_sfc_ce_e_pins[] = { 0x91, };
2607 static int x2000_ssi0_dt_b_pins[] = { 0x3e, };
2608 static int x2000_ssi0_dt_d_pins[] = { 0x69, };
2609 static int x2000_ssi0_dr_b_pins[] = { 0x3d, };
2610 static int x2000_ssi0_dr_d_pins[] = { 0x6a, };
2611 static int x2000_ssi0_clk_b_pins[] = { 0x3f, };
2612 static int x2000_ssi0_clk_d_pins[] = { 0x68, };
2613 static int x2000_ssi0_ce_b_pins[] = { 0x3c, };
2614 static int x2000_ssi0_ce_d_pins[] = { 0x6d, };
2615 static int x2000_ssi1_dt_c_pins[] = { 0x4b, };
2616 static int x2000_ssi1_dt_d_pins[] = { 0x72, };
2617 static int x2000_ssi1_dt_e_pins[] = { 0x91, };
2618 static int x2000_ssi1_dr_c_pins[] = { 0x4a, };
2619 static int x2000_ssi1_dr_d_pins[] = { 0x73, };
2620 static int x2000_ssi1_dr_e_pins[] = { 0x92, };
2621 static int x2000_ssi1_clk_c_pins[] = { 0x4c, };
2622 static int x2000_ssi1_clk_d_pins[] = { 0x71, };
2623 static int x2000_ssi1_clk_e_pins[] = { 0x90, };
2624 static int x2000_ssi1_ce_c_pins[] = { 0x49, };
2625 static int x2000_ssi1_ce_d_pins[] = { 0x76, };
2626 static int x2000_ssi1_ce_e_pins[] = { 0x95, };
2627 static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, };
2628 static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, };
2629 static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
2630 static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, };
2631 static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
2632 static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, };
2633 static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, };
2634 static int x2000_emc_8bit_data_pins[] = {
2635 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
2636 };
2637 static int x2000_emc_16bit_data_pins[] = {
2638 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
2639 };
2640 static int x2000_emc_addr_pins[] = {
2641 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2642 0x28, 0x29, 0x2a, 0x2b, 0x2c,
2643 };
2644 static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, };
2645 static int x2000_emc_wait_pins[] = { 0x2f, };
2646 static int x2000_emc_cs1_pins[] = { 0x57, };
2647 static int x2000_emc_cs2_pins[] = { 0x58, };
2648 static int x2000_i2c0_pins[] = { 0x4e, 0x4d, };
2649 static int x2000_i2c1_c_pins[] = { 0x58, 0x57, };
2650 static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, };
2651 static int x2000_i2c2_b_pins[] = { 0x37, 0x36, };
2652 static int x2000_i2c2_d_pins[] = { 0x75, 0x74, };
2653 static int x2000_i2c2_e_pins[] = { 0x94, 0x93, };
2654 static int x2000_i2c3_a_pins[] = { 0x11, 0x10, };
2655 static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, };
2656 static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, };
2657 static int x2000_i2c4_d_pins[] = { 0x61, 0x60, };
2658 static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, };
2659 static int x2000_i2c5_d_pins[] = { 0x65, 0x64, };
2660 static int x2000_i2s1_data_tx_pins[] = { 0x47, };
2661 static int x2000_i2s1_data_rx_pins[] = { 0x44, };
2662 static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, };
2663 static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, };
2664 static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, };
2665 static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, };
2666 static int x2000_i2s2_data_rx0_pins[] = { 0x0a, };
2667 static int x2000_i2s2_data_rx1_pins[] = { 0x0b, };
2668 static int x2000_i2s2_data_rx2_pins[] = { 0x0c, };
2669 static int x2000_i2s2_data_rx3_pins[] = { 0x0d, };
2670 static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, };
2671 static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, };
2672 static int x2000_i2s3_data_tx0_pins[] = { 0x03, };
2673 static int x2000_i2s3_data_tx1_pins[] = { 0x04, };
2674 static int x2000_i2s3_data_tx2_pins[] = { 0x05, };
2675 static int x2000_i2s3_data_tx3_pins[] = { 0x06, };
2676 static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, };
2677 static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, };
2678 static int x2000_dmic_if0_pins[] = { 0x54, 0x55, };
2679 static int x2000_dmic_if1_pins[] = { 0x56, };
2680 static int x2000_dmic_if2_pins[] = { 0x57, };
2681 static int x2000_dmic_if3_pins[] = { 0x58, };
2682 static int x2000_cim_8bit_pins[] = {
2683 0x0e, 0x0c, 0x0d, 0x4f,
2684 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2685 };
2686 static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, };
2687 static int x2000_lcd_tft_8bit_pins[] = {
2688 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2689 0x38, 0x3a, 0x39, 0x3b,
2690 };
2691 static int x2000_lcd_tft_16bit_pins[] = {
2692 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
2693 };
2694 static int x2000_lcd_tft_18bit_pins[] = {
2695 0x30, 0x31,
2696 };
2697 static int x2000_lcd_tft_24bit_pins[] = {
2698 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
2699 };
2700 static int x2000_lcd_slcd_8bit_pins[] = {
2701 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2702 0x3a, 0x38, 0x3b, 0x30, 0x39,
2703 };
2704 static int x2000_pwm_pwm0_c_pins[] = { 0x40, };
2705 static int x2000_pwm_pwm0_d_pins[] = { 0x7e, };
2706 static int x2000_pwm_pwm1_c_pins[] = { 0x41, };
2707 static int x2000_pwm_pwm1_d_pins[] = { 0x7f, };
2708 static int x2000_pwm_pwm2_c_pins[] = { 0x42, };
2709 static int x2000_pwm_pwm2_e_pins[] = { 0x80, };
2710 static int x2000_pwm_pwm3_c_pins[] = { 0x43, };
2711 static int x2000_pwm_pwm3_e_pins[] = { 0x81, };
2712 static int x2000_pwm_pwm4_c_pins[] = { 0x44, };
2713 static int x2000_pwm_pwm4_e_pins[] = { 0x82, };
2714 static int x2000_pwm_pwm5_c_pins[] = { 0x45, };
2715 static int x2000_pwm_pwm5_e_pins[] = { 0x83, };
2716 static int x2000_pwm_pwm6_c_pins[] = { 0x46, };
2717 static int x2000_pwm_pwm6_e_pins[] = { 0x84, };
2718 static int x2000_pwm_pwm7_c_pins[] = { 0x47, };
2719 static int x2000_pwm_pwm7_e_pins[] = { 0x85, };
2720 static int x2000_pwm_pwm8_pins[] = { 0x48, };
2721 static int x2000_pwm_pwm9_pins[] = { 0x49, };
2722 static int x2000_pwm_pwm10_pins[] = { 0x4a, };
2723 static int x2000_pwm_pwm11_pins[] = { 0x4b, };
2724 static int x2000_pwm_pwm12_pins[] = { 0x4c, };
2725 static int x2000_pwm_pwm13_pins[] = { 0x4d, };
2726 static int x2000_pwm_pwm14_pins[] = { 0x4e, };
2727 static int x2000_pwm_pwm15_pins[] = { 0x4f, };
2728 static int x2000_mac0_rmii_pins[] = {
2729 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41,
2730 };
2731 static int x2000_mac0_rgmii_pins[] = {
2732 0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42,
2733 0x4c, 0x4d, 0x4f, 0x4e, 0x41,
2734 };
2735 static int x2000_mac1_rmii_pins[] = {
2736 0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37,
2737 };
2738 static int x2000_mac1_rgmii_pins[] = {
2739 0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28,
2740 0x33, 0x34, 0x36, 0x35, 0x37,
2741 };
2742 static int x2000_otg_pins[] = { 0x96, };
2743
2744 static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, };
2745
2746 static const struct group_desc x2000_groups[] = {
2747 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
2748 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
2749 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
2750 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
2751 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
2752 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
2753 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
2754 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
2755 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
2756 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
2757 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
2758 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
2759 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
2760 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
2761 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
2762 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
2763 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
2764 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
2765 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
2766 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
2767 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
2768 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
2769 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
2770 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
2771 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
2772 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
2773 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
2774 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
2775 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
2776 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
2777 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
2778 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
2779 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
2780 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
2781 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
2782 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
2783 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
2784 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
2785 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
2786 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
2787 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
2788 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
2789 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
2790 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
2791 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
2792 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
2793 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
2794 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
2795 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
2796 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
2797 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
2798 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
2799 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
2800 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
2801 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
2802 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
2803 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
2804 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
2805 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
2806 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
2807 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
2808 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
2809 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
2810 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
2811 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
2812 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
2813 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
2814 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
2815 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
2816 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
2817 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
2818 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
2819 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
2820 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
2821 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
2822 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
2823 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
2824 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
2825 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
2826 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
2827 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
2828 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
2829 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
2830 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
2831 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
2832 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
2833 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
2834 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
2835 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
2836 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
2837 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
2838 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
2839 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
2840 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
2841 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
2842 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
2843 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
2844 x2000_cim_8bit_funcs),
2845 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
2846 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
2847 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
2848 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
2849 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
2850 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
2851 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
2852 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
2853 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
2854 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
2855 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
2856 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
2857 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
2858 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
2859 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
2860 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
2861 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
2862 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
2863 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
2864 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
2865 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
2866 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
2867 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
2868 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),
2869 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),
2870 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),
2871 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),
2872 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),
2873 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),
2874 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),
2875 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),
2876 INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1),
2877 INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1),
2878 INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3),
2879 INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3),
2880 INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0),
2881 };
2882
2883 static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2884 static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
2885 static const char *x2000_uart2_groups[] = { "uart2-data", };
2886 static const char *x2000_uart3_groups[] = {
2887 "uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d",
2888 };
2889 static const char *x2000_uart4_groups[] = {
2890 "uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c",
2891 };
2892 static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", };
2893 static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", };
2894 static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", };
2895 static const char *x2000_uart8_groups[] = { "uart8-data", };
2896 static const char *x2000_uart9_groups[] = { "uart9-data", };
2897 static const char *x2000_sfc_groups[] = {
2898 "sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1",
2899 "sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e",
2900 };
2901 static const char *x2000_ssi0_groups[] = {
2902 "ssi0-dt-b", "ssi0-dt-d",
2903 "ssi0-dr-b", "ssi0-dr-d",
2904 "ssi0-clk-b", "ssi0-clk-d",
2905 "ssi0-ce-b", "ssi0-ce-d",
2906 };
2907 static const char *x2000_ssi1_groups[] = {
2908 "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e",
2909 "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e",
2910 "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e",
2911 "ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e",
2912 };
2913 static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", };
2914 static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2915 static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", };
2916 static const char *x2000_emc_groups[] = {
2917 "emc-8bit-data", "emc-16bit-data",
2918 "emc-addr", "emc-rd-we", "emc-wait",
2919 };
2920 static const char *x2000_cs1_groups[] = { "emc-cs1", };
2921 static const char *x2000_cs2_groups[] = { "emc-cs2", };
2922 static const char *x2000_i2c0_groups[] = { "i2c0-data", };
2923 static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", };
2924 static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", };
2925 static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", };
2926 static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", };
2927 static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", };
2928 static const char *x2000_i2s1_groups[] = {
2929 "i2s1-data-tx", "i2s1-data-rx",
2930 "i2s1-clk-tx", "i2s1-clk-rx",
2931 "i2s1-sysclk-tx", "i2s1-sysclk-rx",
2932 };
2933 static const char *x2000_i2s2_groups[] = {
2934 "i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3",
2935 "i2s2-clk-rx", "i2s2-sysclk-rx",
2936 };
2937 static const char *x2000_i2s3_groups[] = {
2938 "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3",
2939 "i2s3-clk-tx", "i2s3-sysclk-tx",
2940 };
2941 static const char *x2000_dmic_groups[] = {
2942 "dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3",
2943 };
2944 static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
2945 static const char *x2000_lcd_groups[] = {
2946 "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit",
2947 "lcd-slcd-8bit", "lcd-slcd-16bit",
2948 };
2949 static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", };
2950 static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", };
2951 static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", };
2952 static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", };
2953 static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", };
2954 static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", };
2955 static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", };
2956 static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", };
2957 static const char *x2000_pwm8_groups[] = { "pwm8", };
2958 static const char *x2000_pwm9_groups[] = { "pwm9", };
2959 static const char *x2000_pwm10_groups[] = { "pwm10", };
2960 static const char *x2000_pwm11_groups[] = { "pwm11", };
2961 static const char *x2000_pwm12_groups[] = { "pwm12", };
2962 static const char *x2000_pwm13_groups[] = { "pwm13", };
2963 static const char *x2000_pwm14_groups[] = { "pwm14", };
2964 static const char *x2000_pwm15_groups[] = { "pwm15", };
2965 static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", };
2966 static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", };
2967 static const char *x2000_otg_groups[] = { "otg-vbus", };
2968
2969 static const struct function_desc x2000_functions[] = {
2970 { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), },
2971 { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), },
2972 { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), },
2973 { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), },
2974 { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), },
2975 { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), },
2976 { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), },
2977 { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), },
2978 { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), },
2979 { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), },
2980 { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), },
2981 { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), },
2982 { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), },
2983 { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), },
2984 { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), },
2985 { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), },
2986 { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), },
2987 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
2988 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
2989 { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), },
2990 { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), },
2991 { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), },
2992 { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), },
2993 { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), },
2994 { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), },
2995 { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), },
2996 { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), },
2997 { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), },
2998 { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), },
2999 { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), },
3000 { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), },
3001 { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), },
3002 { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), },
3003 { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), },
3004 { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), },
3005 { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), },
3006 { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), },
3007 { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), },
3008 { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), },
3009 { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), },
3010 { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), },
3011 { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), },
3012 { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), },
3013 { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), },
3014 { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), },
3015 { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), },
3016 { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), },
3017 { "mac0", x2000_mac0_groups, ARRAY_SIZE(x2000_mac0_groups), },
3018 { "mac1", x2000_mac1_groups, ARRAY_SIZE(x2000_mac1_groups), },
3019 { "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), },
3020 };
3021
3022 static const struct regmap_range x2000_access_ranges[] = {
3023 regmap_reg_range(0x000, 0x500 - 4),
3024 regmap_reg_range(0x700, 0x800 - 4),
3025 };
3026
3027 /* shared with X2100 */
3028 static const struct regmap_access_table x2000_access_table = {
3029 .yes_ranges = x2000_access_ranges,
3030 .n_yes_ranges = ARRAY_SIZE(x2000_access_ranges),
3031 };
3032
3033 static const struct ingenic_chip_info x2000_chip_info = {
3034 .num_chips = 5,
3035 .reg_offset = 0x100,
3036 .version = ID_X2000,
3037 .groups = x2000_groups,
3038 .num_groups = ARRAY_SIZE(x2000_groups),
3039 .functions = x2000_functions,
3040 .num_functions = ARRAY_SIZE(x2000_functions),
3041 .pull_ups = x2000_pull_ups,
3042 .pull_downs = x2000_pull_downs,
3043 .access_table = &x2000_access_table,
3044 };
3045
3046 static const u32 x2100_pull_ups[5] = {
3047 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x0fbf003f,
3048 };
3049
3050 static const u32 x2100_pull_downs[5] = {
3051 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x0fbf003f,
3052 };
3053
3054 static int x2100_mac_pins[] = {
3055 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4f, 0x41,
3056 };
3057
3058 static const struct group_desc x2100_groups[] = {
3059 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
3060 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
3061 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
3062 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
3063 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
3064 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
3065 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
3066 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
3067 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
3068 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
3069 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
3070 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
3071 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
3072 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
3073 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
3074 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
3075 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
3076 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
3077 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
3078 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
3079 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
3080 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
3081 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
3082 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
3083 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
3084 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
3085 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
3086 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
3087 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
3088 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
3089 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
3090 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
3091 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
3092 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
3093 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
3094 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
3095 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
3096 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
3097 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
3098 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
3099 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
3100 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
3101 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
3102 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
3103 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
3104 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
3105 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
3106 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
3107 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
3108 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
3109 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
3110 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
3111 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
3112 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
3113 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
3114 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
3115 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
3116 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
3117 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
3118 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
3119 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
3120 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
3121 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
3122 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
3123 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
3124 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
3125 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
3126 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
3127 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
3128 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
3129 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
3130 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
3131 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
3132 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
3133 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
3134 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
3135 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
3136 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
3137 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
3138 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
3139 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
3140 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
3141 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
3142 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
3143 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
3144 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
3145 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
3146 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
3147 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
3148 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
3149 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
3150 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
3151 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
3152 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
3153 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
3154 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
3155 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
3156 x2000_cim_8bit_funcs),
3157 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
3158 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
3159 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
3160 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
3161 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
3162 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
3163 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
3164 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
3165 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
3166 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
3167 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
3168 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
3169 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
3170 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
3171 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
3172 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
3173 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
3174 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
3175 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
3176 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
3177 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
3178 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
3179 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
3180 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),
3181 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),
3182 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),
3183 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),
3184 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),
3185 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),
3186 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),
3187 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),
3188 INGENIC_PIN_GROUP("mac", x2100_mac, 1),
3189 };
3190
3191 static const char *x2100_mac_groups[] = { "mac", };
3192
3193 static const struct function_desc x2100_functions[] = {
3194 { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), },
3195 { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), },
3196 { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), },
3197 { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), },
3198 { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), },
3199 { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), },
3200 { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), },
3201 { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), },
3202 { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), },
3203 { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), },
3204 { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), },
3205 { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), },
3206 { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), },
3207 { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), },
3208 { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), },
3209 { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), },
3210 { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), },
3211 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
3212 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
3213 { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), },
3214 { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), },
3215 { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), },
3216 { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), },
3217 { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), },
3218 { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), },
3219 { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), },
3220 { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), },
3221 { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), },
3222 { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), },
3223 { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), },
3224 { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), },
3225 { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), },
3226 { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), },
3227 { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), },
3228 { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), },
3229 { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), },
3230 { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), },
3231 { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), },
3232 { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), },
3233 { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), },
3234 { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), },
3235 { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), },
3236 { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), },
3237 { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), },
3238 { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), },
3239 { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), },
3240 { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), },
3241 { "mac", x2100_mac_groups, ARRAY_SIZE(x2100_mac_groups), },
3242 };
3243
3244 static const struct ingenic_chip_info x2100_chip_info = {
3245 .num_chips = 5,
3246 .reg_offset = 0x100,
3247 .version = ID_X2100,
3248 .groups = x2100_groups,
3249 .num_groups = ARRAY_SIZE(x2100_groups),
3250 .functions = x2100_functions,
3251 .num_functions = ARRAY_SIZE(x2100_functions),
3252 .pull_ups = x2100_pull_ups,
3253 .pull_downs = x2100_pull_downs,
3254 .access_table = &x2000_access_table,
3255 };
3256
ingenic_gpio_read_reg(struct ingenic_gpio_chip * jzgc,u8 reg)3257 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
3258 {
3259 unsigned int val;
3260
3261 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
3262
3263 return (u32) val;
3264 }
3265
ingenic_gpio_set_bit(struct ingenic_gpio_chip * jzgc,u8 reg,u8 offset,bool set)3266 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
3267 u8 reg, u8 offset, bool set)
3268 {
3269 if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
3270 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg,
3271 BIT(offset), set ? BIT(offset) : 0);
3272 return;
3273 }
3274
3275 if (set)
3276 reg = REG_SET(reg);
3277 else
3278 reg = REG_CLEAR(reg);
3279
3280 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
3281 }
3282
ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip * jzgc,u8 reg,u8 offset,bool set)3283 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
3284 u8 reg, u8 offset, bool set)
3285 {
3286 if (set)
3287 reg = REG_SET(reg);
3288 else
3289 reg = REG_CLEAR(reg);
3290
3291 regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
3292 jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
3293 }
3294
ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip * jzgc)3295 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
3296 {
3297 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
3298 jzgc->jzpc->info->reg_offset),
3299 jzgc->gc.base / PINS_PER_GPIO_CHIP);
3300 }
3301
jz4730_gpio_set_bits(struct ingenic_gpio_chip * jzgc,u8 reg_upper,u8 reg_lower,u8 offset,u8 value)3302 static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc,
3303 u8 reg_upper, u8 reg_lower, u8 offset, u8 value)
3304 {
3305 /*
3306 * JZ4730 function and IRQ registers support two-bits-per-pin
3307 * definitions, split into two groups of 16.
3308 */
3309 u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;
3310 unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG;
3311 unsigned int mask = GENMASK(1, 0) << idx * 2;
3312
3313 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2));
3314 }
3315
ingenic_gpio_get_value(struct ingenic_gpio_chip * jzgc,u8 offset)3316 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
3317 u8 offset)
3318 {
3319 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
3320
3321 return !!(val & BIT(offset));
3322 }
3323
ingenic_gpio_set_value(struct ingenic_gpio_chip * jzgc,u8 offset,int value)3324 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
3325 u8 offset, int value)
3326 {
3327 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3328 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
3329 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3330 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
3331 else
3332 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value);
3333 }
3334
irq_set_type(struct ingenic_gpio_chip * jzgc,u8 offset,unsigned int type)3335 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
3336 u8 offset, unsigned int type)
3337 {
3338 u8 reg1, reg2;
3339 bool val1, val2, val3;
3340
3341 switch (type) {
3342 case IRQ_TYPE_EDGE_BOTH:
3343 val1 = val2 = false;
3344 val3 = true;
3345 break;
3346 case IRQ_TYPE_EDGE_RISING:
3347 val1 = val2 = true;
3348 val3 = false;
3349 break;
3350 case IRQ_TYPE_EDGE_FALLING:
3351 val1 = val3 = false;
3352 val2 = true;
3353 break;
3354 case IRQ_TYPE_LEVEL_HIGH:
3355 val1 = true;
3356 val2 = val3 = false;
3357 break;
3358 case IRQ_TYPE_LEVEL_LOW:
3359 default:
3360 val1 = val2 = val3 = false;
3361 break;
3362 }
3363
3364 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) {
3365 reg1 = JZ4770_GPIO_PAT1;
3366 reg2 = JZ4770_GPIO_PAT0;
3367 } else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
3368 reg1 = JZ4740_GPIO_TRIG;
3369 reg2 = JZ4740_GPIO_DIR;
3370 } else {
3371 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false);
3372 jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR,
3373 JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1);
3374 return;
3375 }
3376
3377 if (is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3378 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3379 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3380 ingenic_gpio_shadow_set_bit_load(jzgc);
3381 ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3);
3382 } else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) {
3383 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3384 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3385 ingenic_gpio_shadow_set_bit_load(jzgc);
3386 } else {
3387 ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
3388 ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
3389 }
3390 }
3391
ingenic_gpio_irq_mask(struct irq_data * irqd)3392 static void ingenic_gpio_irq_mask(struct irq_data *irqd)
3393 {
3394 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3395 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3396 irq_hw_number_t irq = irqd_to_hwirq(irqd);
3397
3398 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3399 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true);
3400 else
3401 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true);
3402 }
3403
ingenic_gpio_irq_unmask(struct irq_data * irqd)3404 static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
3405 {
3406 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3407 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3408 irq_hw_number_t irq = irqd_to_hwirq(irqd);
3409
3410 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3411 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false);
3412 else
3413 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false);
3414 }
3415
ingenic_gpio_irq_enable(struct irq_data * irqd)3416 static void ingenic_gpio_irq_enable(struct irq_data *irqd)
3417 {
3418 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3419 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3420 irq_hw_number_t irq = irqd_to_hwirq(irqd);
3421
3422 gpiochip_enable_irq(gc, irq);
3423
3424 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3425 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
3426 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3427 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
3428 else
3429 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true);
3430
3431 ingenic_gpio_irq_unmask(irqd);
3432 }
3433
ingenic_gpio_irq_disable(struct irq_data * irqd)3434 static void ingenic_gpio_irq_disable(struct irq_data *irqd)
3435 {
3436 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3437 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3438 irq_hw_number_t irq = irqd_to_hwirq(irqd);
3439
3440 ingenic_gpio_irq_mask(irqd);
3441
3442 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3443 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
3444 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3445 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
3446 else
3447 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false);
3448
3449 gpiochip_disable_irq(gc, irq);
3450 }
3451
ingenic_gpio_irq_ack(struct irq_data * irqd)3452 static void ingenic_gpio_irq_ack(struct irq_data *irqd)
3453 {
3454 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3455 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3456 irq_hw_number_t irq = irqd_to_hwirq(irqd);
3457 bool high;
3458
3459 if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) &&
3460 !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3461 /*
3462 * Switch to an interrupt for the opposite edge to the one that
3463 * triggered the interrupt being ACKed.
3464 */
3465 high = ingenic_gpio_get_value(jzgc, irq);
3466 if (high)
3467 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
3468 else
3469 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
3470 }
3471
3472 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3473 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
3474 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3475 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
3476 else
3477 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false);
3478 }
3479
ingenic_gpio_irq_set_type(struct irq_data * irqd,unsigned int type)3480 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
3481 {
3482 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3483 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3484 irq_hw_number_t irq = irqd_to_hwirq(irqd);
3485
3486 switch (type) {
3487 case IRQ_TYPE_EDGE_BOTH:
3488 case IRQ_TYPE_EDGE_RISING:
3489 case IRQ_TYPE_EDGE_FALLING:
3490 irq_set_handler_locked(irqd, handle_edge_irq);
3491 break;
3492 case IRQ_TYPE_LEVEL_HIGH:
3493 case IRQ_TYPE_LEVEL_LOW:
3494 irq_set_handler_locked(irqd, handle_level_irq);
3495 break;
3496 default:
3497 irq_set_handler_locked(irqd, handle_bad_irq);
3498 }
3499
3500 if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
3501 /*
3502 * The hardware does not support interrupts on both edges. The
3503 * best we can do is to set up a single-edge interrupt and then
3504 * switch to the opposing edge when ACKing the interrupt.
3505 */
3506 bool high = ingenic_gpio_get_value(jzgc, irq);
3507
3508 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH;
3509 }
3510
3511 irq_set_type(jzgc, irq, type);
3512 return 0;
3513 }
3514
ingenic_gpio_irq_set_wake(struct irq_data * irqd,unsigned int on)3515 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
3516 {
3517 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3518 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3519
3520 return irq_set_irq_wake(jzgc->irq, on);
3521 }
3522
ingenic_gpio_irq_handler(struct irq_desc * desc)3523 static void ingenic_gpio_irq_handler(struct irq_desc *desc)
3524 {
3525 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
3526 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3527 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
3528 unsigned long flag, i;
3529
3530 chained_irq_enter(irq_chip, desc);
3531
3532 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
3533 flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
3534 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
3535 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
3536 else
3537 flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);
3538
3539 for_each_set_bit(i, &flag, 32)
3540 generic_handle_domain_irq(gc->irq.domain, i);
3541 chained_irq_exit(irq_chip, desc);
3542 }
3543
ingenic_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)3544 static void ingenic_gpio_set(struct gpio_chip *gc,
3545 unsigned int offset, int value)
3546 {
3547 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3548
3549 ingenic_gpio_set_value(jzgc, offset, value);
3550 }
3551
ingenic_gpio_get(struct gpio_chip * gc,unsigned int offset)3552 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
3553 {
3554 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3555
3556 return (int) ingenic_gpio_get_value(jzgc, offset);
3557 }
3558
ingenic_gpio_direction_input(struct gpio_chip * gc,unsigned int offset)3559 static int ingenic_gpio_direction_input(struct gpio_chip *gc,
3560 unsigned int offset)
3561 {
3562 return pinctrl_gpio_direction_input(gc->base + offset);
3563 }
3564
ingenic_gpio_direction_output(struct gpio_chip * gc,unsigned int offset,int value)3565 static int ingenic_gpio_direction_output(struct gpio_chip *gc,
3566 unsigned int offset, int value)
3567 {
3568 ingenic_gpio_set(gc, offset, value);
3569 return pinctrl_gpio_direction_output(gc->base + offset);
3570 }
3571
ingenic_config_pin(struct ingenic_pinctrl * jzpc,unsigned int pin,unsigned int reg,bool set)3572 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
3573 unsigned int pin, unsigned int reg, bool set)
3574 {
3575 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3576 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3577
3578 if (set) {
3579 if (is_soc_or_above(jzpc, ID_JZ4740))
3580 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3581 REG_SET(reg), BIT(idx));
3582 else
3583 regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset +
3584 reg, BIT(idx));
3585 } else {
3586 if (is_soc_or_above(jzpc, ID_JZ4740))
3587 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3588 REG_CLEAR(reg), BIT(idx));
3589 else
3590 regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset +
3591 reg, BIT(idx));
3592 }
3593 }
3594
ingenic_shadow_config_pin(struct ingenic_pinctrl * jzpc,unsigned int pin,u8 reg,bool set)3595 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
3596 unsigned int pin, u8 reg, bool set)
3597 {
3598 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3599
3600 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +
3601 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
3602 }
3603
ingenic_shadow_config_pin_load(struct ingenic_pinctrl * jzpc,unsigned int pin)3604 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
3605 unsigned int pin)
3606 {
3607 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),
3608 pin / PINS_PER_GPIO_CHIP);
3609 }
3610
jz4730_config_pin_function(struct ingenic_pinctrl * jzpc,unsigned int pin,u8 reg_upper,u8 reg_lower,u8 value)3611 static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc,
3612 unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value)
3613 {
3614 /*
3615 * JZ4730 function and IRQ registers support two-bits-per-pin
3616 * definitions, split into two groups of 16.
3617 */
3618 unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG;
3619 unsigned int mask = GENMASK(1, 0) << idx * 2;
3620 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3621 u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;
3622
3623 regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg,
3624 mask, value << (idx * 2));
3625 }
3626
ingenic_get_pin_config(struct ingenic_pinctrl * jzpc,unsigned int pin,unsigned int reg)3627 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
3628 unsigned int pin, unsigned int reg)
3629 {
3630 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3631 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3632 unsigned int val;
3633
3634 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);
3635
3636 return val & BIT(idx);
3637 }
3638
ingenic_gpio_get_direction(struct gpio_chip * gc,unsigned int offset)3639 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
3640 {
3641 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3642 struct ingenic_pinctrl *jzpc = jzgc->jzpc;
3643 unsigned int pin = gc->base + offset;
3644
3645 if (is_soc_or_above(jzpc, ID_JZ4770)) {
3646 if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) ||
3647 ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1))
3648 return GPIO_LINE_DIRECTION_IN;
3649 return GPIO_LINE_DIRECTION_OUT;
3650 } else if (!is_soc_or_above(jzpc, ID_JZ4740)) {
3651 if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR))
3652 return GPIO_LINE_DIRECTION_IN;
3653 return GPIO_LINE_DIRECTION_OUT;
3654 }
3655
3656 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
3657 return GPIO_LINE_DIRECTION_IN;
3658
3659 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR))
3660 return GPIO_LINE_DIRECTION_OUT;
3661
3662 return GPIO_LINE_DIRECTION_IN;
3663 }
3664
3665 static const struct pinctrl_ops ingenic_pctlops = {
3666 .get_groups_count = pinctrl_generic_get_group_count,
3667 .get_group_name = pinctrl_generic_get_group_name,
3668 .get_group_pins = pinctrl_generic_get_group_pins,
3669 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
3670 .dt_free_map = pinconf_generic_dt_free_map,
3671 };
3672
ingenic_gpio_irq_request(struct irq_data * data)3673 static int ingenic_gpio_irq_request(struct irq_data *data)
3674 {
3675 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
3676 irq_hw_number_t irq = irqd_to_hwirq(data);
3677 int ret;
3678
3679 ret = ingenic_gpio_direction_input(gpio_chip, irq);
3680 if (ret)
3681 return ret;
3682
3683 return gpiochip_reqres_irq(gpio_chip, irq);
3684 }
3685
ingenic_gpio_irq_release(struct irq_data * data)3686 static void ingenic_gpio_irq_release(struct irq_data *data)
3687 {
3688 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
3689 irq_hw_number_t irq = irqd_to_hwirq(data);
3690
3691 return gpiochip_relres_irq(gpio_chip, irq);
3692 }
3693
ingenic_gpio_irq_print_chip(struct irq_data * data,struct seq_file * p)3694 static void ingenic_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
3695 {
3696 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
3697
3698 seq_printf(p, "%s", gpio_chip->label);
3699 }
3700
3701 static const struct irq_chip ingenic_gpio_irqchip = {
3702 .irq_enable = ingenic_gpio_irq_enable,
3703 .irq_disable = ingenic_gpio_irq_disable,
3704 .irq_unmask = ingenic_gpio_irq_unmask,
3705 .irq_mask = ingenic_gpio_irq_mask,
3706 .irq_ack = ingenic_gpio_irq_ack,
3707 .irq_set_type = ingenic_gpio_irq_set_type,
3708 .irq_set_wake = ingenic_gpio_irq_set_wake,
3709 .irq_request_resources = ingenic_gpio_irq_request,
3710 .irq_release_resources = ingenic_gpio_irq_release,
3711 .irq_print_chip = ingenic_gpio_irq_print_chip,
3712 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
3713 };
3714
ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl * jzpc,int pin,int func)3715 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
3716 int pin, int func)
3717 {
3718 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3719 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3720
3721 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
3722 'A' + offt, idx, func);
3723
3724 if (is_soc_or_above(jzpc, ID_X1000)) {
3725 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3726 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
3727 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
3728 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
3729 ingenic_shadow_config_pin_load(jzpc, pin);
3730 } else if (is_soc_or_above(jzpc, ID_JZ4770)) {
3731 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3732 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
3733 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
3734 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
3735 } else if (is_soc_or_above(jzpc, ID_JZ4740)) {
3736 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
3737 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
3738 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1);
3739 } else {
3740 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);
3741 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func);
3742 }
3743
3744 return 0;
3745 }
3746
ingenic_pinmux_set_mux(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)3747 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
3748 unsigned int selector, unsigned int group)
3749 {
3750 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
3751 struct function_desc *func;
3752 struct group_desc *grp;
3753 unsigned int i;
3754 uintptr_t mode;
3755 u8 *pin_modes;
3756
3757 func = pinmux_generic_get_function(pctldev, selector);
3758 if (!func)
3759 return -EINVAL;
3760
3761 grp = pinctrl_generic_get_group(pctldev, group);
3762 if (!grp)
3763 return -EINVAL;
3764
3765 dev_dbg(pctldev->dev, "enable function %s group %s\n",
3766 func->name, grp->name);
3767
3768 mode = (uintptr_t)grp->data;
3769 if (mode <= 3) {
3770 for (i = 0; i < grp->num_pins; i++)
3771 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode);
3772 } else {
3773 pin_modes = grp->data;
3774
3775 for (i = 0; i < grp->num_pins; i++)
3776 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
3777 }
3778
3779 return 0;
3780 }
3781
ingenic_pinmux_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin,bool input)3782 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
3783 struct pinctrl_gpio_range *range,
3784 unsigned int pin, bool input)
3785 {
3786 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
3787 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3788 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3789
3790 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
3791 'A' + offt, idx, input ? "in" : "out");
3792
3793 if (is_soc_or_above(jzpc, ID_X1000)) {
3794 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3795 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
3796 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
3797 ingenic_shadow_config_pin_load(jzpc, pin);
3798 } else if (is_soc_or_above(jzpc, ID_JZ4770)) {
3799 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3800 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
3801 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
3802 } else if (is_soc_or_above(jzpc, ID_JZ4740)) {
3803 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
3804 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
3805 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
3806 } else {
3807 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);
3808 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input);
3809 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0);
3810 }
3811
3812 return 0;
3813 }
3814
3815 static const struct pinmux_ops ingenic_pmxops = {
3816 .get_functions_count = pinmux_generic_get_function_count,
3817 .get_function_name = pinmux_generic_get_function_name,
3818 .get_function_groups = pinmux_generic_get_function_groups,
3819 .set_mux = ingenic_pinmux_set_mux,
3820 .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
3821 };
3822
ingenic_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)3823 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
3824 unsigned int pin, unsigned long *config)
3825 {
3826 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
3827 enum pin_config_param param = pinconf_to_config_param(*config);
3828 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3829 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3830 unsigned int arg = 1;
3831 unsigned int bias, reg;
3832 bool pull, pullup, pulldown;
3833
3834 if (is_soc_or_above(jzpc, ID_X2000)) {
3835 pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
3836 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&
3837 (jzpc->info->pull_ups[offt] & BIT(idx));
3838 pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&
3839 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
3840 (jzpc->info->pull_downs[offt] & BIT(idx));
3841
3842 } else if (is_soc_or_above(jzpc, ID_X1830)) {
3843 unsigned int half = PINS_PER_GPIO_CHIP / 2;
3844 unsigned int idxh = (pin % half) * 2;
3845
3846 if (idx < half)
3847 regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
3848 X1830_GPIO_PEL, &bias);
3849 else
3850 regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
3851 X1830_GPIO_PEH, &bias);
3852
3853 bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN);
3854
3855 pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx));
3856 pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx));
3857
3858 } else {
3859 if (is_soc_or_above(jzpc, ID_JZ4770))
3860 pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
3861 else if (is_soc_or_above(jzpc, ID_JZ4740))
3862 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
3863 else
3864 pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR);
3865
3866 pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx));
3867 pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx));
3868 }
3869
3870 switch (param) {
3871 case PIN_CONFIG_BIAS_DISABLE:
3872 if (pullup || pulldown)
3873 return -EINVAL;
3874
3875 break;
3876
3877 case PIN_CONFIG_BIAS_PULL_UP:
3878 if (!pullup)
3879 return -EINVAL;
3880
3881 break;
3882
3883 case PIN_CONFIG_BIAS_PULL_DOWN:
3884 if (!pulldown)
3885 return -EINVAL;
3886
3887 break;
3888
3889 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3890 if (is_soc_or_above(jzpc, ID_X2000))
3891 reg = X2000_GPIO_SMT;
3892 else if (is_soc_or_above(jzpc, ID_X1830))
3893 reg = X1830_GPIO_SMT;
3894 else
3895 return -EINVAL;
3896
3897 arg = !!ingenic_get_pin_config(jzpc, pin, reg);
3898 break;
3899
3900 case PIN_CONFIG_SLEW_RATE:
3901 if (is_soc_or_above(jzpc, ID_X2000))
3902 reg = X2000_GPIO_SR;
3903 else if (is_soc_or_above(jzpc, ID_X1830))
3904 reg = X1830_GPIO_SR;
3905 else
3906 return -EINVAL;
3907
3908 arg = !!ingenic_get_pin_config(jzpc, pin, reg);
3909 break;
3910
3911 default:
3912 return -ENOTSUPP;
3913 }
3914
3915 *config = pinconf_to_config_packed(param, arg);
3916 return 0;
3917 }
3918
ingenic_set_bias(struct ingenic_pinctrl * jzpc,unsigned int pin,unsigned int bias)3919 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
3920 unsigned int pin, unsigned int bias)
3921 {
3922 if (is_soc_or_above(jzpc, ID_X2000)) {
3923 switch (bias) {
3924 case GPIO_PULL_UP:
3925 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
3926 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true);
3927 break;
3928
3929 case GPIO_PULL_DOWN:
3930 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
3931 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true);
3932 break;
3933
3934 case GPIO_PULL_DIS:
3935 default:
3936 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
3937 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
3938 }
3939
3940 } else if (is_soc_or_above(jzpc, ID_X1830)) {
3941 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3942 unsigned int half = PINS_PER_GPIO_CHIP / 2;
3943 unsigned int idxh = (pin % half) * 2;
3944 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3945
3946 if (idx < half) {
3947 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3948 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);
3949 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3950 REG_SET(X1830_GPIO_PEL), bias << idxh);
3951 } else {
3952 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3953 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);
3954 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3955 REG_SET(X1830_GPIO_PEH), bias << idxh);
3956 }
3957
3958 } else if (is_soc_or_above(jzpc, ID_JZ4770)) {
3959 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias);
3960 } else if (is_soc_or_above(jzpc, ID_JZ4740)) {
3961 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
3962 } else {
3963 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias);
3964 }
3965 }
3966
ingenic_set_schmitt_trigger(struct ingenic_pinctrl * jzpc,unsigned int pin,bool enable)3967 static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc,
3968 unsigned int pin, bool enable)
3969 {
3970 if (is_soc_or_above(jzpc, ID_X2000))
3971 ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable);
3972 else
3973 ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable);
3974 }
3975
ingenic_set_output_level(struct ingenic_pinctrl * jzpc,unsigned int pin,bool high)3976 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
3977 unsigned int pin, bool high)
3978 {
3979 if (is_soc_or_above(jzpc, ID_JZ4770))
3980 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high);
3981 else if (is_soc_or_above(jzpc, ID_JZ4740))
3982 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
3983 else
3984 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high);
3985 }
3986
ingenic_set_slew_rate(struct ingenic_pinctrl * jzpc,unsigned int pin,unsigned int slew)3987 static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc,
3988 unsigned int pin, unsigned int slew)
3989 {
3990 if (is_soc_or_above(jzpc, ID_X2000))
3991 ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew);
3992 else
3993 ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew);
3994 }
3995
ingenic_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)3996 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
3997 unsigned long *configs, unsigned int num_configs)
3998 {
3999 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
4000 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
4001 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
4002 unsigned int cfg, arg;
4003 int ret;
4004
4005 for (cfg = 0; cfg < num_configs; cfg++) {
4006 switch (pinconf_to_config_param(configs[cfg])) {
4007 case PIN_CONFIG_BIAS_DISABLE:
4008 case PIN_CONFIG_BIAS_PULL_UP:
4009 case PIN_CONFIG_BIAS_PULL_DOWN:
4010 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
4011 case PIN_CONFIG_OUTPUT:
4012 case PIN_CONFIG_SLEW_RATE:
4013 continue;
4014 default:
4015 return -ENOTSUPP;
4016 }
4017 }
4018
4019 for (cfg = 0; cfg < num_configs; cfg++) {
4020 arg = pinconf_to_config_argument(configs[cfg]);
4021
4022 switch (pinconf_to_config_param(configs[cfg])) {
4023 case PIN_CONFIG_BIAS_DISABLE:
4024 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
4025 'A' + offt, idx);
4026 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);
4027 break;
4028
4029 case PIN_CONFIG_BIAS_PULL_UP:
4030 if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
4031 return -EINVAL;
4032 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
4033 'A' + offt, idx);
4034 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);
4035 break;
4036
4037 case PIN_CONFIG_BIAS_PULL_DOWN:
4038 if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
4039 return -EINVAL;
4040 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
4041 'A' + offt, idx);
4042 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);
4043 break;
4044
4045 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
4046 if (!is_soc_or_above(jzpc, ID_X1830))
4047 return -EINVAL;
4048
4049 ingenic_set_schmitt_trigger(jzpc, pin, arg);
4050 break;
4051
4052 case PIN_CONFIG_OUTPUT:
4053 ret = pinctrl_gpio_direction_output(pin);
4054 if (ret)
4055 return ret;
4056
4057 ingenic_set_output_level(jzpc, pin, arg);
4058 break;
4059
4060 case PIN_CONFIG_SLEW_RATE:
4061 if (!is_soc_or_above(jzpc, ID_X1830))
4062 return -EINVAL;
4063
4064 ingenic_set_slew_rate(jzpc, pin, arg);
4065 break;
4066
4067 default:
4068 /* unreachable */
4069 break;
4070 }
4071 }
4072
4073 return 0;
4074 }
4075
ingenic_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)4076 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
4077 unsigned int group, unsigned long *config)
4078 {
4079 const unsigned int *pins;
4080 unsigned int i, npins, old = 0;
4081 int ret;
4082
4083 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
4084 if (ret)
4085 return ret;
4086
4087 for (i = 0; i < npins; i++) {
4088 if (ingenic_pinconf_get(pctldev, pins[i], config))
4089 return -ENOTSUPP;
4090
4091 /* configs do not match between two pins */
4092 if (i && (old != *config))
4093 return -ENOTSUPP;
4094
4095 old = *config;
4096 }
4097
4098 return 0;
4099 }
4100
ingenic_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int num_configs)4101 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
4102 unsigned int group, unsigned long *configs,
4103 unsigned int num_configs)
4104 {
4105 const unsigned int *pins;
4106 unsigned int i, npins;
4107 int ret;
4108
4109 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
4110 if (ret)
4111 return ret;
4112
4113 for (i = 0; i < npins; i++) {
4114 ret = ingenic_pinconf_set(pctldev,
4115 pins[i], configs, num_configs);
4116 if (ret)
4117 return ret;
4118 }
4119
4120 return 0;
4121 }
4122
4123 static const struct pinconf_ops ingenic_confops = {
4124 .is_generic = true,
4125 .pin_config_get = ingenic_pinconf_get,
4126 .pin_config_set = ingenic_pinconf_set,
4127 .pin_config_group_get = ingenic_pinconf_group_get,
4128 .pin_config_group_set = ingenic_pinconf_group_set,
4129 };
4130
4131 static const struct regmap_config ingenic_pinctrl_regmap_config = {
4132 .reg_bits = 32,
4133 .val_bits = 32,
4134 .reg_stride = 4,
4135 };
4136
4137 static const struct of_device_id ingenic_gpio_of_matches[] __initconst = {
4138 { .compatible = "ingenic,jz4730-gpio" },
4139 { .compatible = "ingenic,jz4740-gpio" },
4140 { .compatible = "ingenic,jz4725b-gpio" },
4141 { .compatible = "ingenic,jz4750-gpio" },
4142 { .compatible = "ingenic,jz4755-gpio" },
4143 { .compatible = "ingenic,jz4760-gpio" },
4144 { .compatible = "ingenic,jz4770-gpio" },
4145 { .compatible = "ingenic,jz4775-gpio" },
4146 { .compatible = "ingenic,jz4780-gpio" },
4147 { .compatible = "ingenic,x1000-gpio" },
4148 { .compatible = "ingenic,x1830-gpio" },
4149 { .compatible = "ingenic,x2000-gpio" },
4150 { .compatible = "ingenic,x2100-gpio" },
4151 {},
4152 };
4153
ingenic_gpio_probe(struct ingenic_pinctrl * jzpc,struct fwnode_handle * fwnode)4154 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
4155 struct fwnode_handle *fwnode)
4156 {
4157 struct ingenic_gpio_chip *jzgc;
4158 struct device *dev = jzpc->dev;
4159 struct gpio_irq_chip *girq;
4160 unsigned int bank;
4161 int err;
4162
4163 err = fwnode_property_read_u32(fwnode, "reg", &bank);
4164 if (err) {
4165 dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
4166 return err;
4167 }
4168
4169 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
4170 if (!jzgc)
4171 return -ENOMEM;
4172
4173 jzgc->jzpc = jzpc;
4174 jzgc->reg_base = bank * jzpc->info->reg_offset;
4175
4176 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
4177 if (!jzgc->gc.label)
4178 return -ENOMEM;
4179
4180 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
4181 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
4182 * <linux/gpio/consumer.h> INSTEAD.
4183 */
4184 jzgc->gc.base = bank * 32;
4185
4186 jzgc->gc.ngpio = 32;
4187 jzgc->gc.parent = dev;
4188 jzgc->gc.fwnode = fwnode;
4189 jzgc->gc.owner = THIS_MODULE;
4190
4191 jzgc->gc.set = ingenic_gpio_set;
4192 jzgc->gc.get = ingenic_gpio_get;
4193 jzgc->gc.direction_input = ingenic_gpio_direction_input;
4194 jzgc->gc.direction_output = ingenic_gpio_direction_output;
4195 jzgc->gc.get_direction = ingenic_gpio_get_direction;
4196 jzgc->gc.request = gpiochip_generic_request;
4197 jzgc->gc.free = gpiochip_generic_free;
4198
4199 err = fwnode_irq_get(fwnode, 0);
4200 if (err < 0)
4201 return err;
4202 if (!err)
4203 return -EINVAL;
4204 jzgc->irq = err;
4205
4206 girq = &jzgc->gc.irq;
4207 gpio_irq_chip_set_chip(girq, &ingenic_gpio_irqchip);
4208 girq->parent_handler = ingenic_gpio_irq_handler;
4209 girq->num_parents = 1;
4210 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
4211 GFP_KERNEL);
4212 if (!girq->parents)
4213 return -ENOMEM;
4214
4215 girq->parents[0] = jzgc->irq;
4216 girq->default_type = IRQ_TYPE_NONE;
4217 girq->handler = handle_level_irq;
4218
4219 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
4220 if (err)
4221 return err;
4222
4223 return 0;
4224 }
4225
ingenic_pinctrl_probe(struct platform_device * pdev)4226 static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
4227 {
4228 struct device *dev = &pdev->dev;
4229 struct ingenic_pinctrl *jzpc;
4230 struct pinctrl_desc *pctl_desc;
4231 void __iomem *base;
4232 const struct ingenic_chip_info *chip_info;
4233 struct regmap_config regmap_config;
4234 struct fwnode_handle *fwnode;
4235 unsigned int i;
4236 int err;
4237
4238 chip_info = device_get_match_data(dev);
4239 if (!chip_info) {
4240 dev_err(dev, "Unsupported SoC\n");
4241 return -EINVAL;
4242 }
4243
4244 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
4245 if (!jzpc)
4246 return -ENOMEM;
4247
4248 base = devm_platform_ioremap_resource(pdev, 0);
4249 if (IS_ERR(base))
4250 return PTR_ERR(base);
4251
4252 regmap_config = ingenic_pinctrl_regmap_config;
4253 if (chip_info->access_table) {
4254 regmap_config.rd_table = chip_info->access_table;
4255 regmap_config.wr_table = chip_info->access_table;
4256 } else {
4257 regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4;
4258 }
4259
4260 jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config);
4261 if (IS_ERR(jzpc->map)) {
4262 dev_err(dev, "Failed to create regmap\n");
4263 return PTR_ERR(jzpc->map);
4264 }
4265
4266 jzpc->dev = dev;
4267 jzpc->info = chip_info;
4268
4269 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
4270 if (!pctl_desc)
4271 return -ENOMEM;
4272
4273 /* fill in pinctrl_desc structure */
4274 pctl_desc->name = dev_name(dev);
4275 pctl_desc->owner = THIS_MODULE;
4276 pctl_desc->pctlops = &ingenic_pctlops;
4277 pctl_desc->pmxops = &ingenic_pmxops;
4278 pctl_desc->confops = &ingenic_confops;
4279 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
4280 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
4281 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
4282 if (!jzpc->pdesc)
4283 return -ENOMEM;
4284
4285 for (i = 0; i < pctl_desc->npins; i++) {
4286 jzpc->pdesc[i].number = i;
4287 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
4288 'A' + (i / PINS_PER_GPIO_CHIP),
4289 i % PINS_PER_GPIO_CHIP);
4290 }
4291
4292 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
4293 if (IS_ERR(jzpc->pctl)) {
4294 dev_err(dev, "Failed to register pinctrl\n");
4295 return PTR_ERR(jzpc->pctl);
4296 }
4297
4298 for (i = 0; i < chip_info->num_groups; i++) {
4299 const struct group_desc *group = &chip_info->groups[i];
4300
4301 err = pinctrl_generic_add_group(jzpc->pctl, group->name,
4302 group->pins, group->num_pins, group->data);
4303 if (err < 0) {
4304 dev_err(dev, "Failed to register group %s\n",
4305 group->name);
4306 return err;
4307 }
4308 }
4309
4310 for (i = 0; i < chip_info->num_functions; i++) {
4311 const struct function_desc *func = &chip_info->functions[i];
4312
4313 err = pinmux_generic_add_function(jzpc->pctl, func->name,
4314 func->group_names, func->num_group_names,
4315 func->data);
4316 if (err < 0) {
4317 dev_err(dev, "Failed to register function %s\n",
4318 func->name);
4319 return err;
4320 }
4321 }
4322
4323 dev_set_drvdata(dev, jzpc->map);
4324
4325 device_for_each_child_node(dev, fwnode) {
4326 if (of_match_node(ingenic_gpio_of_matches, to_of_node(fwnode))) {
4327 err = ingenic_gpio_probe(jzpc, fwnode);
4328 if (err) {
4329 fwnode_handle_put(fwnode);
4330 return err;
4331 }
4332 }
4333 }
4334
4335 return 0;
4336 }
4337
4338 #define IF_ENABLED(cfg, ptr) PTR_IF(IS_ENABLED(cfg), (ptr))
4339
4340 static const struct of_device_id ingenic_pinctrl_of_matches[] = {
4341 {
4342 .compatible = "ingenic,jz4730-pinctrl",
4343 .data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info)
4344 },
4345 {
4346 .compatible = "ingenic,jz4740-pinctrl",
4347 .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info)
4348 },
4349 {
4350 .compatible = "ingenic,jz4725b-pinctrl",
4351 .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info)
4352 },
4353 {
4354 .compatible = "ingenic,jz4750-pinctrl",
4355 .data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info)
4356 },
4357 {
4358 .compatible = "ingenic,jz4755-pinctrl",
4359 .data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info)
4360 },
4361 {
4362 .compatible = "ingenic,jz4760-pinctrl",
4363 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
4364 },
4365 {
4366 .compatible = "ingenic,jz4760b-pinctrl",
4367 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
4368 },
4369 {
4370 .compatible = "ingenic,jz4770-pinctrl",
4371 .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info)
4372 },
4373 {
4374 .compatible = "ingenic,jz4775-pinctrl",
4375 .data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info)
4376 },
4377 {
4378 .compatible = "ingenic,jz4780-pinctrl",
4379 .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info)
4380 },
4381 {
4382 .compatible = "ingenic,x1000-pinctrl",
4383 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
4384 },
4385 {
4386 .compatible = "ingenic,x1000e-pinctrl",
4387 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
4388 },
4389 {
4390 .compatible = "ingenic,x1500-pinctrl",
4391 .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info)
4392 },
4393 {
4394 .compatible = "ingenic,x1830-pinctrl",
4395 .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info)
4396 },
4397 {
4398 .compatible = "ingenic,x2000-pinctrl",
4399 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)
4400 },
4401 {
4402 .compatible = "ingenic,x2000e-pinctrl",
4403 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)
4404 },
4405 {
4406 .compatible = "ingenic,x2100-pinctrl",
4407 .data = IF_ENABLED(CONFIG_MACH_X2100, &x2100_chip_info)
4408 },
4409 { /* sentinel */ },
4410 };
4411
4412 static struct platform_driver ingenic_pinctrl_driver = {
4413 .driver = {
4414 .name = "pinctrl-ingenic",
4415 .of_match_table = ingenic_pinctrl_of_matches,
4416 },
4417 };
4418
ingenic_pinctrl_drv_register(void)4419 static int __init ingenic_pinctrl_drv_register(void)
4420 {
4421 return platform_driver_probe(&ingenic_pinctrl_driver,
4422 ingenic_pinctrl_probe);
4423 }
4424 subsys_initcall(ingenic_pinctrl_drv_register);
4425