| /drivers/phy/freescale/ |
| D | phy-fsl-lynx-28g.c | 23 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
46 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
55 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
61 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
70 #define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30) argument
73 #define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40) argument
80 #define LYNX_28G_LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44) argument
90 #define LYNX_28G_LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48) argument
92 #define LYNX_28G_LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50) argument
93 #define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54) argument
[all …]
|
| /drivers/phy/marvell/ |
| D | phy-mvebu-a3700-comphy.c | 183 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
226 unsigned int lane; member
233 .lane = _lane, \
396 static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane, in comphy_lane_reg_set() argument
399 if (lane->id == 2) { in comphy_lane_reg_set()
401 comphy_set_indirect(lane->priv, in comphy_lane_reg_set()
405 void __iomem *base = lane->id == 1 ? in comphy_lane_reg_set()
406 lane->priv->lane1_phy_regs : in comphy_lane_reg_set()
407 lane->priv->lane0_phy_regs; in comphy_lane_reg_set()
414 static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane, in comphy_lane_reg_poll() argument
[all …]
|
| D | phy-mvebu-cp110-comphy.c | 181 unsigned lane; member
189 .lane = _lane, \
199 .lane = _lane, \
276 unsigned long lane, unsigned long mode) in mvebu_comphy_smc() argument
281 arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res); in mvebu_comphy_smc()
294 static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port, in mvebu_comphy_get_mode() argument
308 if (conf->lane == lane && in mvebu_comphy_get_mode()
324 static inline int mvebu_comphy_get_mux(int lane, int port, in mvebu_comphy_get_mux() argument
327 return mvebu_comphy_get_mode(false, lane, port, mode, submode); in mvebu_comphy_get_mux()
330 static inline int mvebu_comphy_get_fw_mode(int lane, int port, in mvebu_comphy_get_fw_mode() argument
[all …]
|
| D | phy-armada38x-comphy.c | 46 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
58 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
60 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
66 conf |= BIT(lane->port); in a38x_set_conf()
68 conf &= ~BIT(lane->port); in a38x_set_conf()
73 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
78 val = readl_relaxed(lane->base + offset) & ~mask; in a38x_comphy_set_reg()
79 writel(val | value, lane->base + offset); in a38x_comphy_set_reg()
82 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, in a38x_comphy_set_speed() argument
85 a38x_comphy_set_reg(lane, COMPHY_CFG1, in a38x_comphy_set_speed()
[all …]
|
| /drivers/net/dsa/b53/ |
| D | b53_serdes.c | 42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config() local
[all …]
|
| /drivers/net/dsa/mv88e6xxx/ |
| D | serdes.c | 37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
41 return mv88e6xxx_phy_read(chip, lane, reg_c45, val); in mv88e6390_serdes_read()
45 int lane, int device, int reg, u16 val) in mv88e6390_serdes_write() argument
49 return mv88e6xxx_phy_write(chip, lane, reg_c45, val); in mv88e6390_serdes_write()
124 int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, in mv88e6352_serdes_power() argument
146 int lane, unsigned int mode, in mv88e6352_serdes_pcs_config() argument
195 int lane, struct phylink_link_state *state) in mv88e6352_serdes_pcs_get_state() argument
222 int lane) in mv88e6352_serdes_pcs_an_restart() argument
235 int lane, int speed, int duplex) in mv88e6352_serdes_pcs_link_up() argument
268 int lane = -ENODEV; in mv88e6352_serdes_get_lane() local
[all …]
|
| D | serdes.h | 113 int lane, unsigned int mode,
117 int lane, unsigned int mode,
121 int lane, struct phylink_link_state *state);
123 int lane, struct phylink_link_state *state);
125 int lane, struct phylink_link_state *state);
127 int lane, struct phylink_link_state *state);
129 int lane);
131 int lane);
133 int lane, int speed, int duplex);
135 int lane, int speed, int duplex);
[all …]
|
| /drivers/phy/ |
| D | phy-xgene.c | 657 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
663 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
672 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
677 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
683 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
688 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
690 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
693 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
698 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
700 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
[all …]
|
| /drivers/phy/tegra/ |
| D | xusb.c | 109 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane, in tegra_xusb_lane_parse_dt() argument
112 struct device *dev = &lane->pad->dev; in tegra_xusb_lane_parse_dt()
120 err = match_string(lane->soc->funcs, lane->soc->num_funcs, function); in tegra_xusb_lane_parse_dt()
127 lane->function = err; in tegra_xusb_lane_parse_dt()
135 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra_xusb_lane_destroy() local
137 lane->pad->ops->remove(lane); in tegra_xusb_lane_destroy()
185 struct phy *lane; in tegra_xusb_pad_register() local
193 pad->lanes = devm_kcalloc(&pad->dev, pad->soc->num_lanes, sizeof(lane), in tegra_xusb_pad_register()
202 struct tegra_xusb_lane *lane; in tegra_xusb_pad_register() local
217 lane = pad->ops->probe(pad, np, i); in tegra_xusb_pad_register()
[all …]
|
| D | xusb-tegra210.c | 447 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane) in tegra210_usb3_lane_map() argument
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
706 struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0); in tegra210_sata_uphy_enable() local
716 if (IS_ERR(lane)) in tegra210_sata_uphy_enable()
722 usb = tegra_xusb_lane_check(lane, "usb3-ss"); in tegra210_sata_uphy_enable()
1058 static int tegra210_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra210_usb3_enable_phy_sleepwalk() argument
1061 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_enable_phy_sleepwalk()
[all …]
|
| D | xusb.h | 54 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
62 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
64 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
75 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
77 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
85 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
87 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
104 to_hsic_lane(struct tegra_xusb_lane *lane) in to_hsic_lane() argument
106 return container_of(lane, struct tegra_xusb_hsic_lane, base); in to_hsic_lane()
114 to_pcie_lane(struct tegra_xusb_lane *lane) in to_pcie_lane() argument
[all …]
|
| D | xusb-tegra124.c | 292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
303 offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index); in tegra124_usb3_save_context()
452 static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra124_usb2_lane_remove() argument
454 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra124_usb2_lane_remove()
466 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_init() local
468 return tegra124_xusb_padctl_enable(lane->pad->padctl); in tegra124_usb2_phy_init()
473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_exit() local
475 return tegra124_xusb_padctl_disable(lane->pad->padctl); in tegra124_usb2_phy_exit()
[all …]
|
| D | xusb-tegra186.c | 308 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra186_usb2_lane_remove() argument
310 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra186_usb2_lane_remove()
315 static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra186_utmi_enable_phy_sleepwalk() argument
318 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_sleepwalk()
320 unsigned int index = lane->index; in tegra186_utmi_enable_phy_sleepwalk()
460 static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane) in tegra186_utmi_disable_phy_sleepwalk() argument
462 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_disable_phy_sleepwalk()
464 unsigned int index = lane->index; in tegra186_utmi_disable_phy_sleepwalk()
501 static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane) in tegra186_utmi_enable_phy_wake() argument
503 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_wake()
[all …]
|
| /drivers/gpu/drm/bridge/analogix/ |
| D | analogix_dp_core.c | 239 int pre_emphasis, int lane) in analogix_dp_set_lane_lane_pre_emphasis() argument
241 switch (lane) { in analogix_dp_set_lane_lane_pre_emphasis()
262 int lane, lane_count, pll_tries, retval; in analogix_dp_link_start() local
269 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
270 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
290 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
292 PRE_EMPHASIS_LEVEL_0, lane); in analogix_dp_link_start()
316 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
317 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | in analogix_dp_link_start()
328 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) in analogix_dp_get_lane_status() argument
[all …]
|
| /drivers/gpu/drm/i915/display/ |
| D | intel_dp_link_training.c | 317 int lane) in intel_dp_get_lane_adjust_tx_ffe_preset() argument
322 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset()
323 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane); in intel_dp_get_lane_adjust_tx_ffe_preset()
325 for (lane = 0; lane < crtc_state->lane_count; lane++) in intel_dp_get_lane_adjust_tx_ffe_preset()
326 tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); in intel_dp_get_lane_adjust_tx_ffe_preset()
337 int lane) in intel_dp_get_lane_adjust_vswing_preemph() argument
345 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_vswing_preemph()
347 v = drm_dp_get_adjust_request_voltage(link_status, lane); in intel_dp_get_lane_adjust_vswing_preemph()
348 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); in intel_dp_get_lane_adjust_vswing_preemph()
350 for (lane = 0; lane < crtc_state->lane_count; lane++) { in intel_dp_get_lane_adjust_vswing_preemph()
[all …]
|
| /drivers/phy/rockchip/ |
| D | phy-rockchip-typec.c | 505 static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_tx_usb3_cfg_lane() argument
507 writel(0x7799, tcphy->base + TX_PSC_A0(lane)); in tcphy_tx_usb3_cfg_lane()
508 writel(0x7798, tcphy->base + TX_PSC_A1(lane)); in tcphy_tx_usb3_cfg_lane()
509 writel(0x5098, tcphy->base + TX_PSC_A2(lane)); in tcphy_tx_usb3_cfg_lane()
510 writel(0x5098, tcphy->base + TX_PSC_A3(lane)); in tcphy_tx_usb3_cfg_lane()
511 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane)); in tcphy_tx_usb3_cfg_lane()
512 writel(0xbf, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); in tcphy_tx_usb3_cfg_lane()
515 static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_rx_usb3_cfg_lane() argument
517 writel(0xa6fd, tcphy->base + RX_PSC_A0(lane)); in tcphy_rx_usb3_cfg_lane()
518 writel(0xa6fd, tcphy->base + RX_PSC_A1(lane)); in tcphy_rx_usb3_cfg_lane()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_dp.c | 344 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
375 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
376 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
377 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
392 uint8_t lane = 0; in dp_fixed_vs_pe_set_retimer_lane_settings() local
399 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
401 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
403 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
659 uint32_t lane; in dp_is_cr_done() local
661 for (lane = 0; lane < (uint32_t)(ln_count); lane++) { in dp_is_cr_done()
[all …]
|
| /drivers/phy/mediatek/ |
| D | phy-mtk-pcie.c | 81 unsigned int lane) in mtk_pcie_efuse_set_lane() argument
83 struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_set_lane()
90 lane * PEXTP_ANA_LANE_OFFSET; in mtk_pcie_efuse_set_lane()
134 unsigned int lane) in mtk_pcie_efuse_read_for_lane() argument
136 struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_read_for_lane()
141 snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane); in mtk_pcie_efuse_read_for_lane()
146 snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane); in mtk_pcie_efuse_read_for_lane()
151 snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane); in mtk_pcie_efuse_read_for_lane()
159 lane); in mtk_pcie_efuse_read_for_lane()
|
| /drivers/net/ethernet/ti/ |
| D | netcp_xgbepcsr.c | 148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
182 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_enable() argument
185 writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane)); in netcp_xgbe_serdes_lane_enable()
283 void __iomem *sig_detect_reg, int lane) in netcp_xgbe_serdes_reset_cdr() argument
289 serdes_regs, lane + 1, 5); in netcp_xgbe_serdes_reset_cdr()
298 tbus = netcp_xgbe_serdes_read_select_tbus(serdes_regs, lane + in netcp_xgbe_serdes_reset_cdr()
430 int lane, int cm, int c1, int c2) in netcp_xgbe_serdes_setup_cm_c1_c2() argument
[all …]
|
| /drivers/pinctrl/tegra/ |
| D | pinctrl-tegra-xusb.c | 299 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_pinmux_set() local
303 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinmux_set()
305 for (i = 0; i < lane->num_funcs; i++) in tegra_xusb_padctl_pinmux_set()
306 if (lane->funcs[i] == function) in tegra_xusb_padctl_pinmux_set()
309 if (i >= lane->num_funcs) in tegra_xusb_padctl_pinmux_set()
312 value = padctl_readl(padctl, lane->offset); in tegra_xusb_padctl_pinmux_set()
313 value &= ~(lane->mask << lane->shift); in tegra_xusb_padctl_pinmux_set()
314 value |= i << lane->shift; in tegra_xusb_padctl_pinmux_set()
315 padctl_writel(padctl, value, lane->offset); in tegra_xusb_padctl_pinmux_set()
332 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_pinconf_group_get() local
[all …]
|
| /drivers/nvdimm/ |
| D | btt.c | 206 static int btt_log_group_read(struct arena_info *arena, u32 lane, in btt_log_group_read() argument
210 arena->logoff + (lane * LOG_GRP_SIZE), log, in btt_log_group_read()
327 static int btt_log_read(struct arena_info *arena, u32 lane, in btt_log_read() argument
334 ret = btt_log_group_read(arena, lane, &log); in btt_log_read()
342 old_ent, lane, log.ent[arena->log_index[0]].seq, in btt_log_read()
361 static int __btt_log_write(struct arena_info *arena, u32 lane, in __btt_log_write() argument
370 ns_off = arena->logoff + (lane * LOG_GRP_SIZE) + in __btt_log_write()
382 static int btt_flog_write(struct arena_info *arena, u32 lane, u32 sub, in btt_flog_write() argument
387 ret = __btt_log_write(arena, lane, sub, ent, NVDIMM_IO_ATOMIC); in btt_flog_write()
392 arena->freelist[lane].sub = 1 - arena->freelist[lane].sub; in btt_flog_write()
[all …]
|
| /drivers/ata/ |
| D | sata_highbank.c | 259 u8 lane = port_data[sata_port].lane_mapping; in highbank_cphy_disable_overrides() local
263 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in highbank_cphy_disable_overrides()
265 combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); in highbank_cphy_disable_overrides()
270 u8 lane = port_data[sata_port].lane_mapping; in cphy_override_tx_attenuation() local
276 tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_override_tx_attenuation()
278 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
281 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
284 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
289 u8 lane = port_data[sata_port].lane_mapping; in cphy_override_rx_mode() local
291 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_override_rx_mode()
[all …]
|
| /drivers/thunderbolt/ |
| D | lc.c | 52 u32 ctrl, lane; in tb_lc_set_port_configured() local
68 lane = TB_LC_SX_CTRL_L1C; in tb_lc_set_port_configured()
70 lane = TB_LC_SX_CTRL_L2C; in tb_lc_set_port_configured()
73 ctrl |= lane; in tb_lc_set_port_configured()
77 ctrl &= ~lane; in tb_lc_set_port_configured()
110 u32 ctrl, lane; in tb_lc_set_xdomain_configured() local
126 lane = TB_LC_SX_CTRL_L1D; in tb_lc_set_xdomain_configured()
128 lane = TB_LC_SX_CTRL_L2D; in tb_lc_set_xdomain_configured()
131 ctrl |= lane; in tb_lc_set_xdomain_configured()
133 ctrl &= ~lane; in tb_lc_set_xdomain_configured()
|
| /drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 1246 int lane) in cdv_intel_get_adjust_request_voltage() argument
1248 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); in cdv_intel_get_adjust_request_voltage()
1249 int s = ((lane & 1) ? in cdv_intel_get_adjust_request_voltage()
1259 int lane) in cdv_intel_get_adjust_request_pre_emphasis() argument
1261 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); in cdv_intel_get_adjust_request_pre_emphasis()
1262 int s = ((lane & 1) ? in cdv_intel_get_adjust_request_pre_emphasis()
1278 int lane; in cdv_intel_get_adjust_train() local
1280 for (lane = 0; lane < intel_dp->lane_count; lane++) { in cdv_intel_get_adjust_train()
1281 uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane); in cdv_intel_get_adjust_train()
1282 uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); in cdv_intel_get_adjust_train()
[all …]
|
| /drivers/phy/xilinx/ |
| D | phy-zynqmp.c | 197 u8 lane; member
278 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_read_phy()
287 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_write_phy()
296 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_clr_set_phy()
334 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); in xpsgtr_wait_pll_lock()
348 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
352 if (gtr_phy->refclk != gtr_phy->lane) { in xpsgtr_configure_pll()
354 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
394 switch (gtr_phy->lane) { in xpsgtr_lane_set_protocol()
442 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET); in xpsgtr_phy_init_sata()
[all …]
|