| /drivers/scsi/ |
| D | scsi_debug.c | 3082 u32 lb_size = sdebug_sector_size; in comp_write_worker() local
3089 res = !memcmp(fsp + (block * lb_size), arr, (num - rest) * lb_size); in comp_write_worker()
3093 res = memcmp(fsp, arr + ((num - rest) * lb_size), in comp_write_worker()
3094 rest * lb_size); in comp_write_worker()
3099 arr += num * lb_size; in comp_write_worker()
3100 memcpy(fsp + (block * lb_size), arr, (num - rest) * lb_size); in comp_write_worker()
3102 memcpy(fsp, arr + ((num - rest) * lb_size), rest * lb_size); in comp_write_worker()
3738 u32 lb_size = sdebug_sector_size; in resp_write_scat() local
3780 lbdof_blen = lbdof * lb_size; in resp_write_scat()
3818 num_by = num * lb_size; in resp_write_scat()
[all …]
|
| /drivers/gpu/drm/amd/amdgpu/ |
| D | dce_v6_0.c | 506 u32 lb_size; /* line buffer allocated to pipe */ member
790 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v6_0_check_latency_hiding()
827 u32 lb_size, u32 num_heads) in dce_v6_0_program_watermarks() argument
875 wm_high.lb_size = lb_size; in dce_v6_0_program_watermarks()
902 wm_low.lb_size = lb_size; in dce_v6_0_program_watermarks()
954 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v6_0_program_watermarks()
1062 u32 num_heads = 0, lb_size; in dce_v6_0_bandwidth_update() local
1077 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); in dce_v6_0_bandwidth_update()
1078 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1079 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); in dce_v6_0_bandwidth_update()
[all …]
|
| D | dce_v8_0.c | 643 u32 lb_size; /* line buffer allocated to pipe */ member
927 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v8_0_check_latency_hiding()
964 u32 lb_size, u32 num_heads) in dce_v8_0_program_watermarks() argument
1003 wm_high.lb_size = lb_size; in dce_v8_0_program_watermarks()
1042 wm_low.lb_size = lb_size; in dce_v8_0_program_watermarks()
1057 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v8_0_program_watermarks()
1099 u32 num_heads = 0, lb_size; in dce_v8_0_bandwidth_update() local
1110 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v8_0_bandwidth_update()
1112 lb_size, num_heads); in dce_v8_0_bandwidth_update()
|
| D | dce_v10_0.c | 708 u32 lb_size; /* line buffer allocated to pipe */ member
992 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v10_0_check_latency_hiding()
1029 u32 lb_size, u32 num_heads) in dce_v10_0_program_watermarks() argument
1068 wm_high.lb_size = lb_size; in dce_v10_0_program_watermarks()
1107 wm_low.lb_size = lb_size; in dce_v10_0_program_watermarks()
1122 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v10_0_program_watermarks()
1162 u32 num_heads = 0, lb_size; in dce_v10_0_bandwidth_update() local
1173 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v10_0_bandwidth_update()
1175 lb_size, num_heads); in dce_v10_0_bandwidth_update()
|
| D | dce_v11_0.c | 734 u32 lb_size; /* line buffer allocated to pipe */ member
1018 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v11_0_check_latency_hiding()
1055 u32 lb_size, u32 num_heads) in dce_v11_0_program_watermarks() argument
1094 wm_high.lb_size = lb_size; in dce_v11_0_program_watermarks()
1133 wm_low.lb_size = lb_size; in dce_v11_0_program_watermarks()
1148 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v11_0_program_watermarks()
1188 u32 num_heads = 0, lb_size; in dce_v11_0_bandwidth_update() local
1199 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v11_0_bandwidth_update()
1201 lb_size, num_heads); in dce_v11_0_bandwidth_update()
|
| /drivers/gpu/drm/radeon/ |
| D | evergreen.c | 1945 u32 lb_size; /* line buffer allocated to pipe */ member
2130 u32 lb_partitions = wm->lb_size / wm->src_width; in evergreen_check_latency_hiding()
2156 u32 lb_size, u32 num_heads) in evergreen_program_watermarks() argument
2204 wm_high.lb_size = lb_size; in evergreen_program_watermarks()
2231 wm_low.lb_size = lb_size; in evergreen_program_watermarks()
2282 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in evergreen_program_watermarks()
2327 u32 num_heads = 0, lb_size; in evergreen_bandwidth_update() local
2342 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in evergreen_bandwidth_update()
2343 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in evergreen_bandwidth_update()
2344 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in evergreen_bandwidth_update()
[all …]
|
| D | rs690.c | 212 u32 lb_size = 8192; in rs690_line_buffer_adjust() local
253 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in rs690_line_buffer_adjust()
256 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in rs690_line_buffer_adjust()
|
| D | si.c | 2064 u32 lb_size; /* line buffer allocated to pipe */ member
2269 u32 lb_partitions = wm->lb_size / wm->src_width; in dce6_check_latency_hiding()
2295 u32 lb_size, u32 num_heads) in dce6_program_watermarks() argument
2346 wm_high.lb_size = lb_size; in dce6_program_watermarks()
2373 wm_low.lb_size = lb_size; in dce6_program_watermarks()
2426 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce6_program_watermarks()
2463 u32 num_heads = 0, lb_size; in dce6_bandwidth_update() local
2478 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in dce6_bandwidth_update()
2479 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in dce6_bandwidth_update()
2480 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in dce6_bandwidth_update()
[all …]
|
| D | cik.c | 8910 u32 lb_size; /* line buffer allocated to pipe */ member
9194 u32 lb_partitions = wm->lb_size / wm->src_width; in dce8_check_latency_hiding()
9231 u32 lb_size, u32 num_heads) in dce8_program_watermarks() argument
9271 wm_high.lb_size = lb_size; in dce8_program_watermarks()
9311 wm_low.lb_size = lb_size; in dce8_program_watermarks()
9328 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce8_program_watermarks()
9368 u32 num_heads = 0, lb_size; in dce8_bandwidth_update() local
9382 lb_size = dce8_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode); in dce8_bandwidth_update()
9383 dce8_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in dce8_bandwidth_update()
|
| D | r100.c | 3217 u32 lb_size = 8192; in r100_bandwidth_update() local
3642 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in r100_bandwidth_update()
3645 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in r100_bandwidth_update()
|