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Searched refs:mac_base (Results 1 – 10 of 10) sorted by relevance

/drivers/usb/mtu3/
Dmtu3_core.c75 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN); in mtu3_ss_func_set()
77 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN); in mtu3_ss_func_set()
86 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT, in mtu3_hs_softconn_set()
89 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT, in mtu3_hs_softconn_set()
178 void __iomem *mbase = mtu->mac_base; in mtu3_intr_status_clear()
196 mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0); in mtu3_intr_disable()
198 mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0); in mtu3_intr_disable()
205 void __iomem *mbase = mtu->mac_base; in mtu3_intr_enable()
234 void __iomem *mbase = mtu->mac_base; in mtu3_set_speed()
274 void __iomem *mbase = mtu->mac_base; in mtu3_csr_init()
[all …]
Dmtu3_gadget_ep0.c82 void __iomem *fifo = mep->mtu->mac_base + U3D_FIFO0; in ep0_write_fifo()
102 void __iomem *fifo = mep->mtu->mac_base + U3D_FIFO0; in ep0_read_fifo()
138 void __iomem *mbase = mtu->mac_base; in ep0_stall_set()
147 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr); in ep0_stall_set()
158 void __iomem *mbase = mtu->mac_base; in ep0_do_status_stage()
278 void __iomem *mbase = mtu->mac_base; in handle_test_mode()
328 void __iomem *mbase = mtu->mac_base; in ep0_handle_feature_dev()
443 void __iomem *mbase = mtu->mac_base; in handle_standard_request()
513 void __iomem *mbase = mtu->mac_base; in ep0_rx_state()
596 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_tx_state()
[all …]
Dmtu3_qmu.c192 void __iomem *mbase = mtu->mac_base; in mtu3_qmu_resume()
334 void __iomem *mbase = mtu->mac_base; in mtu3_qmu_start()
378 void __iomem *mbase = mtu->mac_base; in mtu3_qmu_stop()
422 void __iomem *mbase = mtu->mac_base; in qmu_tx_zlp_error_handler()
474 void __iomem *mbase = mtu->mac_base; in qmu_done_tx()
514 void __iomem *mbase = mtu->mac_base; in qmu_done_rx()
562 void __iomem *mbase = mtu->mac_base; in qmu_exception_isr()
602 void __iomem *mbase = mtu->mac_base; in mtu3_qmu_isr()
Dmtu3_gadget.c433 return (int)mtu3_readl(mtu->mac_base, U3D_USB20_FRAME_NUM); in mtu3_gadget_get_frame()
438 mtu3_writel(mtu->mac_base, U3D_DEV_NOTIF_0, in function_wake_notif()
440 mtu3_setbits(mtu->mac_base, U3D_DEV_NOTIF_0, SEND_DEV_NOTIF); in function_wake_notif()
460 mtu3_setbits(mtu->mac_base, U3D_LINK_POWER_CONTROL, UX_EXIT); in mtu3_gadget_wakeup()
469 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT, RESUME); in mtu3_gadget_wakeup()
473 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT, RESUME); in mtu3_gadget_wakeup()
Dmtu3_debugfs.c82 void __iomem *mbase = mtu->mac_base; in mtu3_link_state_show()
170 mtu3_debugfs_regset(mtu, mtu->mac_base, regs, 7, "ep-regs", parent); in mtu3_debugfs_ep_regset()
412 mtu3_debugfs_regset(mtu, mtu->mac_base, in ssusb_dev_debugfs_init()
416 mtu3_debugfs_regset(mtu, mtu->mac_base, in ssusb_dev_debugfs_init()
Dmtu3.h245 void __iomem *mac_base; member
326 void __iomem *mac_base; member
Dmtu3_dr.c24 mtu3_setbits(ssusb->mac_base, U3D_DEVICE_CONTROL, DC_SESSION); in toggle_opstate()
25 mtu3_setbits(ssusb->mac_base, U3D_POWER_MANAGEMENT, SOFT_CONN); in toggle_opstate()
/drivers/net/ethernet/atheros/
Dag71xx.c364 void __iomem *mac_base; member
409 iowrite32(value, ag->mac_base + reg); in ag71xx_wr()
411 (void)ioread32(ag->mac_base + reg); in ag71xx_wr()
416 return ioread32(ag->mac_base + reg); in ag71xx_rr()
423 r = ag->mac_base + reg; in ag71xx_sb()
433 r = ag->mac_base + reg; in ag71xx_cb()
1869 ag->mac_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); in ag71xx_probe()
1870 if (!ag->mac_base) in ag71xx_probe()
1959 (unsigned long)ag->mac_base, ndev->irq, in ag71xx_probe()
/drivers/atm/
Deni.c1691 void __iomem *mac_base; in get_esi_fpga() local
1694 mac_base = base+EPROM_SIZE-sizeof(struct midway_eprom); in get_esi_fpga()
1695 for (i = 0; i < ESI_LEN; i++) dev->esi[i] = readb(mac_base+(i^3)); in get_esi_fpga()
/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_link.c13735 u32 mac_base; in bnx2x_check_half_open_conn() local
13749 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in bnx2x_check_half_open_conn()
13752 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_check_half_open_conn()
13753 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_check_half_open_conn()
13756 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) in bnx2x_check_half_open_conn()
13767 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : in bnx2x_check_half_open_conn()
13775 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); in bnx2x_check_half_open_conn()