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Searched refs:mask_val (Results 1 – 19 of 19) sorted by relevance

/drivers/bus/
Domap_l3_noc.c164 u32 err_reg, mask_val; in l3_interrupt_handler() local
205 mask_val = readl_relaxed(mask_reg); in l3_interrupt_handler()
206 mask_val &= ~(1 << err_src); in l3_interrupt_handler()
207 writel_relaxed(mask_val, mask_reg); in l3_interrupt_handler()
312 u32 mask_val; in l3_resume_noirq() local
322 mask_val = readl_relaxed(mask_regx); in l3_resume_noirq()
323 mask_val &= ~(flag_mux->mask_app_bits); in l3_resume_noirq()
325 writel_relaxed(mask_val, mask_regx); in l3_resume_noirq()
328 mask_val = readl_relaxed(mask_regx); in l3_resume_noirq()
329 mask_val &= ~(flag_mux->mask_dbg_bits); in l3_resume_noirq()
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/drivers/irqchip/
Dirq-csky-mpintc.c128 const struct cpumask *mask_val, in csky_irq_set_affinity() argument
135 cpu = cpumask_any_and(mask_val, cpu_online_mask); in csky_irq_set_affinity()
137 cpu = cpumask_first(mask_val); in csky_irq_set_affinity()
151 if (cpumask_equal(mask_val, cpu_present_mask)) in csky_irq_set_affinity()
Dirq-hip04.c147 const struct cpumask *mask_val, in hip04_irq_set_affinity() argument
155 cpu = cpumask_any_and(mask_val, cpu_online_mask); in hip04_irq_set_affinity()
157 cpu = cpumask_first(mask_val); in hip04_irq_set_affinity()
Dexynos-combiner.c94 const struct cpumask *mask_val, bool force) in combiner_set_affinity() argument
101 return chip->irq_set_affinity(data, mask_val, force); in combiner_set_affinity()
Dirq-sifive-plic.c158 const struct cpumask *mask_val, bool force) in plic_set_affinity() argument
164 cpumask_and(&amask, &priv->lmask, mask_val); in plic_set_affinity()
Dirq-armada-370-xp.c468 const struct cpumask *mask_val, bool force) in armada_xp_set_affinity() argument
475 cpu = cpumask_any_and(mask_val, cpu_online_mask); in armada_xp_set_affinity()
Dirq-apple-aic.c399 const struct cpumask *mask_val, bool force) in aic_irq_set_affinity() argument
408 cpu = cpumask_first(mask_val); in aic_irq_set_affinity()
410 cpu = cpumask_any_and(mask_val, cpu_online_mask); in aic_irq_set_affinity()
Dirq-gic.c796 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, in gic_set_affinity() argument
807 cpu = cpumask_any_and(mask_val, cpu_online_mask); in gic_set_affinity()
809 cpu = cpumask_first(mask_val); in gic_set_affinity()
820 trace_android_vh_gic_set_affinity(d, mask_val, force, gic_cpu_map, reg); in gic_set_affinity()
Dirq-gic-v3.c1364 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, in gic_set_affinity() argument
1374 cpu = cpumask_first(mask_val); in gic_set_affinity()
1376 cpu = cpumask_any_and(mask_val, cpu_online_mask); in gic_set_affinity()
1393 trace_android_rvh_gic_v3_set_affinity(d, mask_val, &val, force, gic_dist_base(d), in gic_set_affinity()
Dirq-gic-v3-its.c1670 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, in its_set_affinity() argument
1686 cpu = its_select_cpu(d, mask_val); in its_set_affinity()
1688 cpu = cpumask_pick_least_loaded(d, mask_val); in its_set_affinity()
3804 const struct cpumask *mask_val, in its_vpe_set_affinity() argument
3832 if (table_mask && cpumask_and(&common, mask_val, table_mask)) in its_vpe_set_affinity()
3835 cpu = cpumask_first(mask_val); in its_vpe_set_affinity()
4233 const struct cpumask *mask_val, in its_sgi_set_affinity() argument
4241 irq_data_update_effective_affinity(d, mask_val); in its_sgi_set_affinity()
Dirq-mvebu-sei.c94 const struct cpumask *mask_val, in mvebu_sei_set_affinity() argument
Dirq-ti-sci-inta.c503 const struct cpumask *mask_val, bool force) in ti_sci_inta_set_affinity() argument
/drivers/watchdog/
Ds3c2410_wdt.c318 const u32 mask_val = BIT(wdt->drv_data->mask_bit); in s3c2410wdt_disable_wdt_reset() local
319 const u32 val = mask ? mask_val : 0; in s3c2410wdt_disable_wdt_reset()
323 mask_val, val); in s3c2410wdt_disable_wdt_reset()
332 const u32 mask_val = BIT(wdt->drv_data->mask_bit); in s3c2410wdt_mask_wdt_reset() local
334 const u32 val = (mask ^ val_inv) ? mask_val : 0; in s3c2410wdt_mask_wdt_reset()
338 mask_val, val); in s3c2410wdt_mask_wdt_reset()
347 const u32 mask_val = BIT(wdt->drv_data->cnt_en_bit); in s3c2410wdt_enable_counter() local
348 const u32 val = en ? mask_val : 0; in s3c2410wdt_enable_counter()
352 mask_val, val); in s3c2410wdt_enable_counter()
/drivers/net/ethernet/chelsio/cxgb4/
Dcxgb4_tc_u32_parse.h57 u32 mask_val; in cxgb4_fill_ipv4_frag() local
61 mask_val = ntohl(mask) & 0x0000FFFF; in cxgb4_fill_ipv4_frag()
63 if (frag_val == 0x1 && mask_val != 0x3FFF) { /* MF set */ in cxgb4_fill_ipv4_frag()
66 } else if (frag_val == 0x2 && mask_val != 0x3FFF) { /* DF set */ in cxgb4_fill_ipv4_frag()
/drivers/net/wireless/ath/ath9k/
Dar9003_wow.c126 u32 pattern_val, mask_val; in ath9k_hw_wow_apply_pattern() local
145 memcpy(&mask_val, user_mask, 4); in ath9k_hw_wow_apply_pattern()
146 REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val); in ath9k_hw_wow_apply_pattern()
Dxmit.c1659 u16 mask_val = mask * val; in ath9k_set_moredata() local
1662 if ((hdr->frame_control & mask) != mask_val) { in ath9k_set_moredata()
1663 hdr->frame_control = (hdr->frame_control & ~mask) | mask_val; in ath9k_set_moredata()
/drivers/media/platform/qcom/venus/
Dhfi_venus.c460 u32 ctrl_status = 0, mask_val; in venus_boot_core() local
467 mask_val = readl(wrapper_base + WRAPPER_INTR_MASK); in venus_boot_core()
468 mask_val &= ~(WRAPPER_INTR_MASK_A2HWD_BASK_V6 | in venus_boot_core()
471 mask_val = WRAPPER_INTR_MASK_A2HVCODEC_MASK; in venus_boot_core()
473 writel(mask_val, wrapper_base + WRAPPER_INTR_MASK); in venus_boot_core()
557 u32 mask_val; in venus_halt_axi() local
576 mask_val = (BIT(2) | BIT(1) | BIT(0)); in venus_halt_axi()
577 writel(mask_val, wrapper_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_V6); in venus_halt_axi()
/drivers/net/ethernet/qlogic/qed/
Dqed_dbg_hsi.h174 u32 mask_val; member
Dqed_debug.c5769 reg_result->mask_val = qed_rd(p_hwfn, in qed_dbg_read_attn()
7816 masked_str = reg_result->mask_val & in qed_dbg_parse_attn()