| /drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_cfg.c | 103 .max_clk = 200000000,
190 .max_clk = 320000000,
290 .max_clk = 320000000,
362 .max_clk = 320000000,
442 .max_clk = 366670000,
542 .max_clk = 400000000,
655 .max_clk = 412500000,
752 .max_clk = 360000000,
845 .max_clk = 400000000,
930 .max_clk = 320000000,
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| D | mdp5_cfg.h | 104 uint32_t max_clk; member
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| D | mdp5_kms.c | 860 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); in mdp5_init()
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| /drivers/mmc/host/ |
| D | sdhci-of-esdhc.c | 36 const unsigned int max_clk[MMC_TIMING_NUM]; member
41 .max_clk[MMC_TIMING_MMC_HS] = 46500000,
42 .max_clk[MMC_TIMING_SD_HS] = 46500000,
47 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
48 .max_clk[MMC_TIMING_MMC_HS200] = 167000000,
53 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000,
54 .max_clk[MMC_TIMING_MMC_HS200] = 125000000,
59 .max_clk[MMC_TIMING_LEGACY] = 20000000,
60 .max_clk[MMC_TIMING_MMC_HS] = 42000000,
61 .max_clk[MMC_TIMING_SD_HS] = 40000000,
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| D | sdhci-cns3xxx.c | 37 while (host->max_clk / div > clock) { in sdhci_cns3xxx_set_clock()
51 clock, host->max_clk / div); in sdhci_cns3xxx_set_clock()
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| D | bcm2835.c | 154 unsigned int max_clk; /* Max possible freq */ member
1135 div = host->max_clk / clock; in bcm2835_set_clock()
1138 if ((host->max_clk / div) > clock) in bcm2835_set_clock()
1145 clock = host->max_clk / (div + 2); in bcm2835_set_clock()
1272 if (!mmc->f_max || mmc->f_max > host->max_clk) in bcm2835_add_host()
1273 mmc->f_max = host->max_clk; in bcm2835_add_host()
1274 mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV; in bcm2835_add_host()
1411 host->max_clk = clk_get_rate(clk); in bcm2835_probe()
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| D | sdhci.c | 1933 if ((host->max_clk * host->clk_mul / div) in sdhci_calc_clk()
1937 if ((host->max_clk * host->clk_mul / div) <= clock) { in sdhci_calc_clk()
1957 if (host->max_clk <= clock) in sdhci_calc_clk()
1962 if ((host->max_clk / div) <= clock) in sdhci_calc_clk()
1969 && !div && host->max_clk <= 25000000) in sdhci_calc_clk()
1975 if ((host->max_clk / div) <= clock) in sdhci_calc_clk()
1984 *actual_clock = (host->max_clk * clk_mul) / real_div; in sdhci_calc_clk()
4259 u32 max_clk; in sdhci_setup_host() local
4412 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps); in sdhci_setup_host()
4414 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps); in sdhci_setup_host()
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| D | sdhci-of-aspeed.c | 254 if (WARN_ON(clock > host->max_clk)) in aspeed_sdhci_set_clock()
255 clock = host->max_clk; in aspeed_sdhci_set_clock()
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| D | sdhci-cadence.c | 183 return host->max_clk; in sdhci_cdns_get_timeout_clock()
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| D | sdhci.h | 523 unsigned int max_clk; /* Max possible freq (MHz) */ member
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| D | sdhci-s3c.c | 265 host->max_clk = ourhost->clk_rates[best_src]; in sdhci_s3c_set_clock()
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| D | sdhci-tegra.c | 779 host->max_clk = host_clk; in tegra_sdhci_set_clock()
781 host->max_clk = clk_get_rate(pltfm_host->clk); in tegra_sdhci_set_clock()
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| D | sdhci-of-arasan.c | 283 sdhci_set_clock(host, host->max_clk); in sdhci_arasan_set_clock()
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| /drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| D | aldebaran_ppt.c | 754 uint32_t min_clk, max_clk; in aldebaran_print_clk_levels() local
787 max_clk = pstate_table->gfxclk_pstate.curr.max; in aldebaran_print_clk_levels()
790 freq_values[1] = max_clk; in aldebaran_print_clk_levels()
793 if (now > min_clk && now < max_clk) { in aldebaran_print_clk_levels()
795 freq_values[2] = max_clk; in aldebaran_print_clk_levels()
1318 uint32_t max_clk; in aldebaran_set_soft_freq_limited_range() local
1359 max_clk = dpm_context->dpm_tables.gfx_table.max; in aldebaran_set_soft_freq_limited_range()
1360 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); in aldebaran_set_soft_freq_limited_range()
1386 uint32_t max_clk; in aldebaran_usr_edit_dpm_table() local
1432 max_clk = dpm_context->dpm_tables.gfx_table.max; in aldebaran_usr_edit_dpm_table()
[all …]
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| /drivers/gpu/drm/msm/disp/mdp4/ |
| D | mdp4_kms.c | 394 unsigned long max_clk; in mdp4_kms_init() local
397 max_clk = 266667000; in mdp4_kms_init()
465 clk_set_rate(mdp4_kms->clk, max_clk); in mdp4_kms_init()
485 clk_set_rate(mdp4_kms->lut_clk, max_clk); in mdp4_kms_init()
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| /drivers/gpu/drm/bridge/ |
| D | sil-sii8620.c | 1176 int max_clk; in sii8620_start_video() member
1193 if (clk < clk_spec[i].max_clk) in sii8620_start_video()
1196 if (100 * clk >= 98 * clk_spec[i].max_clk) in sii8620_start_video()
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| /drivers/misc/habanalabs/common/ |
| D | firmware_if.c | 2848 int hl_fw_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk) in hl_fw_get_clk_rate() argument
2857 *max_clk = 0; in hl_fw_get_clk_rate()
2868 *max_clk = (value / 1000 / 1000); in hl_fw_get_clk_rate()
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| D | habanalabs.h | 3760 int hl_fw_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
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