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Searched refs:max_handles (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/radeon/
Dradeon_uvd.c138 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; in radeon_uvd_init()
168 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES; in radeon_uvd_init()
188 RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles; in radeon_uvd_init()
221 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_init()
258 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_suspend()
333 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_free_handles()
508 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { in radeon_uvd_cs_msg()
534 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { in radeon_uvd_cs_msg()
549 for (i = 0; i < p->rdev->uvd.max_handles; ++i) in radeon_uvd_cs_msg()
849 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_count_handles()
Duvd_v4_2.c62 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v4_2_resume()
75 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles); in uvd_v4_2_resume()
Duvd_v2_2.c125 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v2_2_resume()
Duvd_v1_0.c133 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v1_0_resume()
Dradeon.h1709 unsigned max_handles; member
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_uvd.c280 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; in amdgpu_uvd_sw_init()
301 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; in amdgpu_uvd_sw_init()
320 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; in amdgpu_uvd_sw_init()
326 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; in amdgpu_uvd_sw_init()
342 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_sw_init()
437 for (i = 0; i < adev->uvd.max_handles; ++i) in amdgpu_uvd_suspend()
441 if (i == adev->uvd.max_handles) in amdgpu_uvd_suspend()
525 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_free_handles()
849 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_cs_msg()
873 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_cs_msg()
[all …]
Damdgpu_uvd.h57 unsigned max_handles; member
Duvd_v3_1.c258 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; in uvd_v3_1_mc_resume()
Duvd_v4_2.c587 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; in uvd_v4_2_mc_resume()
Duvd_v6_0.c623 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); in uvd_v6_0_mc_resume()
631 WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); in uvd_v6_0_mc_resume()
Duvd_v5_0.c299 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); in uvd_v5_0_mc_resume()
Duvd_v7_0.c722 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); in uvd_v7_0_mc_resume()
858 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); in uvd_v7_0_sriov_start()
Damdgpu_kms.c927 handle.uvd_max_handles = adev->uvd.max_handles; in amdgpu_info_ioctl()