Home
last modified time | relevance | path

Searched refs:mclk_edc_wr_enable_threshold (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/radeon/
Dcypress_dpm.h82 u32 mclk_edc_wr_enable_threshold; member
Dci_dpm.h214 u32 mclk_edc_wr_enable_threshold; member
Dni_dpm.c2343 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) in ni_convert_power_level_to_smc()
4135 eg_pi->mclk_edc_wr_enable_threshold = 55000; in ni_dpm_init()
4139 eg_pi->mclk_edc_wr_enable_threshold = 40000; in ni_dpm_init()
4141 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; in ni_dpm_init()
Dcypress_dpm.c713 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) in cypress_convert_power_level_to_smc()
2067 eg_pi->mclk_edc_wr_enable_threshold = 40000; in cypress_dpm_init()
Dbtc_dpm.c2614 eg_pi->mclk_edc_wr_enable_threshold = 40000; in btc_dpm_init()
Dsi_dpm.c4997 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) in si_convert_power_level_to_smc()
6978 eg_pi->mclk_edc_wr_enable_threshold = 40000; in si_dpm_init()
6980 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; in si_dpm_init()
Dci_dpm.c2908 if (pi->mclk_edc_wr_enable_threshold && in ci_populate_single_memory_level()
2909 (memory_clock > pi->mclk_edc_wr_enable_threshold)) in ci_populate_single_memory_level()
5745 pi->mclk_edc_wr_enable_threshold = 40000; in ci_dpm_init()
/drivers/gpu/drm/amd/pm/legacy-dpm/
Dsi_dpm.h673 u32 mclk_edc_wr_enable_threshold; member
Dsi_dpm.c5499 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) in si_convert_power_level_to_smc()
7415 eg_pi->mclk_edc_wr_enable_threshold = 40000; in si_dpm_init()
7417 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; in si_dpm_init()
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Diceland_smumgr.c1236 uint32_t mclk_edc_wr_enable_threshold = 40000; in iceland_populate_single_memory_level() local
1301 if ((mclk_edc_wr_enable_threshold != 0) && in iceland_populate_single_memory_level()
1302 (memory_clock > mclk_edc_wr_enable_threshold)) { in iceland_populate_single_memory_level()
Dci_smumgr.c1184 uint32_t mclk_edc_wr_enable_threshold = 40000; in ci_populate_single_memory_level() local
1256 if ((mclk_edc_wr_enable_threshold != 0) && in ci_populate_single_memory_level()
1257 (memory_clock > mclk_edc_wr_enable_threshold)) { in ci_populate_single_memory_level()
Dtonga_smumgr.c968 uint32_t mclk_edc_wr_enable_threshold = 40000; in tonga_populate_single_memory_level() local
1041 if ((mclk_edc_wr_enable_threshold != 0) && in tonga_populate_single_memory_level()
1042 (memory_clock > mclk_edc_wr_enable_threshold)) { in tonga_populate_single_memory_level()