| /drivers/fpga/ |
| D | fpga-mgr.c | 25 struct fpga_manager *mgr; member
28 static inline void fpga_mgr_fpga_remove(struct fpga_manager *mgr) in fpga_mgr_fpga_remove() argument
30 if (mgr->mops->fpga_remove) in fpga_mgr_fpga_remove()
31 mgr->mops->fpga_remove(mgr); in fpga_mgr_fpga_remove()
34 static inline enum fpga_mgr_states fpga_mgr_state(struct fpga_manager *mgr) in fpga_mgr_state() argument
36 if (mgr->mops->state) in fpga_mgr_state()
37 return mgr->mops->state(mgr); in fpga_mgr_state()
41 static inline u64 fpga_mgr_status(struct fpga_manager *mgr) in fpga_mgr_status() argument
43 if (mgr->mops->status) in fpga_mgr_status()
44 return mgr->mops->status(mgr); in fpga_mgr_status()
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| D | xilinx-spi.c | 30 static int get_done_gpio(struct fpga_manager *mgr) in get_done_gpio() argument
32 struct xilinx_spi_conf *conf = mgr->priv; in get_done_gpio()
38 dev_err(&mgr->dev, "Error reading DONE (%d)\n", ret); in get_done_gpio()
43 static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr) in xilinx_spi_state() argument
45 if (!get_done_gpio(mgr)) in xilinx_spi_state()
63 static int wait_for_init_b(struct fpga_manager *mgr, int value, in wait_for_init_b() argument
66 struct xilinx_spi_conf *conf = mgr->priv; in wait_for_init_b()
77 dev_err(&mgr->dev, "Error reading INIT_B (%d)\n", ret); in wait_for_init_b()
84 dev_err(&mgr->dev, "Timeout waiting for INIT_B to %s\n", in wait_for_init_b()
94 static int xilinx_spi_write_init(struct fpga_manager *mgr, in xilinx_spi_write_init() argument
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| D | altera-cvp.c | 75 struct fpga_manager *mgr; member
90 int (*wait_credit)(struct fpga_manager *mgr, u32 blocks);
117 static enum fpga_mgr_states altera_cvp_state(struct fpga_manager *mgr) in altera_cvp_state() argument
119 struct altera_cvp_conf *conf = mgr->priv; in altera_cvp_state()
182 static int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes) in altera_cvp_chk_error() argument
184 struct altera_cvp_conf *conf = mgr->priv; in altera_cvp_chk_error()
191 dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n", in altera_cvp_chk_error()
229 static int altera_cvp_v2_wait_for_credit(struct fpga_manager *mgr, in altera_cvp_v2_wait_for_credit() argument
233 struct altera_cvp_conf *conf = mgr->priv; in altera_cvp_v2_wait_for_credit()
249 ret = altera_cvp_chk_error(mgr, blocks * ALTERA_CVP_V2_SIZE); in altera_cvp_v2_wait_for_credit()
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| D | altera-pr-ip-core.c | 32 static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr) in alt_pr_fpga_state() argument
34 struct alt_pr_priv *priv = mgr->priv; in alt_pr_fpga_state()
72 dev_err(&mgr->dev, "encountered error code %d (%s) in %s()\n", in alt_pr_fpga_state()
77 static int alt_pr_fpga_write_init(struct fpga_manager *mgr, in alt_pr_fpga_write_init() argument
81 struct alt_pr_priv *priv = mgr->priv; in alt_pr_fpga_write_init()
85 dev_err(&mgr->dev, "%s Partial Reconfiguration flag not set\n", in alt_pr_fpga_write_init()
93 dev_err(&mgr->dev, in alt_pr_fpga_write_init()
104 static int alt_pr_fpga_write(struct fpga_manager *mgr, const char *buf, in alt_pr_fpga_write() argument
107 struct alt_pr_priv *priv = mgr->priv; in alt_pr_fpga_write()
138 if (alt_pr_fpga_state(mgr) == FPGA_MGR_STATE_WRITE_ERR) in alt_pr_fpga_write()
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| D | stratix10-soc.c | 71 static bool s10_free_buffers(struct fpga_manager *mgr) in s10_free_buffers() argument
73 struct s10_priv *priv = mgr->priv; in s10_free_buffers()
98 static uint s10_free_buffer_count(struct fpga_manager *mgr) in s10_free_buffer_count() argument
100 struct s10_priv *priv = mgr->priv; in s10_free_buffer_count()
174 static int s10_ops_write_init(struct fpga_manager *mgr, in s10_ops_write_init() argument
178 struct s10_priv *priv = mgr->priv; in s10_ops_write_init()
217 s10_free_buffers(mgr); in s10_ops_write_init()
239 static int s10_send_buf(struct fpga_manager *mgr, const char *buf, size_t count) in s10_send_buf() argument
241 struct s10_priv *priv = mgr->priv; in s10_send_buf()
277 static int s10_ops_write(struct fpga_manager *mgr, const char *buf, in s10_ops_write() argument
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| D | dfl-fme-region.c | 36 struct fpga_manager *mgr; in fme_region_probe() local
39 mgr = fpga_mgr_get(&pdata->mgr->dev); in fme_region_probe()
40 if (IS_ERR(mgr)) in fme_region_probe()
43 info.mgr = mgr; in fme_region_probe()
44 info.compat_id = mgr->compat_id; in fme_region_probe()
60 fpga_mgr_put(mgr); in fme_region_probe()
67 struct fpga_manager *mgr = region->mgr; in fme_region_remove() local
70 fpga_mgr_put(mgr); in fme_region_remove()
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| D | zynq-fpga.c | 251 static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, in zynq_fpga_ops_write_init() argument
259 priv = mgr->priv; in zynq_fpga_ops_write_init()
269 dev_err(&mgr->dev, in zynq_fpga_ops_write_init()
279 dev_err(&mgr->dev, in zynq_fpga_ops_write_init()
312 dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n"); in zynq_fpga_ops_write_init()
326 dev_err(&mgr->dev, "Timeout waiting for !PCFG_INIT\n"); in zynq_fpga_ops_write_init()
340 dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n"); in zynq_fpga_ops_write_init()
365 dev_err(&mgr->dev, "DMA command queue not right\n"); in zynq_fpga_ops_write_init()
384 static int zynq_fpga_ops_write(struct fpga_manager *mgr, struct sg_table *sgt) in zynq_fpga_ops_write() argument
395 priv = mgr->priv; in zynq_fpga_ops_write()
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| D | altera-ps-spi.c | 88 static enum fpga_mgr_states altera_ps_state(struct fpga_manager *mgr) in altera_ps_state() argument
90 struct altera_ps_conf *conf = mgr->priv; in altera_ps_state()
106 static int altera_ps_write_init(struct fpga_manager *mgr, in altera_ps_write_init() argument
110 struct altera_ps_conf *conf = mgr->priv; in altera_ps_write_init()
117 dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); in altera_ps_write_init()
127 dev_err(&mgr->dev, "Status pin failed to show a reset\n"); in altera_ps_write_init()
149 dev_err(&mgr->dev, "Status pin not ready.\n"); in altera_ps_write_init()
175 static int altera_ps_write(struct fpga_manager *mgr, const char *buf, in altera_ps_write() argument
178 struct altera_ps_conf *conf = mgr->priv; in altera_ps_write()
191 dev_err(&mgr->dev, "spi error in firmware write: %d\n", in altera_ps_write()
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| D | socfpga-a10.c | 203 static int socfpga_a10_fpga_set_cdratio(struct fpga_manager *mgr, in socfpga_a10_fpga_set_cdratio() argument
207 struct a10_fpga_priv *priv = mgr->priv; in socfpga_a10_fpga_set_cdratio()
272 static int socfpga_a10_fpga_write_init(struct fpga_manager *mgr, in socfpga_a10_fpga_write_init() argument
276 struct a10_fpga_priv *priv = mgr->priv; in socfpga_a10_fpga_write_init()
291 dev_dbg(&mgr->dev, "Fail: invalid msel=%d\n", msel); in socfpga_a10_fpga_write_init()
306 ret = socfpga_a10_fpga_set_cdratio(mgr, cfg_width, buf, count); in socfpga_a10_fpga_write_init()
354 static int socfpga_a10_fpga_write(struct fpga_manager *mgr, const char *buf, in socfpga_a10_fpga_write() argument
357 struct a10_fpga_priv *priv = mgr->priv; in socfpga_a10_fpga_write()
391 static int socfpga_a10_fpga_write_complete(struct fpga_manager *mgr, in socfpga_a10_fpga_write_complete() argument
394 struct a10_fpga_priv *priv = mgr->priv; in socfpga_a10_fpga_write_complete()
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| D | machxo2-spi.c | 135 static int machxo2_cleanup(struct fpga_manager *mgr) in machxo2_cleanup() argument
137 struct spi_device *spi = mgr->priv; in machxo2_cleanup()
169 dev_err(&mgr->dev, "Cleanup failed\n"); in machxo2_cleanup()
174 static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr) in machxo2_spi_state() argument
176 struct spi_device *spi = mgr->priv; in machxo2_spi_state()
187 static int machxo2_write_init(struct fpga_manager *mgr, in machxo2_write_init() argument
191 struct spi_device *spi = mgr->priv; in machxo2_write_init()
201 dev_err(&mgr->dev, in machxo2_write_init()
247 dev_err(&mgr->dev, "Error during FPGA init.\n"); in machxo2_write_init()
252 static int machxo2_write(struct fpga_manager *mgr, const char *buf, in machxo2_write() argument
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| D | microchip-spi.c | 87 static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr) in mpf_ops_state() argument
89 struct mpf_priv *priv = mgr->priv; in mpf_ops_state()
102 static int mpf_ops_parse_header(struct fpga_manager *mgr, in mpf_ops_parse_header() argument
114 dev_err(&mgr->dev, "Image buffer is not provided\n"); in mpf_ops_parse_header()
168 dev_err(&mgr->dev, "Failed to parse header look-up table\n"); in mpf_ops_parse_header()
248 static int mpf_ops_write_init(struct fpga_manager *mgr, in mpf_ops_write_init() argument
254 struct mpf_priv *priv = mgr->priv; in mpf_ops_write_init()
255 struct device *dev = &mgr->dev; in mpf_ops_write_init()
283 static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count) in mpf_ops_write() argument
286 struct mpf_priv *priv = mgr->priv; in mpf_ops_write()
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| D | dfl-fme-pr.c | 176 struct platform_device *mgr, *fme = pdata->dev; in dfl_fme_create_mgr() local
189 mgr = platform_device_alloc(DFL_FPGA_FME_MGR, fme->id); in dfl_fme_create_mgr()
190 if (!mgr) in dfl_fme_create_mgr()
193 mgr->dev.parent = &fme->dev; in dfl_fme_create_mgr()
195 ret = platform_device_add_data(mgr, &mgr_pdata, sizeof(mgr_pdata)); in dfl_fme_create_mgr()
199 ret = platform_device_add(mgr); in dfl_fme_create_mgr()
203 return mgr; in dfl_fme_create_mgr()
206 platform_device_put(mgr); in dfl_fme_create_mgr()
218 platform_device_unregister(priv->mgr); in dfl_fme_destroy_mgr()
302 struct platform_device *mgr, in dfl_fme_create_region() argument
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | manager-sysfs.c | 23 static ssize_t manager_name_show(struct omap_overlay_manager *mgr, char *buf) in manager_name_show() argument
25 return sysfs_emit(buf, "%s\n", mgr->name); in manager_name_show()
28 static ssize_t manager_display_show(struct omap_overlay_manager *mgr, char *buf) in manager_display_show() argument
30 struct omap_dss_device *dssdev = mgr->get_device(mgr); in manager_display_show()
43 static ssize_t manager_display_store(struct omap_overlay_manager *mgr, in manager_display_store() argument
77 old_dssdev = mgr->get_device(mgr); in manager_display_store()
95 old_dssdev = mgr->get_device(mgr); in manager_display_store()
102 r = mgr->apply(mgr); in manager_display_store()
116 static ssize_t manager_default_color_show(struct omap_overlay_manager *mgr, in manager_default_color_show() argument
121 mgr->get_manager_info(mgr, &info); in manager_default_color_show()
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| D | apply.c | 123 static struct mgr_priv_data *get_mgr_priv(struct omap_overlay_manager *mgr) in get_mgr_priv() argument
125 return &dss_data.mgr_priv_data_array[mgr->id]; in get_mgr_priv()
188 static bool mgr_manual_update(struct omap_overlay_manager *mgr) in mgr_manual_update() argument
190 struct mgr_priv_data *mp = get_mgr_priv(mgr); in mgr_manual_update()
195 static int dss_check_settings_low(struct omap_overlay_manager *mgr, in dss_check_settings_low() argument
205 mp = get_mgr_priv(mgr); in dss_check_settings_low()
216 list_for_each_entry(ovl, &mgr->overlays, list) { in dss_check_settings_low()
229 return dss_mgr_check(mgr, mi, &mp->timings, &mp->lcd_config, ois); in dss_check_settings_low()
235 static int dss_check_settings(struct omap_overlay_manager *mgr) in dss_check_settings() argument
237 return dss_check_settings_low(mgr, false); in dss_check_settings()
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| D | manager.c | 40 struct omap_overlay_manager *mgr = &managers[i]; in dss_init_overlay_managers() local
44 mgr->name = "lcd"; in dss_init_overlay_managers()
45 mgr->id = OMAP_DSS_CHANNEL_LCD; in dss_init_overlay_managers()
48 mgr->name = "tv"; in dss_init_overlay_managers()
49 mgr->id = OMAP_DSS_CHANNEL_DIGIT; in dss_init_overlay_managers()
52 mgr->name = "lcd2"; in dss_init_overlay_managers()
53 mgr->id = OMAP_DSS_CHANNEL_LCD2; in dss_init_overlay_managers()
56 mgr->name = "lcd3"; in dss_init_overlay_managers()
57 mgr->id = OMAP_DSS_CHANNEL_LCD3; in dss_init_overlay_managers()
61 mgr->supported_displays = in dss_init_overlay_managers()
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| D | output.c | 164 struct omap_overlay_manager *mgr; in omapdss_find_mgr_from_display() local
171 mgr = out->manager; in omapdss_find_mgr_from_display()
175 return mgr; in omapdss_find_mgr_from_display()
198 int dss_mgr_connect(struct omap_overlay_manager *mgr, in dss_mgr_connect() argument
201 return dss_mgr_ops->connect(mgr, dst); in dss_mgr_connect()
205 void dss_mgr_disconnect(struct omap_overlay_manager *mgr, in dss_mgr_disconnect() argument
208 dss_mgr_ops->disconnect(mgr, dst); in dss_mgr_disconnect()
212 void dss_mgr_set_timings(struct omap_overlay_manager *mgr, in dss_mgr_set_timings() argument
215 dss_mgr_ops->set_timings(mgr, timings); in dss_mgr_set_timings()
219 void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr, in dss_mgr_set_lcd_config() argument
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| D | dss.h | 210 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
212 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
214 int dss_mgr_check(struct omap_overlay_manager *mgr,
229 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
231 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
236 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
485 int (*connect)(struct omap_overlay_manager *mgr,
487 void (*disconnect)(struct omap_overlay_manager *mgr,
490 void (*start_update)(struct omap_overlay_manager *mgr);
491 int (*enable)(struct omap_overlay_manager *mgr);
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| /drivers/isdn/mISDN/ |
| D | tei.c | 72 struct manager *mgr = fi->userdata; in da_debug() local
84 printk(KERN_DEBUG "mgr(%d): %pV\n", mgr->ch.st->dev->id, &vaf); in da_debug()
92 struct manager *mgr = fi->userdata; in da_activate() local
95 mISDN_FsmDelTimer(&mgr->datimer, 1); in da_activate()
108 struct manager *mgr = fi->userdata; in da_deactivate() local
112 read_lock_irqsave(&mgr->lock, flags); in da_deactivate()
113 list_for_each_entry(l2, &mgr->layer2, list) { in da_deactivate()
116 read_unlock_irqrestore(&mgr->lock, flags); in da_deactivate()
120 read_unlock_irqrestore(&mgr->lock, flags); in da_deactivate()
122 if (!test_bit(OPTION_L1_HOLD, &mgr->options)) { in da_deactivate()
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| /drivers/gpu/drm/display/ |
| D | drm_dp_mst_topology.c | 65 static bool dump_dp_payload_table(struct drm_dp_mst_topology_mgr *mgr,
70 static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr,
73 static int drm_dp_send_dpcd_read(struct drm_dp_mst_topology_mgr *mgr,
76 static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr,
80 static int drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr,
84 drm_dp_send_clear_payload_id_table(struct drm_dp_mst_topology_mgr *mgr,
87 static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr,
90 static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr,
95 static void drm_dp_mst_kick_tx(struct drm_dp_mst_topology_mgr *mgr);
292 static bool drm_dp_decode_sideband_msg_hdr(const struct drm_dp_mst_topology_mgr *mgr, in drm_dp_decode_sideband_msg_hdr() argument
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_vram_mgr.c | 48 to_amdgpu_device(struct amdgpu_vram_mgr *mgr) in to_amdgpu_device() argument
50 return container_of(mgr, struct amdgpu_device, mman.vram_mgr); in to_amdgpu_device()
271 struct amdgpu_vram_mgr *mgr = to_vram_mgr(man); in amdgpu_vram_mgr_do_reserve() local
272 struct amdgpu_device *adev = to_amdgpu_device(mgr); in amdgpu_vram_mgr_do_reserve()
273 struct drm_buddy *mm = &mgr->mm; in amdgpu_vram_mgr_do_reserve()
278 list_for_each_entry_safe(rsv, temp, &mgr->reservations_pending, blocks) { in amdgpu_vram_mgr_do_reserve()
292 atomic64_add(vis_usage, &mgr->vis_usage); in amdgpu_vram_mgr_do_reserve()
296 list_move(&rsv->blocks, &mgr->reserved_pages); in amdgpu_vram_mgr_do_reserve()
309 int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr, in amdgpu_vram_mgr_reserve_range() argument
324 mutex_lock(&mgr->lock); in amdgpu_vram_mgr_reserve_range()
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| D | amdgpu_ctx.c | 139 struct amdgpu_device *adev = ctx->mgr->adev; in amdgpu_ctx_get_hw_prio()
206 struct amdgpu_device *adev = ctx->mgr->adev; in amdgpu_ctx_init_entity()
279 struct amdgpu_device *adev = ctx->mgr->adev; in amdgpu_ctx_get_stable_pstate()
304 static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority, in amdgpu_ctx_init() argument
317 ctx->mgr = mgr; in amdgpu_ctx_init()
320 ctx->reset_counter = atomic_read(&mgr->adev->gpu_reset_counter); in amdgpu_ctx_init()
322 ctx->vram_lost_counter = atomic_read(&mgr->adev->vram_lost_counter); in amdgpu_ctx_init()
330 if (mgr->adev->pm.stable_pstate_ctx) in amdgpu_ctx_init()
331 ctx->stable_pstate = mgr->adev->pm.stable_pstate_ctx->stable_pstate; in amdgpu_ctx_init()
341 struct amdgpu_device *adev = ctx->mgr->adev; in amdgpu_ctx_set_stable_pstate()
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| D | amdgpu_gtt_mgr.c | 118 struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man); in amdgpu_gtt_mgr_new() local
135 spin_lock(&mgr->lock); in amdgpu_gtt_mgr_new()
136 r = drm_mm_insert_node_in_range(&mgr->mm, &node->mm_nodes[0], in amdgpu_gtt_mgr_new()
140 spin_unlock(&mgr->lock); in amdgpu_gtt_mgr_new()
172 struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man); in amdgpu_gtt_mgr_del() local
174 spin_lock(&mgr->lock); in amdgpu_gtt_mgr_del()
177 spin_unlock(&mgr->lock); in amdgpu_gtt_mgr_del()
190 void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr) in amdgpu_gtt_mgr_recover() argument
196 adev = container_of(mgr, typeof(*adev), mman.gtt_mgr); in amdgpu_gtt_mgr_recover()
197 spin_lock(&mgr->lock); in amdgpu_gtt_mgr_recover()
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| /drivers/gpu/drm/lima/ |
| D | lima_ctx.c | 9 int lima_ctx_create(struct lima_device *dev, struct lima_ctx_mgr *mgr, u32 *id) in lima_ctx_create() argument
26 err = xa_alloc(&mgr->handles, id, ctx, xa_limit_32b, GFP_KERNEL); in lima_ctx_create()
52 int lima_ctx_free(struct lima_ctx_mgr *mgr, u32 id) in lima_ctx_free() argument
57 mutex_lock(&mgr->lock); in lima_ctx_free()
58 ctx = xa_erase(&mgr->handles, id); in lima_ctx_free()
63 mutex_unlock(&mgr->lock); in lima_ctx_free()
67 struct lima_ctx *lima_ctx_get(struct lima_ctx_mgr *mgr, u32 id) in lima_ctx_get() argument
71 mutex_lock(&mgr->lock); in lima_ctx_get()
72 ctx = xa_load(&mgr->handles, id); in lima_ctx_get()
75 mutex_unlock(&mgr->lock); in lima_ctx_get()
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| /drivers/crypto/ccree/ |
| D | cc_request_mgr.c | 333 struct cc_req_mgr_handle *mgr = drvdata->request_mgr_handle; in cc_enqueue_backlog() local
336 spin_lock_bh(&mgr->bl_lock); in cc_enqueue_backlog()
337 list_add_tail(&bli->list, &mgr->backlog); in cc_enqueue_backlog()
338 ++mgr->bl_len; in cc_enqueue_backlog()
339 dev_dbg(dev, "+++bl len: %d\n", mgr->bl_len); in cc_enqueue_backlog()
340 spin_unlock_bh(&mgr->bl_lock); in cc_enqueue_backlog()
341 tasklet_schedule(&mgr->comptask); in cc_enqueue_backlog()
346 struct cc_req_mgr_handle *mgr = drvdata->request_mgr_handle; in cc_proc_backlog() local
353 spin_lock(&mgr->bl_lock); in cc_proc_backlog()
355 while (mgr->bl_len) { in cc_proc_backlog()
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| /drivers/gpu/drm/ |
| D | drm_vma_manager.c | 85 void drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr, in drm_vma_offset_manager_init() argument
88 rwlock_init(&mgr->vm_lock); in drm_vma_offset_manager_init()
89 drm_mm_init(&mgr->vm_addr_space_mm, page_offset, size); in drm_vma_offset_manager_init()
104 void drm_vma_offset_manager_destroy(struct drm_vma_offset_manager *mgr) in drm_vma_offset_manager_destroy() argument
106 drm_mm_takedown(&mgr->vm_addr_space_mm); in drm_vma_offset_manager_destroy()
140 struct drm_vma_offset_node *drm_vma_offset_lookup_locked(struct drm_vma_offset_manager *mgr, in drm_vma_offset_lookup_locked() argument
148 iter = mgr->vm_addr_space_mm.interval_tree.rb_root.rb_node; in drm_vma_offset_lookup_locked()
201 int drm_vma_offset_add(struct drm_vma_offset_manager *mgr, in drm_vma_offset_add() argument
206 write_lock(&mgr->vm_lock); in drm_vma_offset_add()
209 ret = drm_mm_insert_node(&mgr->vm_addr_space_mm, in drm_vma_offset_add()
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