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1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3 
4 #ifndef _MLXSW_REG_H
5 #define _MLXSW_REG_H
6 
7 #include <linux/kernel.h>
8 #include <linux/string.h>
9 #include <linux/bitops.h>
10 #include <linux/if_vlan.h>
11 
12 #include "item.h"
13 #include "port.h"
14 
15 struct mlxsw_reg_info {
16 	u16 id;
17 	u16 len; /* In u8 */
18 	const char *name;
19 };
20 
21 #define MLXSW_REG_DEFINE(_name, _id, _len)				\
22 static const struct mlxsw_reg_info mlxsw_reg_##_name = {		\
23 	.id = _id,							\
24 	.len = _len,							\
25 	.name = #_name,							\
26 }
27 
28 #define MLXSW_REG(type) (&mlxsw_reg_##type)
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
31 
32 /* SGCR - Switch General Configuration Register
33  * --------------------------------------------
34  * This register is used for configuration of the switch capabilities.
35  */
36 #define MLXSW_REG_SGCR_ID 0x2000
37 #define MLXSW_REG_SGCR_LEN 0x10
38 
39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
40 
41 /* reg_sgcr_llb
42  * Link Local Broadcast (Default=0)
43  * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
44  * packets and ignore the IGMP snooping entries.
45  * Access: RW
46  */
47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
48 
mlxsw_reg_sgcr_pack(char * payload,bool llb)49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
50 {
51 	MLXSW_REG_ZERO(sgcr, payload);
52 	mlxsw_reg_sgcr_llb_set(payload, !!llb);
53 }
54 
55 /* SPAD - Switch Physical Address Register
56  * ---------------------------------------
57  * The SPAD register configures the switch physical MAC address.
58  */
59 #define MLXSW_REG_SPAD_ID 0x2002
60 #define MLXSW_REG_SPAD_LEN 0x10
61 
62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
63 
64 /* reg_spad_base_mac
65  * Base MAC address for the switch partitions.
66  * Per switch partition MAC address is equal to:
67  * base_mac + swid
68  * Access: RW
69  */
70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
71 
72 /* SSPR - Switch System Port Record Register
73  * -----------------------------------------
74  * Configures the system port to local port mapping.
75  */
76 #define MLXSW_REG_SSPR_ID 0x2008
77 #define MLXSW_REG_SSPR_LEN 0x8
78 
79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
80 
81 /* reg_sspr_m
82  * Master - if set, then the record describes the master system port.
83  * This is needed in case a local port is mapped into several system ports
84  * (for multipathing). That number will be reported as the source system
85  * port when packets are forwarded to the CPU. Only one master port is allowed
86  * per local port.
87  *
88  * Note: Must be set for Spectrum.
89  * Access: RW
90  */
91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
92 
93 /* reg_sspr_local_port
94  * Local port number.
95  *
96  * Access: RW
97  */
98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12);
99 
100 /* reg_sspr_system_port
101  * Unique identifier within the stacking domain that represents all the ports
102  * that are available in the system (external ports).
103  *
104  * Currently, only single-ASIC configurations are supported, so we default to
105  * 1:1 mapping between system ports and local ports.
106  * Access: Index
107  */
108 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
109 
mlxsw_reg_sspr_pack(char * payload,u16 local_port)110 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port)
111 {
112 	MLXSW_REG_ZERO(sspr, payload);
113 	mlxsw_reg_sspr_m_set(payload, 1);
114 	mlxsw_reg_sspr_local_port_set(payload, local_port);
115 	mlxsw_reg_sspr_system_port_set(payload, local_port);
116 }
117 
118 /* SFDAT - Switch Filtering Database Aging Time
119  * --------------------------------------------
120  * Controls the Switch aging time. Aging time is able to be set per Switch
121  * Partition.
122  */
123 #define MLXSW_REG_SFDAT_ID 0x2009
124 #define MLXSW_REG_SFDAT_LEN 0x8
125 
126 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
127 
128 /* reg_sfdat_swid
129  * Switch partition ID.
130  * Access: Index
131  */
132 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
133 
134 /* reg_sfdat_age_time
135  * Aging time in seconds
136  * Min - 10 seconds
137  * Max - 1,000,000 seconds
138  * Default is 300 seconds.
139  * Access: RW
140  */
141 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
142 
mlxsw_reg_sfdat_pack(char * payload,u32 age_time)143 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
144 {
145 	MLXSW_REG_ZERO(sfdat, payload);
146 	mlxsw_reg_sfdat_swid_set(payload, 0);
147 	mlxsw_reg_sfdat_age_time_set(payload, age_time);
148 }
149 
150 /* SFD - Switch Filtering Database
151  * -------------------------------
152  * The following register defines the access to the filtering database.
153  * The register supports querying, adding, removing and modifying the database.
154  * The access is optimized for bulk updates in which case more than one
155  * FDB record is present in the same command.
156  */
157 #define MLXSW_REG_SFD_ID 0x200A
158 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
159 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
160 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
161 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN +	\
162 			   MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
163 
164 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
165 
166 /* reg_sfd_swid
167  * Switch partition ID for queries. Reserved on Write.
168  * Access: Index
169  */
170 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
171 
172 enum mlxsw_reg_sfd_op {
173 	/* Dump entire FDB a (process according to record_locator) */
174 	MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
175 	/* Query records by {MAC, VID/FID} value */
176 	MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
177 	/* Query and clear activity. Query records by {MAC, VID/FID} value */
178 	MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
179 	/* Test. Response indicates if each of the records could be
180 	 * added to the FDB.
181 	 */
182 	MLXSW_REG_SFD_OP_WRITE_TEST = 0,
183 	/* Add/modify. Aged-out records cannot be added. This command removes
184 	 * the learning notification of the {MAC, VID/FID}. Response includes
185 	 * the entries that were added to the FDB.
186 	 */
187 	MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
188 	/* Remove record by {MAC, VID/FID}. This command also removes
189 	 * the learning notification and aged-out notifications
190 	 * of the {MAC, VID/FID}. The response provides current (pre-removal)
191 	 * entries as non-aged-out.
192 	 */
193 	MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
194 	/* Remove learned notification by {MAC, VID/FID}. The response provides
195 	 * the removed learning notification.
196 	 */
197 	MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
198 };
199 
200 /* reg_sfd_op
201  * Operation.
202  * Access: OP
203  */
204 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
205 
206 /* reg_sfd_record_locator
207  * Used for querying the FDB. Use record_locator=0 to initiate the
208  * query. When a record is returned, a new record_locator is
209  * returned to be used in the subsequent query.
210  * Reserved for database update.
211  * Access: Index
212  */
213 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
214 
215 /* reg_sfd_num_rec
216  * Request: Number of records to read/add/modify/remove
217  * Response: Number of records read/added/replaced/removed
218  * See above description for more details.
219  * Ranges 0..64
220  * Access: RW
221  */
222 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
223 
mlxsw_reg_sfd_pack(char * payload,enum mlxsw_reg_sfd_op op,u32 record_locator)224 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
225 				      u32 record_locator)
226 {
227 	MLXSW_REG_ZERO(sfd, payload);
228 	mlxsw_reg_sfd_op_set(payload, op);
229 	mlxsw_reg_sfd_record_locator_set(payload, record_locator);
230 }
231 
232 /* reg_sfd_rec_swid
233  * Switch partition ID.
234  * Access: Index
235  */
236 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
237 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
238 
239 enum mlxsw_reg_sfd_rec_type {
240 	MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
241 	MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
242 	MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
243 	MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
244 };
245 
246 /* reg_sfd_rec_type
247  * FDB record type.
248  * Access: RW
249  */
250 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
251 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
252 
253 enum mlxsw_reg_sfd_rec_policy {
254 	/* Replacement disabled, aging disabled. */
255 	MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
256 	/* (mlag remote): Replacement enabled, aging disabled,
257 	 * learning notification enabled on this port.
258 	 */
259 	MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
260 	/* (ingress device): Replacement enabled, aging enabled. */
261 	MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
262 };
263 
264 /* reg_sfd_rec_policy
265  * Policy.
266  * Access: RW
267  */
268 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
269 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
270 
271 /* reg_sfd_rec_a
272  * Activity. Set for new static entries. Set for static entries if a frame SMAC
273  * lookup hits on the entry.
274  * To clear the a bit, use "query and clear activity" op.
275  * Access: RO
276  */
277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
278 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
279 
280 /* reg_sfd_rec_mac
281  * MAC address.
282  * Access: Index
283  */
284 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
285 		       MLXSW_REG_SFD_REC_LEN, 0x02);
286 
287 enum mlxsw_reg_sfd_rec_action {
288 	/* forward */
289 	MLXSW_REG_SFD_REC_ACTION_NOP = 0,
290 	/* forward and trap, trap_id is FDB_TRAP */
291 	MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
292 	/* trap and do not forward, trap_id is FDB_TRAP */
293 	MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
294 	/* forward to IP router */
295 	MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
296 	MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
297 };
298 
299 /* reg_sfd_rec_action
300  * Action to apply on the packet.
301  * Note: Dynamic entries can only be configured with NOP action.
302  * Access: RW
303  */
304 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
305 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
306 
307 /* reg_sfd_uc_sub_port
308  * VEPA channel on local port.
309  * Valid only if local port is a non-stacking port. Must be 0 if multichannel
310  * VEPA is not enabled.
311  * Access: RW
312  */
313 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
314 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
315 
316 /* reg_sfd_uc_set_vid
317  * Set VID.
318  * 0 - Do not update VID.
319  * 1 - Set VID.
320  * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid.
321  * Access: RW
322  *
323  * Note: Reserved when legacy bridge model is used.
324  */
325 MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,
326 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
327 
328 /* reg_sfd_uc_fid_vid
329  * Filtering ID or VLAN ID
330  * For SwitchX and SwitchX-2:
331  * - Dynamic entries (policy 2,3) use FID
332  * - Static entries (policy 0) use VID
333  * - When independent learning is configured, VID=FID
334  * For Spectrum: use FID for both Dynamic and Static entries.
335  * VID should not be used.
336  * Access: Index
337  */
338 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
339 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
340 
341 /* reg_sfd_uc_vid
342  * New VID when set_vid=1.
343  * Access: RW
344  *
345  * Note: Reserved when legacy bridge model is used and when set_vid=0.
346  */
347 MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
348 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
349 
350 /* reg_sfd_uc_system_port
351  * Unique port identifier for the final destination of the packet.
352  * Access: RW
353  */
354 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
355 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
356 
mlxsw_reg_sfd_rec_pack(char * payload,int rec_index,enum mlxsw_reg_sfd_rec_type rec_type,const char * mac,enum mlxsw_reg_sfd_rec_action action)357 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
358 					  enum mlxsw_reg_sfd_rec_type rec_type,
359 					  const char *mac,
360 					  enum mlxsw_reg_sfd_rec_action action)
361 {
362 	u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
363 
364 	if (rec_index >= num_rec)
365 		mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
366 	mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
367 	mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
368 	mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
369 	mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
370 }
371 
mlxsw_reg_sfd_uc_pack(char * payload,int rec_index,enum mlxsw_reg_sfd_rec_policy policy,const char * mac,u16 fid_vid,u16 vid,enum mlxsw_reg_sfd_rec_action action,u16 local_port)372 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
373 					 enum mlxsw_reg_sfd_rec_policy policy,
374 					 const char *mac, u16 fid_vid, u16 vid,
375 					 enum mlxsw_reg_sfd_rec_action action,
376 					 u16 local_port)
377 {
378 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
379 			       MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
380 	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
381 	mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
382 	mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
383 	mlxsw_reg_sfd_uc_set_vid_set(payload, rec_index, vid ? true : false);
384 	mlxsw_reg_sfd_uc_vid_set(payload, rec_index, vid);
385 	mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
386 }
387 
388 /* reg_sfd_uc_lag_sub_port
389  * LAG sub port.
390  * Must be 0 if multichannel VEPA is not enabled.
391  * Access: RW
392  */
393 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
394 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
395 
396 /* reg_sfd_uc_lag_set_vid
397  * Set VID.
398  * 0 - Do not update VID.
399  * 1 - Set VID.
400  * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid.
401  * Access: RW
402  *
403  * Note: Reserved when legacy bridge model is used.
404  */
405 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,
406 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
407 
408 /* reg_sfd_uc_lag_fid_vid
409  * Filtering ID or VLAN ID
410  * For SwitchX and SwitchX-2:
411  * - Dynamic entries (policy 2,3) use FID
412  * - Static entries (policy 0) use VID
413  * - When independent learning is configured, VID=FID
414  * For Spectrum: use FID for both Dynamic and Static entries.
415  * VID should not be used.
416  * Access: Index
417  */
418 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
419 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
420 
421 /* reg_sfd_uc_lag_lag_vid
422  * New vlan ID.
423  * Access: RW
424  *
425  * Note: Reserved when legacy bridge model is used and set_vid=0.
426  */
427 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
428 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
429 
430 /* reg_sfd_uc_lag_lag_id
431  * LAG Identifier - pointer into the LAG descriptor table.
432  * Access: RW
433  */
434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
435 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
436 
437 static inline void
mlxsw_reg_sfd_uc_lag_pack(char * payload,int rec_index,enum mlxsw_reg_sfd_rec_policy policy,const char * mac,u16 fid_vid,enum mlxsw_reg_sfd_rec_action action,u16 lag_vid,u16 lag_id)438 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
439 			  enum mlxsw_reg_sfd_rec_policy policy,
440 			  const char *mac, u16 fid_vid,
441 			  enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
442 			  u16 lag_id)
443 {
444 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
445 			       MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
446 			       mac, action);
447 	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
448 	mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
449 	mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
450 	mlxsw_reg_sfd_uc_lag_set_vid_set(payload, rec_index, true);
451 	mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
452 	mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
453 }
454 
455 /* reg_sfd_mc_pgi
456  *
457  * Multicast port group index - index into the port group table.
458  * Value 0x1FFF indicates the pgi should point to the MID entry.
459  * For Spectrum this value must be set to 0x1FFF
460  * Access: RW
461  */
462 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
463 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
464 
465 /* reg_sfd_mc_fid_vid
466  *
467  * Filtering ID or VLAN ID
468  * Access: Index
469  */
470 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
471 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
472 
473 /* reg_sfd_mc_mid
474  *
475  * Multicast identifier - global identifier that represents the multicast
476  * group across all devices.
477  * Access: RW
478  */
479 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
480 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
481 
482 static inline void
mlxsw_reg_sfd_mc_pack(char * payload,int rec_index,const char * mac,u16 fid_vid,enum mlxsw_reg_sfd_rec_action action,u16 mid)483 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
484 		      const char *mac, u16 fid_vid,
485 		      enum mlxsw_reg_sfd_rec_action action, u16 mid)
486 {
487 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
488 			       MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
489 	mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
490 	mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
491 	mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
492 }
493 
494 /* reg_sfd_uc_tunnel_uip_msb
495  * When protocol is IPv4, the most significant byte of the underlay IPv4
496  * destination IP.
497  * When protocol is IPv6, reserved.
498  * Access: RW
499  */
500 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
501 		     8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
502 
503 /* reg_sfd_uc_tunnel_fid
504  * Filtering ID.
505  * Access: Index
506  */
507 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
508 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
509 
510 enum mlxsw_reg_sfd_uc_tunnel_protocol {
511 	MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
512 	MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
513 };
514 
515 /* reg_sfd_uc_tunnel_protocol
516  * IP protocol.
517  * Access: RW
518  */
519 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
520 		     1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
521 
522 /* reg_sfd_uc_tunnel_uip_lsb
523  * When protocol is IPv4, the least significant bytes of the underlay
524  * IPv4 destination IP.
525  * When protocol is IPv6, pointer to the underlay IPv6 destination IP
526  * which is configured by RIPS.
527  * Access: RW
528  */
529 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
530 		     24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
531 
532 static inline void
mlxsw_reg_sfd_uc_tunnel_pack(char * payload,int rec_index,enum mlxsw_reg_sfd_rec_policy policy,const char * mac,u16 fid,enum mlxsw_reg_sfd_rec_action action,enum mlxsw_reg_sfd_uc_tunnel_protocol proto)533 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
534 			     enum mlxsw_reg_sfd_rec_policy policy,
535 			     const char *mac, u16 fid,
536 			     enum mlxsw_reg_sfd_rec_action action,
537 			     enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
538 {
539 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
540 			       MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
541 			       action);
542 	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
543 	mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
544 	mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
545 }
546 
547 static inline void
mlxsw_reg_sfd_uc_tunnel_pack4(char * payload,int rec_index,enum mlxsw_reg_sfd_rec_policy policy,const char * mac,u16 fid,enum mlxsw_reg_sfd_rec_action action,u32 uip)548 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index,
549 			      enum mlxsw_reg_sfd_rec_policy policy,
550 			      const char *mac, u16 fid,
551 			      enum mlxsw_reg_sfd_rec_action action, u32 uip)
552 {
553 	mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
554 	mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
555 	mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid,
556 				     action,
557 				     MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4);
558 }
559 
560 static inline void
mlxsw_reg_sfd_uc_tunnel_pack6(char * payload,int rec_index,const char * mac,u16 fid,enum mlxsw_reg_sfd_rec_action action,u32 uip_ptr)561 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac,
562 			      u16 fid, enum mlxsw_reg_sfd_rec_action action,
563 			      u32 uip_ptr)
564 {
565 	mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr);
566 	/* Only static policy is supported for IPv6 unicast tunnel entry. */
567 	mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index,
568 				     MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY,
569 				     mac, fid, action,
570 				     MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6);
571 }
572 
573 enum mlxsw_reg_tunnel_port {
574 	MLXSW_REG_TUNNEL_PORT_NVE,
575 	MLXSW_REG_TUNNEL_PORT_VPLS,
576 	MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0,
577 	MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1,
578 };
579 
580 /* SFN - Switch FDB Notification Register
581  * -------------------------------------------
582  * The switch provides notifications on newly learned FDB entries and
583  * aged out entries. The notifications can be polled by software.
584  */
585 #define MLXSW_REG_SFN_ID 0x200B
586 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
587 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
588 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
589 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN +	\
590 			   MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
591 
592 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
593 
594 /* reg_sfn_swid
595  * Switch partition ID.
596  * Access: Index
597  */
598 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
599 
600 /* reg_sfn_end
601  * Forces the current session to end.
602  * Access: OP
603  */
604 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
605 
606 /* reg_sfn_num_rec
607  * Request: Number of learned notifications and aged-out notification
608  * records requested.
609  * Response: Number of notification records returned (must be smaller
610  * than or equal to the value requested)
611  * Ranges 0..64
612  * Access: OP
613  */
614 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
615 
mlxsw_reg_sfn_pack(char * payload)616 static inline void mlxsw_reg_sfn_pack(char *payload)
617 {
618 	MLXSW_REG_ZERO(sfn, payload);
619 	mlxsw_reg_sfn_swid_set(payload, 0);
620 	mlxsw_reg_sfn_end_set(payload, 0);
621 	mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
622 }
623 
624 /* reg_sfn_rec_swid
625  * Switch partition ID.
626  * Access: RO
627  */
628 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
629 		     MLXSW_REG_SFN_REC_LEN, 0x00, false);
630 
631 enum mlxsw_reg_sfn_rec_type {
632 	/* MAC addresses learned on a regular port. */
633 	MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
634 	/* MAC addresses learned on a LAG port. */
635 	MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
636 	/* Aged-out MAC address on a regular port. */
637 	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
638 	/* Aged-out MAC address on a LAG port. */
639 	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
640 	/* Learned unicast tunnel record. */
641 	MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
642 	/* Aged-out unicast tunnel record. */
643 	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
644 };
645 
646 /* reg_sfn_rec_type
647  * Notification record type.
648  * Access: RO
649  */
650 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
651 		     MLXSW_REG_SFN_REC_LEN, 0x00, false);
652 
653 /* reg_sfn_rec_mac
654  * MAC address.
655  * Access: RO
656  */
657 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
658 		       MLXSW_REG_SFN_REC_LEN, 0x02);
659 
660 /* reg_sfn_mac_sub_port
661  * VEPA channel on the local port.
662  * 0 if multichannel VEPA is not enabled.
663  * Access: RO
664  */
665 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
666 		     MLXSW_REG_SFN_REC_LEN, 0x08, false);
667 
668 /* reg_sfn_mac_fid
669  * Filtering identifier.
670  * Access: RO
671  */
672 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
673 		     MLXSW_REG_SFN_REC_LEN, 0x08, false);
674 
675 /* reg_sfn_mac_system_port
676  * Unique port identifier for the final destination of the packet.
677  * Access: RO
678  */
679 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
680 		     MLXSW_REG_SFN_REC_LEN, 0x0C, false);
681 
mlxsw_reg_sfn_mac_unpack(char * payload,int rec_index,char * mac,u16 * p_vid,u16 * p_local_port)682 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
683 					    char *mac, u16 *p_vid,
684 					    u16 *p_local_port)
685 {
686 	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
687 	*p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
688 	*p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
689 }
690 
691 /* reg_sfn_mac_lag_lag_id
692  * LAG ID (pointer into the LAG descriptor table).
693  * Access: RO
694  */
695 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
696 		     MLXSW_REG_SFN_REC_LEN, 0x0C, false);
697 
mlxsw_reg_sfn_mac_lag_unpack(char * payload,int rec_index,char * mac,u16 * p_vid,u16 * p_lag_id)698 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
699 						char *mac, u16 *p_vid,
700 						u16 *p_lag_id)
701 {
702 	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
703 	*p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
704 	*p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
705 }
706 
707 /* reg_sfn_uc_tunnel_uip_msb
708  * When protocol is IPv4, the most significant byte of the underlay IPv4
709  * address of the remote VTEP.
710  * When protocol is IPv6, reserved.
711  * Access: RO
712  */
713 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
714 		     8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
715 
716 enum mlxsw_reg_sfn_uc_tunnel_protocol {
717 	MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
718 	MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
719 };
720 
721 /* reg_sfn_uc_tunnel_protocol
722  * IP protocol.
723  * Access: RO
724  */
725 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
726 		     1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
727 
728 /* reg_sfn_uc_tunnel_uip_lsb
729  * When protocol is IPv4, the least significant bytes of the underlay
730  * IPv4 address of the remote VTEP.
731  * When protocol is IPv6, ipv6_id to be queried from TNIPSD.
732  * Access: RO
733  */
734 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
735 		     24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
736 
737 /* reg_sfn_uc_tunnel_port
738  * Tunnel port.
739  * Reserved on Spectrum.
740  * Access: RO
741  */
742 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
743 		     MLXSW_REG_SFN_REC_LEN, 0x10, false);
744 
745 static inline void
mlxsw_reg_sfn_uc_tunnel_unpack(char * payload,int rec_index,char * mac,u16 * p_fid,u32 * p_uip,enum mlxsw_reg_sfn_uc_tunnel_protocol * p_proto)746 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
747 			       u16 *p_fid, u32 *p_uip,
748 			       enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
749 {
750 	u32 uip_msb, uip_lsb;
751 
752 	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
753 	*p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
754 	uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
755 	uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
756 	*p_uip = uip_msb << 24 | uip_lsb;
757 	*p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
758 }
759 
760 /* SPMS - Switch Port MSTP/RSTP State Register
761  * -------------------------------------------
762  * Configures the spanning tree state of a physical port.
763  */
764 #define MLXSW_REG_SPMS_ID 0x200D
765 #define MLXSW_REG_SPMS_LEN 0x404
766 
767 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
768 
769 /* reg_spms_local_port
770  * Local port number.
771  * Access: Index
772  */
773 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12);
774 
775 enum mlxsw_reg_spms_state {
776 	MLXSW_REG_SPMS_STATE_NO_CHANGE,
777 	MLXSW_REG_SPMS_STATE_DISCARDING,
778 	MLXSW_REG_SPMS_STATE_LEARNING,
779 	MLXSW_REG_SPMS_STATE_FORWARDING,
780 };
781 
782 /* reg_spms_state
783  * Spanning tree state of each VLAN ID (VID) of the local port.
784  * 0 - Do not change spanning tree state (used only when writing).
785  * 1 - Discarding. No learning or forwarding to/from this port (default).
786  * 2 - Learning. Port is learning, but not forwarding.
787  * 3 - Forwarding. Port is learning and forwarding.
788  * Access: RW
789  */
790 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
791 
mlxsw_reg_spms_pack(char * payload,u16 local_port)792 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port)
793 {
794 	MLXSW_REG_ZERO(spms, payload);
795 	mlxsw_reg_spms_local_port_set(payload, local_port);
796 }
797 
mlxsw_reg_spms_vid_pack(char * payload,u16 vid,enum mlxsw_reg_spms_state state)798 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
799 					   enum mlxsw_reg_spms_state state)
800 {
801 	mlxsw_reg_spms_state_set(payload, vid, state);
802 }
803 
804 /* SPVID - Switch Port VID
805  * -----------------------
806  * The switch port VID configures the default VID for a port.
807  */
808 #define MLXSW_REG_SPVID_ID 0x200E
809 #define MLXSW_REG_SPVID_LEN 0x08
810 
811 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
812 
813 /* reg_spvid_tport
814  * Port is tunnel port.
815  * Reserved when SwitchX/-2 or Spectrum-1.
816  * Access: Index
817  */
818 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1);
819 
820 /* reg_spvid_local_port
821  * When tport = 0: Local port number. Not supported for CPU port.
822  * When tport = 1: Tunnel port.
823  * Access: Index
824  */
825 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12);
826 
827 /* reg_spvid_sub_port
828  * Virtual port within the physical port.
829  * Should be set to 0 when virtual ports are not enabled on the port.
830  * Access: Index
831  */
832 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
833 
834 /* reg_spvid_egr_et_set
835  * When VLAN is pushed at ingress (for untagged packets or for
836  * QinQ push mode) then the EtherType is decided at the egress port.
837  * Reserved when Spectrum-1.
838  * Access: RW
839  */
840 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1);
841 
842 /* reg_spvid_et_vlan
843  * EtherType used for when VLAN is pushed at ingress (for untagged
844  * packets or for QinQ push mode).
845  * 0: ether_type0 - (default)
846  * 1: ether_type1
847  * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2
848  * Ethertype IDs are configured by SVER.
849  * Reserved when egr_et_set = 1.
850  * Access: RW
851  */
852 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2);
853 
854 /* reg_spvid_pvid
855  * Port default VID
856  * Access: RW
857  */
858 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
859 
mlxsw_reg_spvid_pack(char * payload,u16 local_port,u16 pvid,u8 et_vlan)860 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid,
861 					u8 et_vlan)
862 {
863 	MLXSW_REG_ZERO(spvid, payload);
864 	mlxsw_reg_spvid_local_port_set(payload, local_port);
865 	mlxsw_reg_spvid_pvid_set(payload, pvid);
866 	mlxsw_reg_spvid_et_vlan_set(payload, et_vlan);
867 }
868 
869 /* SPVM - Switch Port VLAN Membership
870  * ----------------------------------
871  * The Switch Port VLAN Membership register configures the VLAN membership
872  * of a port in a VLAN denoted by VID. VLAN membership is managed per
873  * virtual port. The register can be used to add and remove VID(s) from a port.
874  */
875 #define MLXSW_REG_SPVM_ID 0x200F
876 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
877 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
878 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255
879 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN +	\
880 		    MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
881 
882 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
883 
884 /* reg_spvm_pt
885  * Priority tagged. If this bit is set, packets forwarded to the port with
886  * untagged VLAN membership (u bit is set) will be tagged with priority tag
887  * (VID=0)
888  * Access: RW
889  */
890 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
891 
892 /* reg_spvm_pte
893  * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
894  * the pt bit will NOT be updated. To update the pt bit, pte must be set.
895  * Access: WO
896  */
897 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
898 
899 /* reg_spvm_local_port
900  * Local port number.
901  * Access: Index
902  */
903 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12);
904 
905 /* reg_spvm_sub_port
906  * Virtual port within the physical port.
907  * Should be set to 0 when virtual ports are not enabled on the port.
908  * Access: Index
909  */
910 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
911 
912 /* reg_spvm_num_rec
913  * Number of records to update. Each record contains: i, e, u, vid.
914  * Access: OP
915  */
916 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
917 
918 /* reg_spvm_rec_i
919  * Ingress membership in VLAN ID.
920  * Access: Index
921  */
922 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
923 		     MLXSW_REG_SPVM_BASE_LEN, 14, 1,
924 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
925 
926 /* reg_spvm_rec_e
927  * Egress membership in VLAN ID.
928  * Access: Index
929  */
930 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
931 		     MLXSW_REG_SPVM_BASE_LEN, 13, 1,
932 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
933 
934 /* reg_spvm_rec_u
935  * Untagged - port is an untagged member - egress transmission uses untagged
936  * frames on VID<n>
937  * Access: Index
938  */
939 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
940 		     MLXSW_REG_SPVM_BASE_LEN, 12, 1,
941 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
942 
943 /* reg_spvm_rec_vid
944  * Egress membership in VLAN ID.
945  * Access: Index
946  */
947 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
948 		     MLXSW_REG_SPVM_BASE_LEN, 0, 12,
949 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
950 
mlxsw_reg_spvm_pack(char * payload,u16 local_port,u16 vid_begin,u16 vid_end,bool is_member,bool untagged)951 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port,
952 				       u16 vid_begin, u16 vid_end,
953 				       bool is_member, bool untagged)
954 {
955 	int size = vid_end - vid_begin + 1;
956 	int i;
957 
958 	MLXSW_REG_ZERO(spvm, payload);
959 	mlxsw_reg_spvm_local_port_set(payload, local_port);
960 	mlxsw_reg_spvm_num_rec_set(payload, size);
961 
962 	for (i = 0; i < size; i++) {
963 		mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
964 		mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
965 		mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
966 		mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
967 	}
968 }
969 
970 /* SPAFT - Switch Port Acceptable Frame Types
971  * ------------------------------------------
972  * The Switch Port Acceptable Frame Types register configures the frame
973  * admittance of the port.
974  */
975 #define MLXSW_REG_SPAFT_ID 0x2010
976 #define MLXSW_REG_SPAFT_LEN 0x08
977 
978 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
979 
980 /* reg_spaft_local_port
981  * Local port number.
982  * Access: Index
983  *
984  * Note: CPU port is not supported (all tag types are allowed).
985  */
986 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12);
987 
988 /* reg_spaft_sub_port
989  * Virtual port within the physical port.
990  * Should be set to 0 when virtual ports are not enabled on the port.
991  * Access: RW
992  */
993 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
994 
995 /* reg_spaft_allow_untagged
996  * When set, untagged frames on the ingress are allowed (default).
997  * Access: RW
998  */
999 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
1000 
1001 /* reg_spaft_allow_prio_tagged
1002  * When set, priority tagged frames on the ingress are allowed (default).
1003  * Access: RW
1004  */
1005 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
1006 
1007 /* reg_spaft_allow_tagged
1008  * When set, tagged frames on the ingress are allowed (default).
1009  * Access: RW
1010  */
1011 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
1012 
mlxsw_reg_spaft_pack(char * payload,u16 local_port,bool allow_untagged)1013 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port,
1014 					bool allow_untagged)
1015 {
1016 	MLXSW_REG_ZERO(spaft, payload);
1017 	mlxsw_reg_spaft_local_port_set(payload, local_port);
1018 	mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
1019 	mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
1020 	mlxsw_reg_spaft_allow_tagged_set(payload, true);
1021 }
1022 
1023 /* SFGC - Switch Flooding Group Configuration
1024  * ------------------------------------------
1025  * The following register controls the association of flooding tables and MIDs
1026  * to packet types used for flooding.
1027  */
1028 #define MLXSW_REG_SFGC_ID 0x2011
1029 #define MLXSW_REG_SFGC_LEN 0x14
1030 
1031 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1032 
1033 enum mlxsw_reg_sfgc_type {
1034 	MLXSW_REG_SFGC_TYPE_BROADCAST,
1035 	MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1036 	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1037 	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1038 	MLXSW_REG_SFGC_TYPE_RESERVED,
1039 	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1040 	MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1041 	MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1042 	MLXSW_REG_SFGC_TYPE_MAX,
1043 };
1044 
1045 /* reg_sfgc_type
1046  * The traffic type to reach the flooding table.
1047  * Access: Index
1048  */
1049 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1050 
1051 /* bridge_type is used in SFGC and SFMR. */
1052 enum mlxsw_reg_bridge_type {
1053 	MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */
1054 	MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */
1055 };
1056 
1057 /* reg_sfgc_bridge_type
1058  * Access: Index
1059  *
1060  * Note: SwitchX-2 only supports 802.1Q mode.
1061  */
1062 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1063 
1064 enum mlxsw_flood_table_type {
1065 	MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1066 	MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1067 	MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1068 	MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1069 	MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1070 };
1071 
1072 /* reg_sfgc_table_type
1073  * See mlxsw_flood_table_type
1074  * Access: RW
1075  *
1076  * Note: FID offset and FID types are not supported in SwitchX-2.
1077  */
1078 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1079 
1080 /* reg_sfgc_flood_table
1081  * Flooding table index to associate with the specific type on the specific
1082  * switch partition.
1083  * Access: RW
1084  */
1085 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1086 
1087 /* reg_sfgc_counter_set_type
1088  * Counter Set Type for flow counters.
1089  * Access: RW
1090  */
1091 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1092 
1093 /* reg_sfgc_counter_index
1094  * Counter Index for flow counters.
1095  * Access: RW
1096  */
1097 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1098 
1099 /* reg_sfgc_mid_base
1100  * MID Base.
1101  * Access: RW
1102  *
1103  * Note: Reserved when legacy bridge model is used.
1104  */
1105 MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16);
1106 
1107 static inline void
mlxsw_reg_sfgc_pack(char * payload,enum mlxsw_reg_sfgc_type type,enum mlxsw_reg_bridge_type bridge_type,enum mlxsw_flood_table_type table_type,unsigned int flood_table,u16 mid_base)1108 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1109 		    enum mlxsw_reg_bridge_type bridge_type,
1110 		    enum mlxsw_flood_table_type table_type,
1111 		    unsigned int flood_table, u16 mid_base)
1112 {
1113 	MLXSW_REG_ZERO(sfgc, payload);
1114 	mlxsw_reg_sfgc_type_set(payload, type);
1115 	mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1116 	mlxsw_reg_sfgc_table_type_set(payload, table_type);
1117 	mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1118 	mlxsw_reg_sfgc_mid_base_set(payload, mid_base);
1119 }
1120 
1121 /* SFDF - Switch Filtering DB Flush
1122  * --------------------------------
1123  * The switch filtering DB flush register is used to flush the FDB.
1124  * Note that FDB notifications are flushed as well.
1125  */
1126 #define MLXSW_REG_SFDF_ID 0x2013
1127 #define MLXSW_REG_SFDF_LEN 0x14
1128 
1129 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1130 
1131 /* reg_sfdf_swid
1132  * Switch partition ID.
1133  * Access: Index
1134  */
1135 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1136 
1137 enum mlxsw_reg_sfdf_flush_type {
1138 	MLXSW_REG_SFDF_FLUSH_PER_SWID,
1139 	MLXSW_REG_SFDF_FLUSH_PER_FID,
1140 	MLXSW_REG_SFDF_FLUSH_PER_PORT,
1141 	MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1142 	MLXSW_REG_SFDF_FLUSH_PER_LAG,
1143 	MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1144 	MLXSW_REG_SFDF_FLUSH_PER_NVE,
1145 	MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1146 };
1147 
1148 /* reg_sfdf_flush_type
1149  * Flush type.
1150  * 0 - All SWID dynamic entries are flushed.
1151  * 1 - All FID dynamic entries are flushed.
1152  * 2 - All dynamic entries pointing to port are flushed.
1153  * 3 - All FID dynamic entries pointing to port are flushed.
1154  * 4 - All dynamic entries pointing to LAG are flushed.
1155  * 5 - All FID dynamic entries pointing to LAG are flushed.
1156  * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1157  *     flushed.
1158  * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1159  *     flushed, per FID.
1160  * Access: RW
1161  */
1162 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1163 
1164 /* reg_sfdf_flush_static
1165  * Static.
1166  * 0 - Flush only dynamic entries.
1167  * 1 - Flush both dynamic and static entries.
1168  * Access: RW
1169  */
1170 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1171 
mlxsw_reg_sfdf_pack(char * payload,enum mlxsw_reg_sfdf_flush_type type)1172 static inline void mlxsw_reg_sfdf_pack(char *payload,
1173 				       enum mlxsw_reg_sfdf_flush_type type)
1174 {
1175 	MLXSW_REG_ZERO(sfdf, payload);
1176 	mlxsw_reg_sfdf_flush_type_set(payload, type);
1177 	mlxsw_reg_sfdf_flush_static_set(payload, true);
1178 }
1179 
1180 /* reg_sfdf_fid
1181  * FID to flush.
1182  * Access: RW
1183  */
1184 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1185 
1186 /* reg_sfdf_system_port
1187  * Port to flush.
1188  * Access: RW
1189  */
1190 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1191 
1192 /* reg_sfdf_port_fid_system_port
1193  * Port to flush, pointed to by FID.
1194  * Access: RW
1195  */
1196 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1197 
1198 /* reg_sfdf_lag_id
1199  * LAG ID to flush.
1200  * Access: RW
1201  */
1202 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1203 
1204 /* reg_sfdf_lag_fid_lag_id
1205  * LAG ID to flush, pointed to by FID.
1206  * Access: RW
1207  */
1208 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1209 
1210 /* SLDR - Switch LAG Descriptor Register
1211  * -----------------------------------------
1212  * The switch LAG descriptor register is populated by LAG descriptors.
1213  * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1214  * max_lag-1.
1215  */
1216 #define MLXSW_REG_SLDR_ID 0x2014
1217 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1218 
1219 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1220 
1221 enum mlxsw_reg_sldr_op {
1222 	/* Indicates a creation of a new LAG-ID, lag_id must be valid */
1223 	MLXSW_REG_SLDR_OP_LAG_CREATE,
1224 	MLXSW_REG_SLDR_OP_LAG_DESTROY,
1225 	/* Ports that appear in the list have the Distributor enabled */
1226 	MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1227 	/* Removes ports from the disributor list */
1228 	MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1229 };
1230 
1231 /* reg_sldr_op
1232  * Operation.
1233  * Access: RW
1234  */
1235 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1236 
1237 /* reg_sldr_lag_id
1238  * LAG identifier. The lag_id is the index into the LAG descriptor table.
1239  * Access: Index
1240  */
1241 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1242 
mlxsw_reg_sldr_lag_create_pack(char * payload,u8 lag_id)1243 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1244 {
1245 	MLXSW_REG_ZERO(sldr, payload);
1246 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1247 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1248 }
1249 
mlxsw_reg_sldr_lag_destroy_pack(char * payload,u8 lag_id)1250 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1251 {
1252 	MLXSW_REG_ZERO(sldr, payload);
1253 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1254 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1255 }
1256 
1257 /* reg_sldr_num_ports
1258  * The number of member ports of the LAG.
1259  * Reserved for Create / Destroy operations
1260  * For Add / Remove operations - indicates the number of ports in the list.
1261  * Access: RW
1262  */
1263 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1264 
1265 /* reg_sldr_system_port
1266  * System port.
1267  * Access: RW
1268  */
1269 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1270 
mlxsw_reg_sldr_lag_add_port_pack(char * payload,u8 lag_id,u16 local_port)1271 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1272 						    u16 local_port)
1273 {
1274 	MLXSW_REG_ZERO(sldr, payload);
1275 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1276 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1277 	mlxsw_reg_sldr_num_ports_set(payload, 1);
1278 	mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1279 }
1280 
mlxsw_reg_sldr_lag_remove_port_pack(char * payload,u8 lag_id,u16 local_port)1281 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1282 						       u16 local_port)
1283 {
1284 	MLXSW_REG_ZERO(sldr, payload);
1285 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1286 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1287 	mlxsw_reg_sldr_num_ports_set(payload, 1);
1288 	mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1289 }
1290 
1291 /* SLCR - Switch LAG Configuration 2 Register
1292  * -------------------------------------------
1293  * The Switch LAG Configuration register is used for configuring the
1294  * LAG properties of the switch.
1295  */
1296 #define MLXSW_REG_SLCR_ID 0x2015
1297 #define MLXSW_REG_SLCR_LEN 0x10
1298 
1299 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1300 
1301 enum mlxsw_reg_slcr_pp {
1302 	/* Global Configuration (for all ports) */
1303 	MLXSW_REG_SLCR_PP_GLOBAL,
1304 	/* Per port configuration, based on local_port field */
1305 	MLXSW_REG_SLCR_PP_PER_PORT,
1306 };
1307 
1308 /* reg_slcr_pp
1309  * Per Port Configuration
1310  * Note: Reading at Global mode results in reading port 1 configuration.
1311  * Access: Index
1312  */
1313 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1314 
1315 /* reg_slcr_local_port
1316  * Local port number
1317  * Supported from CPU port
1318  * Not supported from router port
1319  * Reserved when pp = Global Configuration
1320  * Access: Index
1321  */
1322 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12);
1323 
1324 enum mlxsw_reg_slcr_type {
1325 	MLXSW_REG_SLCR_TYPE_CRC, /* default */
1326 	MLXSW_REG_SLCR_TYPE_XOR,
1327 	MLXSW_REG_SLCR_TYPE_RANDOM,
1328 };
1329 
1330 /* reg_slcr_type
1331  * Hash type
1332  * Access: RW
1333  */
1334 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1335 
1336 /* Ingress port */
1337 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT		BIT(0)
1338 /* SMAC - for IPv4 and IPv6 packets */
1339 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP		BIT(1)
1340 /* SMAC - for non-IP packets */
1341 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP	BIT(2)
1342 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1343 	(MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1344 	 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1345 /* DMAC - for IPv4 and IPv6 packets */
1346 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP		BIT(3)
1347 /* DMAC - for non-IP packets */
1348 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP	BIT(4)
1349 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1350 	(MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1351 	 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1352 /* Ethertype - for IPv4 and IPv6 packets */
1353 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP	BIT(5)
1354 /* Ethertype - for non-IP packets */
1355 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP	BIT(6)
1356 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1357 	(MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1358 	 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1359 /* VLAN ID - for IPv4 and IPv6 packets */
1360 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP	BIT(7)
1361 /* VLAN ID - for non-IP packets */
1362 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP	BIT(8)
1363 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1364 	(MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1365 	 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1366 /* Source IP address (can be IPv4 or IPv6) */
1367 #define MLXSW_REG_SLCR_LAG_HASH_SIP		BIT(9)
1368 /* Destination IP address (can be IPv4 or IPv6) */
1369 #define MLXSW_REG_SLCR_LAG_HASH_DIP		BIT(10)
1370 /* TCP/UDP source port */
1371 #define MLXSW_REG_SLCR_LAG_HASH_SPORT		BIT(11)
1372 /* TCP/UDP destination port*/
1373 #define MLXSW_REG_SLCR_LAG_HASH_DPORT		BIT(12)
1374 /* IPv4 Protocol/IPv6 Next Header */
1375 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO		BIT(13)
1376 /* IPv6 Flow label */
1377 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL	BIT(14)
1378 /* SID - FCoE source ID */
1379 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID	BIT(15)
1380 /* DID - FCoE destination ID */
1381 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID	BIT(16)
1382 /* OXID - FCoE originator exchange ID */
1383 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID	BIT(17)
1384 /* Destination QP number - for RoCE packets */
1385 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP	BIT(19)
1386 
1387 /* reg_slcr_lag_hash
1388  * LAG hashing configuration. This is a bitmask, in which each set
1389  * bit includes the corresponding item in the LAG hash calculation.
1390  * The default lag_hash contains SMAC, DMAC, VLANID and
1391  * Ethertype (for all packet types).
1392  * Access: RW
1393  */
1394 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1395 
1396 /* reg_slcr_seed
1397  * LAG seed value. The seed is the same for all ports.
1398  * Access: RW
1399  */
1400 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1401 
mlxsw_reg_slcr_pack(char * payload,u16 lag_hash,u32 seed)1402 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1403 {
1404 	MLXSW_REG_ZERO(slcr, payload);
1405 	mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1406 	mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1407 	mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1408 	mlxsw_reg_slcr_seed_set(payload, seed);
1409 }
1410 
1411 /* SLCOR - Switch LAG Collector Register
1412  * -------------------------------------
1413  * The Switch LAG Collector register controls the Local Port membership
1414  * in a LAG and enablement of the collector.
1415  */
1416 #define MLXSW_REG_SLCOR_ID 0x2016
1417 #define MLXSW_REG_SLCOR_LEN 0x10
1418 
1419 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1420 
1421 enum mlxsw_reg_slcor_col {
1422 	/* Port is added with collector disabled */
1423 	MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1424 	MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1425 	MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1426 	MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1427 };
1428 
1429 /* reg_slcor_col
1430  * Collector configuration
1431  * Access: RW
1432  */
1433 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1434 
1435 /* reg_slcor_local_port
1436  * Local port number
1437  * Not supported for CPU port
1438  * Access: Index
1439  */
1440 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12);
1441 
1442 /* reg_slcor_lag_id
1443  * LAG Identifier. Index into the LAG descriptor table.
1444  * Access: Index
1445  */
1446 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1447 
1448 /* reg_slcor_port_index
1449  * Port index in the LAG list. Only valid on Add Port to LAG col.
1450  * Valid range is from 0 to cap_max_lag_members-1
1451  * Access: RW
1452  */
1453 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1454 
mlxsw_reg_slcor_pack(char * payload,u16 local_port,u16 lag_id,enum mlxsw_reg_slcor_col col)1455 static inline void mlxsw_reg_slcor_pack(char *payload,
1456 					u16 local_port, u16 lag_id,
1457 					enum mlxsw_reg_slcor_col col)
1458 {
1459 	MLXSW_REG_ZERO(slcor, payload);
1460 	mlxsw_reg_slcor_col_set(payload, col);
1461 	mlxsw_reg_slcor_local_port_set(payload, local_port);
1462 	mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1463 }
1464 
mlxsw_reg_slcor_port_add_pack(char * payload,u16 local_port,u16 lag_id,u8 port_index)1465 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1466 						 u16 local_port, u16 lag_id,
1467 						 u8 port_index)
1468 {
1469 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1470 			     MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1471 	mlxsw_reg_slcor_port_index_set(payload, port_index);
1472 }
1473 
mlxsw_reg_slcor_port_remove_pack(char * payload,u16 local_port,u16 lag_id)1474 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1475 						    u16 local_port, u16 lag_id)
1476 {
1477 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1478 			     MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1479 }
1480 
mlxsw_reg_slcor_col_enable_pack(char * payload,u16 local_port,u16 lag_id)1481 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1482 						   u16 local_port, u16 lag_id)
1483 {
1484 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1485 			     MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1486 }
1487 
mlxsw_reg_slcor_col_disable_pack(char * payload,u16 local_port,u16 lag_id)1488 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1489 						    u16 local_port, u16 lag_id)
1490 {
1491 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1492 			     MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1493 }
1494 
1495 /* SPMLR - Switch Port MAC Learning Register
1496  * -----------------------------------------
1497  * Controls the Switch MAC learning policy per port.
1498  */
1499 #define MLXSW_REG_SPMLR_ID 0x2018
1500 #define MLXSW_REG_SPMLR_LEN 0x8
1501 
1502 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1503 
1504 /* reg_spmlr_local_port
1505  * Local port number.
1506  * Access: Index
1507  */
1508 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12);
1509 
1510 /* reg_spmlr_sub_port
1511  * Virtual port within the physical port.
1512  * Should be set to 0 when virtual ports are not enabled on the port.
1513  * Access: Index
1514  */
1515 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1516 
1517 enum mlxsw_reg_spmlr_learn_mode {
1518 	MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1519 	MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1520 	MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1521 };
1522 
1523 /* reg_spmlr_learn_mode
1524  * Learning mode on the port.
1525  * 0 - Learning disabled.
1526  * 2 - Learning enabled.
1527  * 3 - Security mode.
1528  *
1529  * In security mode the switch does not learn MACs on the port, but uses the
1530  * SMAC to see if it exists on another ingress port. If so, the packet is
1531  * classified as a bad packet and is discarded unless the software registers
1532  * to receive port security error packets usign HPKT.
1533  */
1534 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1535 
mlxsw_reg_spmlr_pack(char * payload,u16 local_port,enum mlxsw_reg_spmlr_learn_mode mode)1536 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port,
1537 					enum mlxsw_reg_spmlr_learn_mode mode)
1538 {
1539 	MLXSW_REG_ZERO(spmlr, payload);
1540 	mlxsw_reg_spmlr_local_port_set(payload, local_port);
1541 	mlxsw_reg_spmlr_sub_port_set(payload, 0);
1542 	mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1543 }
1544 
1545 /* SVFA - Switch VID to FID Allocation Register
1546  * --------------------------------------------
1547  * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1548  * virtualized ports.
1549  */
1550 #define MLXSW_REG_SVFA_ID 0x201C
1551 #define MLXSW_REG_SVFA_LEN 0x18
1552 
1553 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1554 
1555 /* reg_svfa_swid
1556  * Switch partition ID.
1557  * Access: Index
1558  */
1559 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1560 
1561 /* reg_svfa_local_port
1562  * Local port number.
1563  * Access: Index
1564  *
1565  * Note: Reserved for 802.1Q FIDs.
1566  */
1567 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12);
1568 
1569 enum mlxsw_reg_svfa_mt {
1570 	MLXSW_REG_SVFA_MT_VID_TO_FID,
1571 	MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1572 	MLXSW_REG_SVFA_MT_VNI_TO_FID,
1573 };
1574 
1575 /* reg_svfa_mapping_table
1576  * Mapping table:
1577  * 0 - VID to FID
1578  * 1 - {Port, VID} to FID
1579  * Access: Index
1580  *
1581  * Note: Reserved for SwitchX-2.
1582  */
1583 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1584 
1585 /* reg_svfa_v
1586  * Valid.
1587  * Valid if set.
1588  * Access: RW
1589  *
1590  * Note: Reserved for SwitchX-2.
1591  */
1592 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1593 
1594 /* reg_svfa_fid
1595  * Filtering ID.
1596  * Access: RW
1597  */
1598 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1599 
1600 /* reg_svfa_vid
1601  * VLAN ID.
1602  * Access: Index
1603  */
1604 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1605 
1606 /* reg_svfa_counter_set_type
1607  * Counter set type for flow counters.
1608  * Access: RW
1609  *
1610  * Note: Reserved for SwitchX-2.
1611  */
1612 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1613 
1614 /* reg_svfa_counter_index
1615  * Counter index for flow counters.
1616  * Access: RW
1617  *
1618  * Note: Reserved for SwitchX-2.
1619  */
1620 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1621 
1622 /* reg_svfa_vni
1623  * Virtual Network Identifier.
1624  * Access: Index
1625  *
1626  * Note: Reserved when mapping_table is not 2 (VNI mapping table).
1627  */
1628 MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24);
1629 
1630 /* reg_svfa_irif_v
1631  * Ingress RIF valid.
1632  * 0 - Ingress RIF is not valid, no ingress RIF assigned.
1633  * 1 - Ingress RIF valid.
1634  * Must not be set for a non enabled RIF.
1635  * Access: RW
1636  *
1637  * Note: Reserved when legacy bridge model is used.
1638  */
1639 MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1);
1640 
1641 /* reg_svfa_irif
1642  * Ingress RIF (Router Interface).
1643  * Range is 0..cap_max_router_interfaces-1.
1644  * Access: RW
1645  *
1646  * Note: Reserved when legacy bridge model is used and when irif_v=0.
1647  */
1648 MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16);
1649 
__mlxsw_reg_svfa_pack(char * payload,enum mlxsw_reg_svfa_mt mt,bool valid,u16 fid,bool irif_v,u16 irif)1650 static inline void __mlxsw_reg_svfa_pack(char *payload,
1651 					 enum mlxsw_reg_svfa_mt mt, bool valid,
1652 					 u16 fid, bool irif_v, u16 irif)
1653 {
1654 	MLXSW_REG_ZERO(svfa, payload);
1655 	mlxsw_reg_svfa_swid_set(payload, 0);
1656 	mlxsw_reg_svfa_mapping_table_set(payload, mt);
1657 	mlxsw_reg_svfa_v_set(payload, valid);
1658 	mlxsw_reg_svfa_fid_set(payload, fid);
1659 	mlxsw_reg_svfa_irif_v_set(payload, irif_v);
1660 	mlxsw_reg_svfa_irif_set(payload, irif_v ? irif : 0);
1661 }
1662 
mlxsw_reg_svfa_port_vid_pack(char * payload,u16 local_port,bool valid,u16 fid,u16 vid,bool irif_v,u16 irif)1663 static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port,
1664 						bool valid, u16 fid, u16 vid,
1665 						bool irif_v, u16 irif)
1666 {
1667 	enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1668 
1669 	__mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);
1670 	mlxsw_reg_svfa_local_port_set(payload, local_port);
1671 	mlxsw_reg_svfa_vid_set(payload, vid);
1672 }
1673 
mlxsw_reg_svfa_vid_pack(char * payload,bool valid,u16 fid,u16 vid,bool irif_v,u16 irif)1674 static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid,
1675 					   u16 vid, bool irif_v, u16 irif)
1676 {
1677 	enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID;
1678 
1679 	__mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);
1680 	mlxsw_reg_svfa_vid_set(payload, vid);
1681 }
1682 
mlxsw_reg_svfa_vni_pack(char * payload,bool valid,u16 fid,u32 vni,bool irif_v,u16 irif)1683 static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid,
1684 					   u32 vni, bool irif_v, u16 irif)
1685 {
1686 	enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID;
1687 
1688 	__mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);
1689 	mlxsw_reg_svfa_vni_set(payload, vni);
1690 }
1691 
1692 /*  SPVTR - Switch Port VLAN Stacking Register
1693  *  ------------------------------------------
1694  *  The Switch Port VLAN Stacking register configures the VLAN mode of the port
1695  *  to enable VLAN stacking.
1696  */
1697 #define MLXSW_REG_SPVTR_ID 0x201D
1698 #define MLXSW_REG_SPVTR_LEN 0x10
1699 
1700 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN);
1701 
1702 /* reg_spvtr_tport
1703  * Port is tunnel port.
1704  * Access: Index
1705  *
1706  * Note: Reserved when SwitchX/-2 or Spectrum-1.
1707  */
1708 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1);
1709 
1710 /* reg_spvtr_local_port
1711  * When tport = 0: local port number (Not supported from/to CPU).
1712  * When tport = 1: tunnel port.
1713  * Access: Index
1714  */
1715 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12);
1716 
1717 /* reg_spvtr_ippe
1718  * Ingress Port Prio Mode Update Enable.
1719  * When set, the Port Prio Mode is updated with the provided ipprio_mode field.
1720  * Reserved on Get operations.
1721  * Access: OP
1722  */
1723 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1);
1724 
1725 /* reg_spvtr_ipve
1726  * Ingress Port VID Mode Update Enable.
1727  * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode
1728  * field.
1729  * Reserved on Get operations.
1730  * Access: OP
1731  */
1732 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1);
1733 
1734 /* reg_spvtr_epve
1735  * Egress Port VID Mode Update Enable.
1736  * When set, the Egress Port VID Mode is updated with the provided epvid_mode
1737  * field.
1738  * Access: OP
1739  */
1740 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1);
1741 
1742 /* reg_spvtr_ipprio_mode
1743  * Ingress Port Priority Mode.
1744  * This controls the PCP and DEI of the new outer VLAN
1745  * Note: for SwitchX/-2 the DEI is not affected.
1746  * 0: use port default PCP and DEI (configured by QPDPC).
1747  * 1: use C-VLAN PCP and DEI.
1748  * Has no effect when ipvid_mode = 0.
1749  * Reserved when tport = 1.
1750  * Access: RW
1751  */
1752 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4);
1753 
1754 enum mlxsw_reg_spvtr_ipvid_mode {
1755 	/* IEEE Compliant PVID (default) */
1756 	MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID,
1757 	/* Push VLAN (for VLAN stacking, except prio tagged packets) */
1758 	MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET,
1759 	/* Always push VLAN (also for prio tagged packets) */
1760 	MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN,
1761 };
1762 
1763 /* reg_spvtr_ipvid_mode
1764  * Ingress Port VLAN-ID Mode.
1765  * For Spectrum family, this affects the values of SPVM.i
1766  * Access: RW
1767  */
1768 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4);
1769 
1770 enum mlxsw_reg_spvtr_epvid_mode {
1771 	/* IEEE Compliant VLAN membership */
1772 	MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP,
1773 	/* Pop VLAN (for VLAN stacking) */
1774 	MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN,
1775 };
1776 
1777 /* reg_spvtr_epvid_mode
1778  * Egress Port VLAN-ID Mode.
1779  * For Spectrum family, this affects the values of SPVM.e,u,pt.
1780  * Access: WO
1781  */
1782 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4);
1783 
mlxsw_reg_spvtr_pack(char * payload,bool tport,u16 local_port,enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode)1784 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport,
1785 					u16 local_port,
1786 					enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode)
1787 {
1788 	MLXSW_REG_ZERO(spvtr, payload);
1789 	mlxsw_reg_spvtr_tport_set(payload, tport);
1790 	mlxsw_reg_spvtr_local_port_set(payload, local_port);
1791 	mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode);
1792 	mlxsw_reg_spvtr_ipve_set(payload, true);
1793 }
1794 
1795 /* SVPE - Switch Virtual-Port Enabling Register
1796  * --------------------------------------------
1797  * Enables port virtualization.
1798  */
1799 #define MLXSW_REG_SVPE_ID 0x201E
1800 #define MLXSW_REG_SVPE_LEN 0x4
1801 
1802 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1803 
1804 /* reg_svpe_local_port
1805  * Local port number
1806  * Access: Index
1807  *
1808  * Note: CPU port is not supported (uses VLAN mode only).
1809  */
1810 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12);
1811 
1812 /* reg_svpe_vp_en
1813  * Virtual port enable.
1814  * 0 - Disable, VLAN mode (VID to FID).
1815  * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1816  * Access: RW
1817  */
1818 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1819 
mlxsw_reg_svpe_pack(char * payload,u16 local_port,bool enable)1820 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port,
1821 				       bool enable)
1822 {
1823 	MLXSW_REG_ZERO(svpe, payload);
1824 	mlxsw_reg_svpe_local_port_set(payload, local_port);
1825 	mlxsw_reg_svpe_vp_en_set(payload, enable);
1826 }
1827 
1828 /* SFMR - Switch FID Management Register
1829  * -------------------------------------
1830  * Creates and configures FIDs.
1831  */
1832 #define MLXSW_REG_SFMR_ID 0x201F
1833 #define MLXSW_REG_SFMR_LEN 0x30
1834 
1835 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1836 
1837 enum mlxsw_reg_sfmr_op {
1838 	MLXSW_REG_SFMR_OP_CREATE_FID,
1839 	MLXSW_REG_SFMR_OP_DESTROY_FID,
1840 };
1841 
1842 /* reg_sfmr_op
1843  * Operation.
1844  * 0 - Create or edit FID.
1845  * 1 - Destroy FID.
1846  * Access: WO
1847  */
1848 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1849 
1850 /* reg_sfmr_fid
1851  * Filtering ID.
1852  * Access: Index
1853  */
1854 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1855 
1856 /* reg_sfmr_flood_rsp
1857  * Router sub-port flooding table.
1858  * 0 - Regular flooding table.
1859  * 1 - Router sub-port flooding table. For this FID the flooding is per
1860  * router-sub-port local_port. Must not be set for a FID which is not a
1861  * router-sub-port and must be set prior to enabling the relevant RIF.
1862  * Access: RW
1863  *
1864  * Note: Reserved when legacy bridge model is used.
1865  */
1866 MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1);
1867 
1868 /* reg_sfmr_flood_bridge_type
1869  * Flood bridge type (see SFGC.bridge_type).
1870  * 0 - type_0.
1871  * 1 - type_1.
1872  * Access: RW
1873  *
1874  * Note: Reserved when legacy bridge model is used and when flood_rsp=1.
1875  */
1876 MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1);
1877 
1878 /* reg_sfmr_fid_offset
1879  * FID offset.
1880  * Used to point into the flooding table selected by SFGC register if
1881  * the table is of type FID-Offset. Otherwise, this field is reserved.
1882  * Access: RW
1883  */
1884 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1885 
1886 /* reg_sfmr_vtfp
1887  * Valid Tunnel Flood Pointer.
1888  * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1889  * Access: RW
1890  *
1891  * Note: Reserved for 802.1Q FIDs.
1892  */
1893 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1894 
1895 /* reg_sfmr_nve_tunnel_flood_ptr
1896  * Underlay Flooding and BC Pointer.
1897  * Used as a pointer to the first entry of the group based link lists of
1898  * flooding or BC entries (for NVE tunnels).
1899  * Access: RW
1900  */
1901 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1902 
1903 /* reg_sfmr_vv
1904  * VNI Valid.
1905  * If not set, then vni is reserved.
1906  * Access: RW
1907  *
1908  * Note: Reserved for 802.1Q FIDs.
1909  */
1910 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1911 
1912 /* reg_sfmr_vni
1913  * Virtual Network Identifier.
1914  * When legacy bridge model is used, a given VNI can only be assigned to one
1915  * FID. When unified bridge model is used, it configures only the FID->VNI,
1916  * the VNI->FID is done by SVFA.
1917  * Access: RW
1918  */
1919 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1920 
1921 /* reg_sfmr_irif_v
1922  * Ingress RIF valid.
1923  * 0 - Ingress RIF is not valid, no ingress RIF assigned.
1924  * 1 - Ingress RIF valid.
1925  * Must not be set for a non valid RIF.
1926  * Access: RW
1927  *
1928  * Note: Reserved when legacy bridge model is used.
1929  */
1930 MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1);
1931 
1932 /* reg_sfmr_irif
1933  * Ingress RIF (Router Interface).
1934  * Range is 0..cap_max_router_interfaces-1.
1935  * Access: RW
1936  *
1937  * Note: Reserved when legacy bridge model is used and when irif_v=0.
1938  */
1939 MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16);
1940 
1941 /* reg_sfmr_smpe_valid
1942  * SMPE is valid.
1943  * Access: RW
1944  *
1945  * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on
1946  * Spectrum-1.
1947  */
1948 MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1);
1949 
1950 /* reg_sfmr_smpe
1951  * Switch multicast port to egress VID.
1952  * Range is 0..cap_max_rmpe-1
1953  * Access: RW
1954  *
1955  * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on
1956  * Spectrum-1.
1957  */
1958 MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16);
1959 
mlxsw_reg_sfmr_pack(char * payload,enum mlxsw_reg_sfmr_op op,u16 fid,u16 fid_offset,bool flood_rsp,enum mlxsw_reg_bridge_type bridge_type,bool smpe_valid,u16 smpe)1960 static inline void mlxsw_reg_sfmr_pack(char *payload,
1961 				       enum mlxsw_reg_sfmr_op op, u16 fid,
1962 				       u16 fid_offset, bool flood_rsp,
1963 				       enum mlxsw_reg_bridge_type bridge_type,
1964 				       bool smpe_valid, u16 smpe)
1965 {
1966 	MLXSW_REG_ZERO(sfmr, payload);
1967 	mlxsw_reg_sfmr_op_set(payload, op);
1968 	mlxsw_reg_sfmr_fid_set(payload, fid);
1969 	mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1970 	mlxsw_reg_sfmr_vtfp_set(payload, false);
1971 	mlxsw_reg_sfmr_vv_set(payload, false);
1972 	mlxsw_reg_sfmr_flood_rsp_set(payload, flood_rsp);
1973 	mlxsw_reg_sfmr_flood_bridge_type_set(payload, bridge_type);
1974 	mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid);
1975 	mlxsw_reg_sfmr_smpe_set(payload, smpe);
1976 }
1977 
1978 /* SPVMLR - Switch Port VLAN MAC Learning Register
1979  * -----------------------------------------------
1980  * Controls the switch MAC learning policy per {Port, VID}.
1981  */
1982 #define MLXSW_REG_SPVMLR_ID 0x2020
1983 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1984 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1985 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1986 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1987 			      MLXSW_REG_SPVMLR_REC_LEN * \
1988 			      MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1989 
1990 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1991 
1992 /* reg_spvmlr_local_port
1993  * Local ingress port.
1994  * Access: Index
1995  *
1996  * Note: CPU port is not supported.
1997  */
1998 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12);
1999 
2000 /* reg_spvmlr_num_rec
2001  * Number of records to update.
2002  * Access: OP
2003  */
2004 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
2005 
2006 /* reg_spvmlr_rec_learn_enable
2007  * 0 - Disable learning for {Port, VID}.
2008  * 1 - Enable learning for {Port, VID}.
2009  * Access: RW
2010  */
2011 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
2012 		     31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
2013 
2014 /* reg_spvmlr_rec_vid
2015  * VLAN ID to be added/removed from port or for querying.
2016  * Access: Index
2017  */
2018 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
2019 		     MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
2020 
mlxsw_reg_spvmlr_pack(char * payload,u16 local_port,u16 vid_begin,u16 vid_end,bool learn_enable)2021 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port,
2022 					 u16 vid_begin, u16 vid_end,
2023 					 bool learn_enable)
2024 {
2025 	int num_rec = vid_end - vid_begin + 1;
2026 	int i;
2027 
2028 	WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
2029 
2030 	MLXSW_REG_ZERO(spvmlr, payload);
2031 	mlxsw_reg_spvmlr_local_port_set(payload, local_port);
2032 	mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
2033 
2034 	for (i = 0; i < num_rec; i++) {
2035 		mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
2036 		mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
2037 	}
2038 }
2039 
2040 /* SPVC - Switch Port VLAN Classification Register
2041  * -----------------------------------------------
2042  * Configures the port to identify packets as untagged / single tagged /
2043  * double packets based on the packet EtherTypes.
2044  * Ethertype IDs are configured by SVER.
2045  */
2046 #define MLXSW_REG_SPVC_ID 0x2026
2047 #define MLXSW_REG_SPVC_LEN 0x0C
2048 
2049 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN);
2050 
2051 /* reg_spvc_local_port
2052  * Local port.
2053  * Access: Index
2054  *
2055  * Note: applies both to Rx port and Tx port, so if a packet traverses
2056  * through Rx port i and a Tx port j then port i and port j must have the
2057  * same configuration.
2058  */
2059 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12);
2060 
2061 /* reg_spvc_inner_et2
2062  * Vlan Tag1 EtherType2 enable.
2063  * Packet is initially classified as double VLAN Tag if in addition to
2064  * being classified with a tag0 VLAN Tag its tag1 EtherType value is
2065  * equal to ether_type2.
2066  * 0: disable (default)
2067  * 1: enable
2068  * Access: RW
2069  */
2070 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1);
2071 
2072 /* reg_spvc_et2
2073  * Vlan Tag0 EtherType2 enable.
2074  * Packet is initially classified as VLAN Tag if its tag0 EtherType is
2075  * equal to ether_type2.
2076  * 0: disable (default)
2077  * 1: enable
2078  * Access: RW
2079  */
2080 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1);
2081 
2082 /* reg_spvc_inner_et1
2083  * Vlan Tag1 EtherType1 enable.
2084  * Packet is initially classified as double VLAN Tag if in addition to
2085  * being classified with a tag0 VLAN Tag its tag1 EtherType value is
2086  * equal to ether_type1.
2087  * 0: disable
2088  * 1: enable (default)
2089  * Access: RW
2090  */
2091 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1);
2092 
2093 /* reg_spvc_et1
2094  * Vlan Tag0 EtherType1 enable.
2095  * Packet is initially classified as VLAN Tag if its tag0 EtherType is
2096  * equal to ether_type1.
2097  * 0: disable
2098  * 1: enable (default)
2099  * Access: RW
2100  */
2101 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1);
2102 
2103 /* reg_inner_et0
2104  * Vlan Tag1 EtherType0 enable.
2105  * Packet is initially classified as double VLAN Tag if in addition to
2106  * being classified with a tag0 VLAN Tag its tag1 EtherType value is
2107  * equal to ether_type0.
2108  * 0: disable
2109  * 1: enable (default)
2110  * Access: RW
2111  */
2112 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1);
2113 
2114 /* reg_et0
2115  * Vlan Tag0 EtherType0 enable.
2116  * Packet is initially classified as VLAN Tag if its tag0 EtherType is
2117  * equal to ether_type0.
2118  * 0: disable
2119  * 1: enable (default)
2120  * Access: RW
2121  */
2122 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1);
2123 
mlxsw_reg_spvc_pack(char * payload,u16 local_port,bool et1,bool et0)2124 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1,
2125 				       bool et0)
2126 {
2127 	MLXSW_REG_ZERO(spvc, payload);
2128 	mlxsw_reg_spvc_local_port_set(payload, local_port);
2129 	/* Enable inner_et1 and inner_et0 to enable identification of double
2130 	 * tagged packets.
2131 	 */
2132 	mlxsw_reg_spvc_inner_et1_set(payload, 1);
2133 	mlxsw_reg_spvc_inner_et0_set(payload, 1);
2134 	mlxsw_reg_spvc_et1_set(payload, et1);
2135 	mlxsw_reg_spvc_et0_set(payload, et0);
2136 }
2137 
2138 /* SPEVET - Switch Port Egress VLAN EtherType
2139  * ------------------------------------------
2140  * The switch port egress VLAN EtherType configures which EtherType to push at
2141  * egress for packets incoming through a local port for which 'SPVID.egr_et_set'
2142  * is set.
2143  */
2144 #define MLXSW_REG_SPEVET_ID 0x202A
2145 #define MLXSW_REG_SPEVET_LEN 0x08
2146 
2147 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN);
2148 
2149 /* reg_spevet_local_port
2150  * Egress Local port number.
2151  * Not supported to CPU port.
2152  * Access: Index
2153  */
2154 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12);
2155 
2156 /* reg_spevet_et_vlan
2157  * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet:
2158  * 0: ether_type0 - (default)
2159  * 1: ether_type1
2160  * 2: ether_type2
2161  * Access: RW
2162  */
2163 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2);
2164 
mlxsw_reg_spevet_pack(char * payload,u16 local_port,u8 et_vlan)2165 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port,
2166 					 u8 et_vlan)
2167 {
2168 	MLXSW_REG_ZERO(spevet, payload);
2169 	mlxsw_reg_spevet_local_port_set(payload, local_port);
2170 	mlxsw_reg_spevet_et_vlan_set(payload, et_vlan);
2171 }
2172 
2173 /* SMPE - Switch Multicast Port to Egress VID
2174  * ------------------------------------------
2175  * The switch multicast port to egress VID maps
2176  * {egress_port, SMPE index} -> {VID}.
2177  */
2178 #define MLXSW_REG_SMPE_ID 0x202B
2179 #define MLXSW_REG_SMPE_LEN 0x0C
2180 
2181 MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN);
2182 
2183 /* reg_smpe_local_port
2184  * Local port number.
2185  * CPU port is not supported.
2186  * Access: Index
2187  */
2188 MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12);
2189 
2190 /* reg_smpe_smpe_index
2191  * Switch multicast port to egress VID.
2192  * Range is 0..cap_max_rmpe-1.
2193  * Access: Index
2194  */
2195 MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16);
2196 
2197 /* reg_smpe_evid
2198  * Egress VID.
2199  * Access: RW
2200  */
2201 MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12);
2202 
mlxsw_reg_smpe_pack(char * payload,u16 local_port,u16 smpe_index,u16 evid)2203 static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port,
2204 				       u16 smpe_index, u16 evid)
2205 {
2206 	MLXSW_REG_ZERO(smpe, payload);
2207 	mlxsw_reg_smpe_local_port_set(payload, local_port);
2208 	mlxsw_reg_smpe_smpe_index_set(payload, smpe_index);
2209 	mlxsw_reg_smpe_evid_set(payload, evid);
2210 }
2211 
2212 /* SMID-V2 - Switch Multicast ID Version 2 Register
2213  * ------------------------------------------------
2214  * The MID record maps from a MID (Multicast ID), which is a unique identifier
2215  * of the multicast group within the stacking domain, into a list of local
2216  * ports into which the packet is replicated.
2217  */
2218 #define MLXSW_REG_SMID2_ID 0x2034
2219 #define MLXSW_REG_SMID2_LEN 0x120
2220 
2221 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN);
2222 
2223 /* reg_smid2_swid
2224  * Switch partition ID.
2225  * Access: Index
2226  */
2227 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8);
2228 
2229 /* reg_smid2_mid
2230  * Multicast identifier - global identifier that represents the multicast group
2231  * across all devices.
2232  * Access: Index
2233  */
2234 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16);
2235 
2236 /* reg_smid2_smpe_valid
2237  * SMPE is valid.
2238  * When not valid, the egress VID will not be modified by the SMPE table.
2239  * Access: RW
2240  *
2241  * Note: Reserved when legacy bridge model is used and on Spectrum-2.
2242  */
2243 MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1);
2244 
2245 /* reg_smid2_smpe
2246  * Switch multicast port to egress VID.
2247  * Access: RW
2248  *
2249  * Note: Reserved when legacy bridge model is used and on Spectrum-2.
2250  */
2251 MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16);
2252 
2253 /* reg_smid2_port
2254  * Local port memebership (1 bit per port).
2255  * Access: RW
2256  */
2257 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1);
2258 
2259 /* reg_smid2_port_mask
2260  * Local port mask (1 bit per port).
2261  * Access: WO
2262  */
2263 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1);
2264 
mlxsw_reg_smid2_pack(char * payload,u16 mid,u16 port,bool set,bool smpe_valid,u16 smpe)2265 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port,
2266 					bool set, bool smpe_valid, u16 smpe)
2267 {
2268 	MLXSW_REG_ZERO(smid2, payload);
2269 	mlxsw_reg_smid2_swid_set(payload, 0);
2270 	mlxsw_reg_smid2_mid_set(payload, mid);
2271 	mlxsw_reg_smid2_port_set(payload, port, set);
2272 	mlxsw_reg_smid2_port_mask_set(payload, port, 1);
2273 	mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid);
2274 	mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0);
2275 }
2276 
2277 /* CWTP - Congetion WRED ECN TClass Profile
2278  * ----------------------------------------
2279  * Configures the profiles for queues of egress port and traffic class
2280  */
2281 #define MLXSW_REG_CWTP_ID 0x2802
2282 #define MLXSW_REG_CWTP_BASE_LEN 0x28
2283 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
2284 #define MLXSW_REG_CWTP_LEN 0x40
2285 
2286 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
2287 
2288 /* reg_cwtp_local_port
2289  * Local port number
2290  * Not supported for CPU port
2291  * Access: Index
2292  */
2293 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12);
2294 
2295 /* reg_cwtp_traffic_class
2296  * Traffic Class to configure
2297  * Access: Index
2298  */
2299 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
2300 
2301 /* reg_cwtp_profile_min
2302  * Minimum Average Queue Size of the profile in cells.
2303  * Access: RW
2304  */
2305 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
2306 		     0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
2307 
2308 /* reg_cwtp_profile_percent
2309  * Percentage of WRED and ECN marking for maximum Average Queue size
2310  * Range is 0 to 100, units of integer percentage
2311  * Access: RW
2312  */
2313 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
2314 		     24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2315 
2316 /* reg_cwtp_profile_max
2317  * Maximum Average Queue size of the profile in cells
2318  * Access: RW
2319  */
2320 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
2321 		     0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2322 
2323 #define MLXSW_REG_CWTP_MIN_VALUE 64
2324 #define MLXSW_REG_CWTP_MAX_PROFILE 2
2325 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
2326 
mlxsw_reg_cwtp_pack(char * payload,u16 local_port,u8 traffic_class)2327 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port,
2328 				       u8 traffic_class)
2329 {
2330 	int i;
2331 
2332 	MLXSW_REG_ZERO(cwtp, payload);
2333 	mlxsw_reg_cwtp_local_port_set(payload, local_port);
2334 	mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
2335 
2336 	for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
2337 		mlxsw_reg_cwtp_profile_min_set(payload, i,
2338 					       MLXSW_REG_CWTP_MIN_VALUE);
2339 		mlxsw_reg_cwtp_profile_max_set(payload, i,
2340 					       MLXSW_REG_CWTP_MIN_VALUE);
2341 	}
2342 }
2343 
2344 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
2345 
2346 static inline void
mlxsw_reg_cwtp_profile_pack(char * payload,u8 profile,u32 min,u32 max,u32 probability)2347 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
2348 			    u32 probability)
2349 {
2350 	u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
2351 
2352 	mlxsw_reg_cwtp_profile_min_set(payload, index, min);
2353 	mlxsw_reg_cwtp_profile_max_set(payload, index, max);
2354 	mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
2355 }
2356 
2357 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping
2358  * ---------------------------------------------------
2359  * The CWTPM register maps each egress port and traffic class to profile num.
2360  */
2361 #define MLXSW_REG_CWTPM_ID 0x2803
2362 #define MLXSW_REG_CWTPM_LEN 0x44
2363 
2364 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
2365 
2366 /* reg_cwtpm_local_port
2367  * Local port number
2368  * Not supported for CPU port
2369  * Access: Index
2370  */
2371 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12);
2372 
2373 /* reg_cwtpm_traffic_class
2374  * Traffic Class to configure
2375  * Access: Index
2376  */
2377 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
2378 
2379 /* reg_cwtpm_ew
2380  * Control enablement of WRED for traffic class:
2381  * 0 - Disable
2382  * 1 - Enable
2383  * Access: RW
2384  */
2385 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
2386 
2387 /* reg_cwtpm_ee
2388  * Control enablement of ECN for traffic class:
2389  * 0 - Disable
2390  * 1 - Enable
2391  * Access: RW
2392  */
2393 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
2394 
2395 /* reg_cwtpm_tcp_g
2396  * TCP Green Profile.
2397  * Index of the profile within {port, traffic class} to use.
2398  * 0 for disabling both WRED and ECN for this type of traffic.
2399  * Access: RW
2400  */
2401 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
2402 
2403 /* reg_cwtpm_tcp_y
2404  * TCP Yellow Profile.
2405  * Index of the profile within {port, traffic class} to use.
2406  * 0 for disabling both WRED and ECN for this type of traffic.
2407  * Access: RW
2408  */
2409 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
2410 
2411 /* reg_cwtpm_tcp_r
2412  * TCP Red Profile.
2413  * Index of the profile within {port, traffic class} to use.
2414  * 0 for disabling both WRED and ECN for this type of traffic.
2415  * Access: RW
2416  */
2417 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2418 
2419 /* reg_cwtpm_ntcp_g
2420  * Non-TCP Green Profile.
2421  * Index of the profile within {port, traffic class} to use.
2422  * 0 for disabling both WRED and ECN for this type of traffic.
2423  * Access: RW
2424  */
2425 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2426 
2427 /* reg_cwtpm_ntcp_y
2428  * Non-TCP Yellow Profile.
2429  * Index of the profile within {port, traffic class} to use.
2430  * 0 for disabling both WRED and ECN for this type of traffic.
2431  * Access: RW
2432  */
2433 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2434 
2435 /* reg_cwtpm_ntcp_r
2436  * Non-TCP Red Profile.
2437  * Index of the profile within {port, traffic class} to use.
2438  * 0 for disabling both WRED and ECN for this type of traffic.
2439  * Access: RW
2440  */
2441 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2442 
2443 #define MLXSW_REG_CWTPM_RESET_PROFILE 0
2444 
mlxsw_reg_cwtpm_pack(char * payload,u16 local_port,u8 traffic_class,u8 profile,bool wred,bool ecn)2445 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port,
2446 					u8 traffic_class, u8 profile,
2447 					bool wred, bool ecn)
2448 {
2449 	MLXSW_REG_ZERO(cwtpm, payload);
2450 	mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2451 	mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2452 	mlxsw_reg_cwtpm_ew_set(payload, wred);
2453 	mlxsw_reg_cwtpm_ee_set(payload, ecn);
2454 	mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
2455 	mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
2456 	mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
2457 	mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
2458 	mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
2459 	mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
2460 }
2461 
2462 /* PGCR - Policy-Engine General Configuration Register
2463  * ---------------------------------------------------
2464  * This register configures general Policy-Engine settings.
2465  */
2466 #define MLXSW_REG_PGCR_ID 0x3001
2467 #define MLXSW_REG_PGCR_LEN 0x20
2468 
2469 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2470 
2471 /* reg_pgcr_default_action_pointer_base
2472  * Default action pointer base. Each region has a default action pointer
2473  * which is equal to default_action_pointer_base + region_id.
2474  * Access: RW
2475  */
2476 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2477 
mlxsw_reg_pgcr_pack(char * payload,u32 pointer_base)2478 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2479 {
2480 	MLXSW_REG_ZERO(pgcr, payload);
2481 	mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2482 }
2483 
2484 /* PPBT - Policy-Engine Port Binding Table
2485  * ---------------------------------------
2486  * This register is used for configuration of the Port Binding Table.
2487  */
2488 #define MLXSW_REG_PPBT_ID 0x3002
2489 #define MLXSW_REG_PPBT_LEN 0x14
2490 
2491 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2492 
2493 enum mlxsw_reg_pxbt_e {
2494 	MLXSW_REG_PXBT_E_IACL,
2495 	MLXSW_REG_PXBT_E_EACL,
2496 };
2497 
2498 /* reg_ppbt_e
2499  * Access: Index
2500  */
2501 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2502 
2503 enum mlxsw_reg_pxbt_op {
2504 	MLXSW_REG_PXBT_OP_BIND,
2505 	MLXSW_REG_PXBT_OP_UNBIND,
2506 };
2507 
2508 /* reg_ppbt_op
2509  * Access: RW
2510  */
2511 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2512 
2513 /* reg_ppbt_local_port
2514  * Local port. Not including CPU port.
2515  * Access: Index
2516  */
2517 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12);
2518 
2519 /* reg_ppbt_g
2520  * group - When set, the binding is of an ACL group. When cleared,
2521  * the binding is of an ACL.
2522  * Must be set to 1 for Spectrum.
2523  * Access: RW
2524  */
2525 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2526 
2527 /* reg_ppbt_acl_info
2528  * ACL/ACL group identifier. If the g bit is set, this field should hold
2529  * the acl_group_id, else it should hold the acl_id.
2530  * Access: RW
2531  */
2532 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2533 
mlxsw_reg_ppbt_pack(char * payload,enum mlxsw_reg_pxbt_e e,enum mlxsw_reg_pxbt_op op,u16 local_port,u16 acl_info)2534 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2535 				       enum mlxsw_reg_pxbt_op op,
2536 				       u16 local_port, u16 acl_info)
2537 {
2538 	MLXSW_REG_ZERO(ppbt, payload);
2539 	mlxsw_reg_ppbt_e_set(payload, e);
2540 	mlxsw_reg_ppbt_op_set(payload, op);
2541 	mlxsw_reg_ppbt_local_port_set(payload, local_port);
2542 	mlxsw_reg_ppbt_g_set(payload, true);
2543 	mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2544 }
2545 
2546 /* PACL - Policy-Engine ACL Register
2547  * ---------------------------------
2548  * This register is used for configuration of the ACL.
2549  */
2550 #define MLXSW_REG_PACL_ID 0x3004
2551 #define MLXSW_REG_PACL_LEN 0x70
2552 
2553 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2554 
2555 /* reg_pacl_v
2556  * Valid. Setting the v bit makes the ACL valid. It should not be cleared
2557  * while the ACL is bounded to either a port, VLAN or ACL rule.
2558  * Access: RW
2559  */
2560 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2561 
2562 /* reg_pacl_acl_id
2563  * An identifier representing the ACL (managed by software)
2564  * Range 0 .. cap_max_acl_regions - 1
2565  * Access: Index
2566  */
2567 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2568 
2569 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2570 
2571 /* reg_pacl_tcam_region_info
2572  * Opaque object that represents a TCAM region.
2573  * Obtained through PTAR register.
2574  * Access: RW
2575  */
2576 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2577 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2578 
mlxsw_reg_pacl_pack(char * payload,u16 acl_id,bool valid,const char * tcam_region_info)2579 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2580 				       bool valid, const char *tcam_region_info)
2581 {
2582 	MLXSW_REG_ZERO(pacl, payload);
2583 	mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2584 	mlxsw_reg_pacl_v_set(payload, valid);
2585 	mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2586 }
2587 
2588 /* PAGT - Policy-Engine ACL Group Table
2589  * ------------------------------------
2590  * This register is used for configuration of the ACL Group Table.
2591  */
2592 #define MLXSW_REG_PAGT_ID 0x3005
2593 #define MLXSW_REG_PAGT_BASE_LEN 0x30
2594 #define MLXSW_REG_PAGT_ACL_LEN 4
2595 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2596 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2597 		MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2598 
2599 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2600 
2601 /* reg_pagt_size
2602  * Number of ACLs in the group.
2603  * Size 0 invalidates a group.
2604  * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
2605  * Total number of ACLs in all groups must be lower or equal
2606  * to cap_max_acl_tot_groups
2607  * Note: a group which is binded must not be invalidated
2608  * Access: Index
2609  */
2610 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2611 
2612 /* reg_pagt_acl_group_id
2613  * An identifier (numbered from 0..cap_max_acl_groups-1) representing
2614  * the ACL Group identifier (managed by software).
2615  * Access: Index
2616  */
2617 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2618 
2619 /* reg_pagt_multi
2620  * Multi-ACL
2621  * 0 - This ACL is the last ACL in the multi-ACL
2622  * 1 - This ACL is part of a multi-ACL
2623  * Access: RW
2624  */
2625 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2626 
2627 /* reg_pagt_acl_id
2628  * ACL identifier
2629  * Access: RW
2630  */
2631 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2632 
mlxsw_reg_pagt_pack(char * payload,u16 acl_group_id)2633 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2634 {
2635 	MLXSW_REG_ZERO(pagt, payload);
2636 	mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2637 }
2638 
mlxsw_reg_pagt_acl_id_pack(char * payload,int index,u16 acl_id,bool multi)2639 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2640 					      u16 acl_id, bool multi)
2641 {
2642 	u8 size = mlxsw_reg_pagt_size_get(payload);
2643 
2644 	if (index >= size)
2645 		mlxsw_reg_pagt_size_set(payload, index + 1);
2646 	mlxsw_reg_pagt_multi_set(payload, index, multi);
2647 	mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2648 }
2649 
2650 /* PTAR - Policy-Engine TCAM Allocation Register
2651  * ---------------------------------------------
2652  * This register is used for allocation of regions in the TCAM.
2653  * Note: Query method is not supported on this register.
2654  */
2655 #define MLXSW_REG_PTAR_ID 0x3006
2656 #define MLXSW_REG_PTAR_BASE_LEN 0x20
2657 #define MLXSW_REG_PTAR_KEY_ID_LEN 1
2658 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2659 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2660 		MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2661 
2662 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2663 
2664 enum mlxsw_reg_ptar_op {
2665 	/* allocate a TCAM region */
2666 	MLXSW_REG_PTAR_OP_ALLOC,
2667 	/* resize a TCAM region */
2668 	MLXSW_REG_PTAR_OP_RESIZE,
2669 	/* deallocate TCAM region */
2670 	MLXSW_REG_PTAR_OP_FREE,
2671 	/* test allocation */
2672 	MLXSW_REG_PTAR_OP_TEST,
2673 };
2674 
2675 /* reg_ptar_op
2676  * Access: OP
2677  */
2678 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2679 
2680 /* reg_ptar_action_set_type
2681  * Type of action set to be used on this region.
2682  * For Spectrum and Spectrum-2, this is always type 2 - "flexible"
2683  * Access: WO
2684  */
2685 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2686 
2687 enum mlxsw_reg_ptar_key_type {
2688 	MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */
2689 	MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */
2690 };
2691 
2692 /* reg_ptar_key_type
2693  * TCAM key type for the region.
2694  * Access: WO
2695  */
2696 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2697 
2698 /* reg_ptar_region_size
2699  * TCAM region size. When allocating/resizing this is the requested size,
2700  * the response is the actual size. Note that actual size may be
2701  * larger than requested.
2702  * Allowed range 1 .. cap_max_rules-1
2703  * Reserved during op deallocate.
2704  * Access: WO
2705  */
2706 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2707 
2708 /* reg_ptar_region_id
2709  * Region identifier
2710  * Range 0 .. cap_max_regions-1
2711  * Access: Index
2712  */
2713 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2714 
2715 /* reg_ptar_tcam_region_info
2716  * Opaque object that represents the TCAM region.
2717  * Returned when allocating a region.
2718  * Provided by software for ACL generation and region deallocation and resize.
2719  * Access: RW
2720  */
2721 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2722 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2723 
2724 /* reg_ptar_flexible_key_id
2725  * Identifier of the Flexible Key.
2726  * Only valid if key_type == "FLEX_KEY"
2727  * The key size will be rounded up to one of the following values:
2728  * 9B, 18B, 36B, 54B.
2729  * This field is reserved for in resize operation.
2730  * Access: WO
2731  */
2732 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2733 		    MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2734 
mlxsw_reg_ptar_pack(char * payload,enum mlxsw_reg_ptar_op op,enum mlxsw_reg_ptar_key_type key_type,u16 region_size,u16 region_id,const char * tcam_region_info)2735 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2736 				       enum mlxsw_reg_ptar_key_type key_type,
2737 				       u16 region_size, u16 region_id,
2738 				       const char *tcam_region_info)
2739 {
2740 	MLXSW_REG_ZERO(ptar, payload);
2741 	mlxsw_reg_ptar_op_set(payload, op);
2742 	mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */
2743 	mlxsw_reg_ptar_key_type_set(payload, key_type);
2744 	mlxsw_reg_ptar_region_size_set(payload, region_size);
2745 	mlxsw_reg_ptar_region_id_set(payload, region_id);
2746 	mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2747 }
2748 
mlxsw_reg_ptar_key_id_pack(char * payload,int index,u16 key_id)2749 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2750 					      u16 key_id)
2751 {
2752 	mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2753 }
2754 
mlxsw_reg_ptar_unpack(char * payload,char * tcam_region_info)2755 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2756 {
2757 	mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2758 }
2759 
2760 /* PPBS - Policy-Engine Policy Based Switching Register
2761  * ----------------------------------------------------
2762  * This register retrieves and sets Policy Based Switching Table entries.
2763  */
2764 #define MLXSW_REG_PPBS_ID 0x300C
2765 #define MLXSW_REG_PPBS_LEN 0x14
2766 
2767 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2768 
2769 /* reg_ppbs_pbs_ptr
2770  * Index into the PBS table.
2771  * For Spectrum, the index points to the KVD Linear.
2772  * Access: Index
2773  */
2774 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2775 
2776 /* reg_ppbs_system_port
2777  * Unique port identifier for the final destination of the packet.
2778  * Access: RW
2779  */
2780 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2781 
mlxsw_reg_ppbs_pack(char * payload,u32 pbs_ptr,u16 system_port)2782 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2783 				       u16 system_port)
2784 {
2785 	MLXSW_REG_ZERO(ppbs, payload);
2786 	mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2787 	mlxsw_reg_ppbs_system_port_set(payload, system_port);
2788 }
2789 
2790 /* PRCR - Policy-Engine Rules Copy Register
2791  * ----------------------------------------
2792  * This register is used for accessing rules within a TCAM region.
2793  */
2794 #define MLXSW_REG_PRCR_ID 0x300D
2795 #define MLXSW_REG_PRCR_LEN 0x40
2796 
2797 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2798 
2799 enum mlxsw_reg_prcr_op {
2800 	/* Move rules. Moves the rules from "tcam_region_info" starting
2801 	 * at offset "offset" to "dest_tcam_region_info"
2802 	 * at offset "dest_offset."
2803 	 */
2804 	MLXSW_REG_PRCR_OP_MOVE,
2805 	/* Copy rules. Copies the rules from "tcam_region_info" starting
2806 	 * at offset "offset" to "dest_tcam_region_info"
2807 	 * at offset "dest_offset."
2808 	 */
2809 	MLXSW_REG_PRCR_OP_COPY,
2810 };
2811 
2812 /* reg_prcr_op
2813  * Access: OP
2814  */
2815 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2816 
2817 /* reg_prcr_offset
2818  * Offset within the source region to copy/move from.
2819  * Access: Index
2820  */
2821 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2822 
2823 /* reg_prcr_size
2824  * The number of rules to copy/move.
2825  * Access: WO
2826  */
2827 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2828 
2829 /* reg_prcr_tcam_region_info
2830  * Opaque object that represents the source TCAM region.
2831  * Access: Index
2832  */
2833 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2834 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2835 
2836 /* reg_prcr_dest_offset
2837  * Offset within the source region to copy/move to.
2838  * Access: Index
2839  */
2840 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2841 
2842 /* reg_prcr_dest_tcam_region_info
2843  * Opaque object that represents the destination TCAM region.
2844  * Access: Index
2845  */
2846 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2847 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2848 
mlxsw_reg_prcr_pack(char * payload,enum mlxsw_reg_prcr_op op,const char * src_tcam_region_info,u16 src_offset,const char * dest_tcam_region_info,u16 dest_offset,u16 size)2849 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2850 				       const char *src_tcam_region_info,
2851 				       u16 src_offset,
2852 				       const char *dest_tcam_region_info,
2853 				       u16 dest_offset, u16 size)
2854 {
2855 	MLXSW_REG_ZERO(prcr, payload);
2856 	mlxsw_reg_prcr_op_set(payload, op);
2857 	mlxsw_reg_prcr_offset_set(payload, src_offset);
2858 	mlxsw_reg_prcr_size_set(payload, size);
2859 	mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2860 						  src_tcam_region_info);
2861 	mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2862 	mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2863 						       dest_tcam_region_info);
2864 }
2865 
2866 /* PEFA - Policy-Engine Extended Flexible Action Register
2867  * ------------------------------------------------------
2868  * This register is used for accessing an extended flexible action entry
2869  * in the central KVD Linear Database.
2870  */
2871 #define MLXSW_REG_PEFA_ID 0x300F
2872 #define MLXSW_REG_PEFA_LEN 0xB0
2873 
2874 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2875 
2876 /* reg_pefa_index
2877  * Index in the KVD Linear Centralized Database.
2878  * Access: Index
2879  */
2880 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2881 
2882 /* reg_pefa_a
2883  * Index in the KVD Linear Centralized Database.
2884  * Activity
2885  * For a new entry: set if ca=0, clear if ca=1
2886  * Set if a packet lookup has hit on the specific entry
2887  * Access: RO
2888  */
2889 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2890 
2891 /* reg_pefa_ca
2892  * Clear activity
2893  * When write: activity is according to this field
2894  * When read: after reading the activity is cleared according to ca
2895  * Access: OP
2896  */
2897 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2898 
2899 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2900 
2901 /* reg_pefa_flex_action_set
2902  * Action-set to perform when rule is matched.
2903  * Must be zero padded if action set is shorter.
2904  * Access: RW
2905  */
2906 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2907 
mlxsw_reg_pefa_pack(char * payload,u32 index,bool ca,const char * flex_action_set)2908 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2909 				       const char *flex_action_set)
2910 {
2911 	MLXSW_REG_ZERO(pefa, payload);
2912 	mlxsw_reg_pefa_index_set(payload, index);
2913 	mlxsw_reg_pefa_ca_set(payload, ca);
2914 	if (flex_action_set)
2915 		mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2916 							 flex_action_set);
2917 }
2918 
mlxsw_reg_pefa_unpack(char * payload,bool * p_a)2919 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2920 {
2921 	*p_a = mlxsw_reg_pefa_a_get(payload);
2922 }
2923 
2924 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register
2925  * --------------------------------------------------------------
2926  * This register is used for binding Multicast router to an ACL group
2927  * that serves the MC router.
2928  * This register is not supported by SwitchX/-2 and Spectrum.
2929  */
2930 #define MLXSW_REG_PEMRBT_ID 0x3014
2931 #define MLXSW_REG_PEMRBT_LEN 0x14
2932 
2933 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
2934 
2935 enum mlxsw_reg_pemrbt_protocol {
2936 	MLXSW_REG_PEMRBT_PROTO_IPV4,
2937 	MLXSW_REG_PEMRBT_PROTO_IPV6,
2938 };
2939 
2940 /* reg_pemrbt_protocol
2941  * Access: Index
2942  */
2943 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
2944 
2945 /* reg_pemrbt_group_id
2946  * ACL group identifier.
2947  * Range 0..cap_max_acl_groups-1
2948  * Access: RW
2949  */
2950 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
2951 
2952 static inline void
mlxsw_reg_pemrbt_pack(char * payload,enum mlxsw_reg_pemrbt_protocol protocol,u16 group_id)2953 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
2954 		      u16 group_id)
2955 {
2956 	MLXSW_REG_ZERO(pemrbt, payload);
2957 	mlxsw_reg_pemrbt_protocol_set(payload, protocol);
2958 	mlxsw_reg_pemrbt_group_id_set(payload, group_id);
2959 }
2960 
2961 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
2962  * -----------------------------------------------------
2963  * This register is used for accessing rules within a TCAM region.
2964  * It is a new version of PTCE in order to support wider key,
2965  * mask and action within a TCAM region. This register is not supported
2966  * by SwitchX and SwitchX-2.
2967  */
2968 #define MLXSW_REG_PTCE2_ID 0x3017
2969 #define MLXSW_REG_PTCE2_LEN 0x1D8
2970 
2971 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2972 
2973 /* reg_ptce2_v
2974  * Valid.
2975  * Access: RW
2976  */
2977 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2978 
2979 /* reg_ptce2_a
2980  * Activity. Set if a packet lookup has hit on the specific entry.
2981  * To clear the "a" bit, use "clear activity" op or "clear on read" op.
2982  * Access: RO
2983  */
2984 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2985 
2986 enum mlxsw_reg_ptce2_op {
2987 	/* Read operation. */
2988 	MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2989 	/* clear on read operation. Used to read entry
2990 	 * and clear Activity bit.
2991 	 */
2992 	MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2993 	/* Write operation. Used to write a new entry to the table.
2994 	 * All R/W fields are relevant for new entry. Activity bit is set
2995 	 * for new entries - Note write with v = 0 will delete the entry.
2996 	 */
2997 	MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2998 	/* Update action. Only action set will be updated. */
2999 	MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
3000 	/* Clear activity. A bit is cleared for the entry. */
3001 	MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
3002 };
3003 
3004 /* reg_ptce2_op
3005  * Access: OP
3006  */
3007 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
3008 
3009 /* reg_ptce2_offset
3010  * Access: Index
3011  */
3012 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
3013 
3014 /* reg_ptce2_priority
3015  * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.
3016  * Note: priority does not have to be unique per rule.
3017  * Within a region, higher priority should have lower offset (no limitation
3018  * between regions in a multi-region).
3019  * Access: RW
3020  */
3021 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
3022 
3023 /* reg_ptce2_tcam_region_info
3024  * Opaque object that represents the TCAM region.
3025  * Access: Index
3026  */
3027 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
3028 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
3029 
3030 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
3031 
3032 /* reg_ptce2_flex_key_blocks
3033  * ACL Key.
3034  * Access: RW
3035  */
3036 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
3037 	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3038 
3039 /* reg_ptce2_mask
3040  * mask- in the same size as key. A bit that is set directs the TCAM
3041  * to compare the corresponding bit in key. A bit that is clear directs
3042  * the TCAM to ignore the corresponding bit in key.
3043  * Access: RW
3044  */
3045 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
3046 	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3047 
3048 /* reg_ptce2_flex_action_set
3049  * ACL action set.
3050  * Access: RW
3051  */
3052 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
3053 	       MLXSW_REG_FLEX_ACTION_SET_LEN);
3054 
mlxsw_reg_ptce2_pack(char * payload,bool valid,enum mlxsw_reg_ptce2_op op,const char * tcam_region_info,u16 offset,u32 priority)3055 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
3056 					enum mlxsw_reg_ptce2_op op,
3057 					const char *tcam_region_info,
3058 					u16 offset, u32 priority)
3059 {
3060 	MLXSW_REG_ZERO(ptce2, payload);
3061 	mlxsw_reg_ptce2_v_set(payload, valid);
3062 	mlxsw_reg_ptce2_op_set(payload, op);
3063 	mlxsw_reg_ptce2_offset_set(payload, offset);
3064 	mlxsw_reg_ptce2_priority_set(payload, priority);
3065 	mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
3066 }
3067 
3068 /* PERPT - Policy-Engine ERP Table Register
3069  * ----------------------------------------
3070  * This register adds and removes eRPs from the eRP table.
3071  */
3072 #define MLXSW_REG_PERPT_ID 0x3021
3073 #define MLXSW_REG_PERPT_LEN 0x80
3074 
3075 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
3076 
3077 /* reg_perpt_erpt_bank
3078  * eRP table bank.
3079  * Range 0 .. cap_max_erp_table_banks - 1
3080  * Access: Index
3081  */
3082 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
3083 
3084 /* reg_perpt_erpt_index
3085  * Index to eRP table within the eRP bank.
3086  * Range is 0 .. cap_max_erp_table_bank_size - 1
3087  * Access: Index
3088  */
3089 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
3090 
3091 enum mlxsw_reg_perpt_key_size {
3092 	MLXSW_REG_PERPT_KEY_SIZE_2KB,
3093 	MLXSW_REG_PERPT_KEY_SIZE_4KB,
3094 	MLXSW_REG_PERPT_KEY_SIZE_8KB,
3095 	MLXSW_REG_PERPT_KEY_SIZE_12KB,
3096 };
3097 
3098 /* reg_perpt_key_size
3099  * Access: OP
3100  */
3101 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
3102 
3103 /* reg_perpt_bf_bypass
3104  * 0 - The eRP is used only if bloom filter state is set for the given
3105  * rule.
3106  * 1 - The eRP is used regardless of bloom filter state.
3107  * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass
3108  * Access: RW
3109  */
3110 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
3111 
3112 /* reg_perpt_erp_id
3113  * eRP ID for use by the rules.
3114  * Access: RW
3115  */
3116 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
3117 
3118 /* reg_perpt_erpt_base_bank
3119  * Base eRP table bank, points to head of erp_vector
3120  * Range is 0 .. cap_max_erp_table_banks - 1
3121  * Access: OP
3122  */
3123 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
3124 
3125 /* reg_perpt_erpt_base_index
3126  * Base index to eRP table within the eRP bank
3127  * Range is 0 .. cap_max_erp_table_bank_size - 1
3128  * Access: OP
3129  */
3130 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
3131 
3132 /* reg_perpt_erp_index_in_vector
3133  * eRP index in the vector.
3134  * Access: OP
3135  */
3136 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
3137 
3138 /* reg_perpt_erp_vector
3139  * eRP vector.
3140  * Access: OP
3141  */
3142 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
3143 
3144 /* reg_perpt_mask
3145  * Mask
3146  * 0 - A-TCAM will ignore the bit in key
3147  * 1 - A-TCAM will compare the bit in key
3148  * Access: RW
3149  */
3150 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3151 
mlxsw_reg_perpt_erp_vector_pack(char * payload,unsigned long * erp_vector,unsigned long size)3152 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
3153 						   unsigned long *erp_vector,
3154 						   unsigned long size)
3155 {
3156 	unsigned long bit;
3157 
3158 	for_each_set_bit(bit, erp_vector, size)
3159 		mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
3160 }
3161 
3162 static inline void
mlxsw_reg_perpt_pack(char * payload,u8 erpt_bank,u8 erpt_index,enum mlxsw_reg_perpt_key_size key_size,u8 erp_id,u8 erpt_base_bank,u8 erpt_base_index,u8 erp_index,char * mask)3163 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
3164 		     enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
3165 		     u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
3166 		     char *mask)
3167 {
3168 	MLXSW_REG_ZERO(perpt, payload);
3169 	mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
3170 	mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
3171 	mlxsw_reg_perpt_key_size_set(payload, key_size);
3172 	mlxsw_reg_perpt_bf_bypass_set(payload, false);
3173 	mlxsw_reg_perpt_erp_id_set(payload, erp_id);
3174 	mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
3175 	mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
3176 	mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
3177 	mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
3178 }
3179 
3180 /* PERAR - Policy-Engine Region Association Register
3181  * -------------------------------------------------
3182  * This register associates a hw region for region_id's. Changing on the fly
3183  * is supported by the device.
3184  */
3185 #define MLXSW_REG_PERAR_ID 0x3026
3186 #define MLXSW_REG_PERAR_LEN 0x08
3187 
3188 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
3189 
3190 /* reg_perar_region_id
3191  * Region identifier
3192  * Range 0 .. cap_max_regions-1
3193  * Access: Index
3194  */
3195 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
3196 
3197 static inline unsigned int
mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)3198 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
3199 {
3200 	return DIV_ROUND_UP(block_num, 4);
3201 }
3202 
3203 /* reg_perar_hw_region
3204  * HW Region
3205  * Range 0 .. cap_max_regions-1
3206  * Default: hw_region = region_id
3207  * For a 8 key block region, 2 consecutive regions are used
3208  * For a 12 key block region, 3 consecutive regions are used
3209  * Access: RW
3210  */
3211 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
3212 
mlxsw_reg_perar_pack(char * payload,u16 region_id,u16 hw_region)3213 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
3214 					u16 hw_region)
3215 {
3216 	MLXSW_REG_ZERO(perar, payload);
3217 	mlxsw_reg_perar_region_id_set(payload, region_id);
3218 	mlxsw_reg_perar_hw_region_set(payload, hw_region);
3219 }
3220 
3221 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3
3222  * -----------------------------------------------------
3223  * This register is a new version of PTCE-V2 in order to support the
3224  * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
3225  */
3226 #define MLXSW_REG_PTCE3_ID 0x3027
3227 #define MLXSW_REG_PTCE3_LEN 0xF0
3228 
3229 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
3230 
3231 /* reg_ptce3_v
3232  * Valid.
3233  * Access: RW
3234  */
3235 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
3236 
3237 enum mlxsw_reg_ptce3_op {
3238 	/* Write operation. Used to write a new entry to the table.
3239 	 * All R/W fields are relevant for new entry. Activity bit is set
3240 	 * for new entries. Write with v = 0 will delete the entry. Must
3241 	 * not be used if an entry exists.
3242 	 */
3243 	 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
3244 	 /* Update operation */
3245 	 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
3246 	 /* Read operation */
3247 	 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
3248 };
3249 
3250 /* reg_ptce3_op
3251  * Access: OP
3252  */
3253 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
3254 
3255 /* reg_ptce3_priority
3256  * Priority of the rule. Higher values win.
3257  * For Spectrum-2 range is 1..cap_kvd_size - 1
3258  * Note: Priority does not have to be unique per rule.
3259  * Access: RW
3260  */
3261 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
3262 
3263 /* reg_ptce3_tcam_region_info
3264  * Opaque object that represents the TCAM region.
3265  * Access: Index
3266  */
3267 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
3268 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
3269 
3270 /* reg_ptce3_flex2_key_blocks
3271  * ACL key. The key must be masked according to eRP (if exists) or
3272  * according to master mask.
3273  * Access: Index
3274  */
3275 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
3276 	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3277 
3278 /* reg_ptce3_erp_id
3279  * eRP ID.
3280  * Access: Index
3281  */
3282 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
3283 
3284 /* reg_ptce3_delta_start
3285  * Start point of delta_value and delta_mask, in bits. Must not exceed
3286  * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.
3287  * Access: Index
3288  */
3289 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
3290 
3291 /* reg_ptce3_delta_mask
3292  * Delta mask.
3293  * 0 - Ignore relevant bit in delta_value
3294  * 1 - Compare relevant bit in delta_value
3295  * Delta mask must not be set for reserved fields in the key blocks.
3296  * Note: No delta when no eRPs. Thus, for regions with
3297  * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.
3298  * Access: Index
3299  */
3300 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
3301 
3302 /* reg_ptce3_delta_value
3303  * Delta value.
3304  * Bits which are masked by delta_mask must be 0.
3305  * Access: Index
3306  */
3307 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
3308 
3309 /* reg_ptce3_prune_vector
3310  * Pruning vector relative to the PERPT.erp_id.
3311  * Used for reducing lookups.
3312  * 0 - NEED: Do a lookup using the eRP.
3313  * 1 - PRUNE: Do not perform a lookup using the eRP.
3314  * Maybe be modified by PEAPBL and PEAPBM.
3315  * Note: In Spectrum-2, a region of 8 key blocks must be set to either
3316  * all 1's or all 0's.
3317  * Access: RW
3318  */
3319 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
3320 
3321 /* reg_ptce3_prune_ctcam
3322  * Pruning on C-TCAM. Used for reducing lookups.
3323  * 0 - NEED: Do a lookup in the C-TCAM.
3324  * 1 - PRUNE: Do not perform a lookup in the C-TCAM.
3325  * Access: RW
3326  */
3327 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
3328 
3329 /* reg_ptce3_large_exists
3330  * Large entry key ID exists.
3331  * Within the region:
3332  * 0 - SINGLE: The large_entry_key_id is not currently in use.
3333  * For rule insert: The MSB of the key (blocks 6..11) will be added.
3334  * For rule delete: The MSB of the key will be removed.
3335  * 1 - NON_SINGLE: The large_entry_key_id is currently in use.
3336  * For rule insert: The MSB of the key (blocks 6..11) will not be added.
3337  * For rule delete: The MSB of the key will not be removed.
3338  * Access: WO
3339  */
3340 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
3341 
3342 /* reg_ptce3_large_entry_key_id
3343  * Large entry key ID.
3344  * A key for 12 key blocks rules. Reserved when region has less than 12 key
3345  * blocks. Must be different for different keys which have the same common
3346  * 6 key blocks (MSB, blocks 6..11) key within a region.
3347  * Range is 0..cap_max_pe_large_key_id - 1
3348  * Access: RW
3349  */
3350 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
3351 
3352 /* reg_ptce3_action_pointer
3353  * Pointer to action.
3354  * Range is 0..cap_max_kvd_action_sets - 1
3355  * Access: RW
3356  */
3357 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
3358 
mlxsw_reg_ptce3_pack(char * payload,bool valid,enum mlxsw_reg_ptce3_op op,u32 priority,const char * tcam_region_info,const char * key,u8 erp_id,u16 delta_start,u8 delta_mask,u8 delta_value,bool large_exists,u32 lkey_id,u32 action_pointer)3359 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
3360 					enum mlxsw_reg_ptce3_op op,
3361 					u32 priority,
3362 					const char *tcam_region_info,
3363 					const char *key, u8 erp_id,
3364 					u16 delta_start, u8 delta_mask,
3365 					u8 delta_value, bool large_exists,
3366 					u32 lkey_id, u32 action_pointer)
3367 {
3368 	MLXSW_REG_ZERO(ptce3, payload);
3369 	mlxsw_reg_ptce3_v_set(payload, valid);
3370 	mlxsw_reg_ptce3_op_set(payload, op);
3371 	mlxsw_reg_ptce3_priority_set(payload, priority);
3372 	mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
3373 	mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
3374 	mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
3375 	mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
3376 	mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
3377 	mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
3378 	mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
3379 	mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
3380 	mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
3381 }
3382 
3383 /* PERCR - Policy-Engine Region Configuration Register
3384  * ---------------------------------------------------
3385  * This register configures the region parameters. The region_id must be
3386  * allocated.
3387  */
3388 #define MLXSW_REG_PERCR_ID 0x302A
3389 #define MLXSW_REG_PERCR_LEN 0x80
3390 
3391 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
3392 
3393 /* reg_percr_region_id
3394  * Region identifier.
3395  * Range 0..cap_max_regions-1
3396  * Access: Index
3397  */
3398 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
3399 
3400 /* reg_percr_atcam_ignore_prune
3401  * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.
3402  * Access: RW
3403  */
3404 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
3405 
3406 /* reg_percr_ctcam_ignore_prune
3407  * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.
3408  * Access: RW
3409  */
3410 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
3411 
3412 /* reg_percr_bf_bypass
3413  * Bloom filter bypass.
3414  * 0 - Bloom filter is used (default)
3415  * 1 - Bloom filter is bypassed. The bypass is an OR condition of
3416  * region_id or eRP. See PERPT.bf_bypass
3417  * Access: RW
3418  */
3419 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3420 
3421 /* reg_percr_master_mask
3422  * Master mask. Logical OR mask of all masks of all rules of a region
3423  * (both A-TCAM and C-TCAM). When there are no eRPs
3424  * (erpt_pointer_valid = 0), then this provides the mask.
3425  * Access: RW
3426  */
3427 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3428 
mlxsw_reg_percr_pack(char * payload,u16 region_id)3429 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3430 {
3431 	MLXSW_REG_ZERO(percr, payload);
3432 	mlxsw_reg_percr_region_id_set(payload, region_id);
3433 	mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
3434 	mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
3435 	mlxsw_reg_percr_bf_bypass_set(payload, false);
3436 }
3437 
3438 /* PERERP - Policy-Engine Region eRP Register
3439  * ------------------------------------------
3440  * This register configures the region eRP. The region_id must be
3441  * allocated.
3442  */
3443 #define MLXSW_REG_PERERP_ID 0x302B
3444 #define MLXSW_REG_PERERP_LEN 0x1C
3445 
3446 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3447 
3448 /* reg_pererp_region_id
3449  * Region identifier.
3450  * Range 0..cap_max_regions-1
3451  * Access: Index
3452  */
3453 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3454 
3455 /* reg_pererp_ctcam_le
3456  * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
3457  * Access: RW
3458  */
3459 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3460 
3461 /* reg_pererp_erpt_pointer_valid
3462  * erpt_pointer is valid.
3463  * Access: RW
3464  */
3465 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3466 
3467 /* reg_pererp_erpt_bank_pointer
3468  * Pointer to eRP table bank. May be modified at any time.
3469  * Range 0..cap_max_erp_table_banks-1
3470  * Reserved when erpt_pointer_valid = 0
3471  */
3472 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3473 
3474 /* reg_pererp_erpt_pointer
3475  * Pointer to eRP table within the eRP bank. Can be changed for an
3476  * existing region.
3477  * Range 0..cap_max_erp_table_size-1
3478  * Reserved when erpt_pointer_valid = 0
3479  * Access: RW
3480  */
3481 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3482 
3483 /* reg_pererp_erpt_vector
3484  * Vector of allowed eRP indexes starting from erpt_pointer within the
3485  * erpt_bank_pointer. Next entries will be in next bank.
3486  * Note that eRP index is used and not eRP ID.
3487  * Reserved when erpt_pointer_valid = 0
3488  * Access: RW
3489  */
3490 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3491 
3492 /* reg_pererp_master_rp_id
3493  * Master RP ID. When there are no eRPs, then this provides the eRP ID
3494  * for the lookup. Can be changed for an existing region.
3495  * Reserved when erpt_pointer_valid = 1
3496  * Access: RW
3497  */
3498 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3499 
mlxsw_reg_pererp_erp_vector_pack(char * payload,unsigned long * erp_vector,unsigned long size)3500 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3501 						    unsigned long *erp_vector,
3502 						    unsigned long size)
3503 {
3504 	unsigned long bit;
3505 
3506 	for_each_set_bit(bit, erp_vector, size)
3507 		mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
3508 }
3509 
mlxsw_reg_pererp_pack(char * payload,u16 region_id,bool ctcam_le,bool erpt_pointer_valid,u8 erpt_bank_pointer,u8 erpt_pointer,u8 master_rp_id)3510 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3511 					 bool ctcam_le, bool erpt_pointer_valid,
3512 					 u8 erpt_bank_pointer, u8 erpt_pointer,
3513 					 u8 master_rp_id)
3514 {
3515 	MLXSW_REG_ZERO(pererp, payload);
3516 	mlxsw_reg_pererp_region_id_set(payload, region_id);
3517 	mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
3518 	mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
3519 	mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
3520 	mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
3521 	mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
3522 }
3523 
3524 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register
3525  * ----------------------------------------------------------------
3526  * This register configures the Bloom filter entries.
3527  */
3528 #define MLXSW_REG_PEABFE_ID 0x3022
3529 #define MLXSW_REG_PEABFE_BASE_LEN 0x10
3530 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3531 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3532 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3533 			      MLXSW_REG_PEABFE_BF_REC_LEN * \
3534 			      MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3535 
3536 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3537 
3538 /* reg_peabfe_size
3539  * Number of BF entries to be updated.
3540  * Range 1..256
3541  * Access: Op
3542  */
3543 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3544 
3545 /* reg_peabfe_bf_entry_state
3546  * Bloom filter state
3547  * 0 - Clear
3548  * 1 - Set
3549  * Access: RW
3550  */
3551 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3552 		     MLXSW_REG_PEABFE_BASE_LEN,	31, 1,
3553 		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3554 
3555 /* reg_peabfe_bf_entry_bank
3556  * Bloom filter bank ID
3557  * Range 0..cap_max_erp_table_banks-1
3558  * Access: Index
3559  */
3560 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3561 		     MLXSW_REG_PEABFE_BASE_LEN,	24, 4,
3562 		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3563 
3564 /* reg_peabfe_bf_entry_index
3565  * Bloom filter entry index
3566  * Range 0..2^cap_max_bf_log-1
3567  * Access: Index
3568  */
3569 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3570 		     MLXSW_REG_PEABFE_BASE_LEN,	0, 24,
3571 		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3572 
mlxsw_reg_peabfe_pack(char * payload)3573 static inline void mlxsw_reg_peabfe_pack(char *payload)
3574 {
3575 	MLXSW_REG_ZERO(peabfe, payload);
3576 }
3577 
mlxsw_reg_peabfe_rec_pack(char * payload,int rec_index,u8 state,u8 bank,u32 bf_index)3578 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3579 					     u8 state, u8 bank, u32 bf_index)
3580 {
3581 	u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
3582 
3583 	if (rec_index >= num_rec)
3584 		mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
3585 	mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
3586 	mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
3587 	mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
3588 }
3589 
3590 /* IEDR - Infrastructure Entry Delete Register
3591  * ----------------------------------------------------
3592  * This register is used for deleting entries from the entry tables.
3593  * It is legitimate to attempt to delete a nonexisting entry (the device will
3594  * respond as a good flow).
3595  */
3596 #define MLXSW_REG_IEDR_ID 0x3804
3597 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */
3598 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */
3599 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3600 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN +	\
3601 			    MLXSW_REG_IEDR_REC_LEN *	\
3602 			    MLXSW_REG_IEDR_REC_MAX_COUNT)
3603 
3604 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3605 
3606 /* reg_iedr_num_rec
3607  * Number of records.
3608  * Access: OP
3609  */
3610 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3611 
3612 /* reg_iedr_rec_type
3613  * Resource type.
3614  * Access: OP
3615  */
3616 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3617 		     MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3618 
3619 /* reg_iedr_rec_size
3620  * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
3621  * Access: OP
3622  */
3623 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13,
3624 		     MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3625 
3626 /* reg_iedr_rec_index_start
3627  * Resource index start.
3628  * Access: OP
3629  */
3630 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3631 		     MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3632 
mlxsw_reg_iedr_pack(char * payload)3633 static inline void mlxsw_reg_iedr_pack(char *payload)
3634 {
3635 	MLXSW_REG_ZERO(iedr, payload);
3636 }
3637 
mlxsw_reg_iedr_rec_pack(char * payload,int rec_index,u8 rec_type,u16 rec_size,u32 rec_index_start)3638 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3639 					   u8 rec_type, u16 rec_size,
3640 					   u32 rec_index_start)
3641 {
3642 	u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3643 
3644 	if (rec_index >= num_rec)
3645 		mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3646 	mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3647 	mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3648 	mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3649 }
3650 
3651 /* QPTS - QoS Priority Trust State Register
3652  * ----------------------------------------
3653  * This register controls the port policy to calculate the switch priority and
3654  * packet color based on incoming packet fields.
3655  */
3656 #define MLXSW_REG_QPTS_ID 0x4002
3657 #define MLXSW_REG_QPTS_LEN 0x8
3658 
3659 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3660 
3661 /* reg_qpts_local_port
3662  * Local port number.
3663  * Access: Index
3664  *
3665  * Note: CPU port is supported.
3666  */
3667 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12);
3668 
3669 enum mlxsw_reg_qpts_trust_state {
3670 	MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3671 	MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */
3672 };
3673 
3674 /* reg_qpts_trust_state
3675  * Trust state for a given port.
3676  * Access: RW
3677  */
3678 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3679 
mlxsw_reg_qpts_pack(char * payload,u16 local_port,enum mlxsw_reg_qpts_trust_state ts)3680 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port,
3681 				       enum mlxsw_reg_qpts_trust_state ts)
3682 {
3683 	MLXSW_REG_ZERO(qpts, payload);
3684 
3685 	mlxsw_reg_qpts_local_port_set(payload, local_port);
3686 	mlxsw_reg_qpts_trust_state_set(payload, ts);
3687 }
3688 
3689 /* QPCR - QoS Policer Configuration Register
3690  * -----------------------------------------
3691  * The QPCR register is used to create policers - that limit
3692  * the rate of bytes or packets via some trap group.
3693  */
3694 #define MLXSW_REG_QPCR_ID 0x4004
3695 #define MLXSW_REG_QPCR_LEN 0x28
3696 
3697 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3698 
3699 enum mlxsw_reg_qpcr_g {
3700 	MLXSW_REG_QPCR_G_GLOBAL = 2,
3701 	MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3702 };
3703 
3704 /* reg_qpcr_g
3705  * The policer type.
3706  * Access: Index
3707  */
3708 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3709 
3710 /* reg_qpcr_pid
3711  * Policer ID.
3712  * Access: Index
3713  */
3714 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3715 
3716 /* reg_qpcr_clear_counter
3717  * Clear counters.
3718  * Access: OP
3719  */
3720 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1);
3721 
3722 /* reg_qpcr_color_aware
3723  * Is the policer aware of colors.
3724  * Must be 0 (unaware) for cpu port.
3725  * Access: RW for unbounded policer. RO for bounded policer.
3726  */
3727 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3728 
3729 /* reg_qpcr_bytes
3730  * Is policer limit is for bytes per sec or packets per sec.
3731  * 0 - packets
3732  * 1 - bytes
3733  * Access: RW for unbounded policer. RO for bounded policer.
3734  */
3735 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3736 
3737 enum mlxsw_reg_qpcr_ir_units {
3738 	MLXSW_REG_QPCR_IR_UNITS_M,
3739 	MLXSW_REG_QPCR_IR_UNITS_K,
3740 };
3741 
3742 /* reg_qpcr_ir_units
3743  * Policer's units for cir and eir fields (for bytes limits only)
3744  * 1 - 10^3
3745  * 0 - 10^6
3746  * Access: OP
3747  */
3748 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3749 
3750 enum mlxsw_reg_qpcr_rate_type {
3751 	MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3752 	MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3753 };
3754 
3755 /* reg_qpcr_rate_type
3756  * Policer can have one limit (single rate) or 2 limits with specific operation
3757  * for packets that exceed the lower rate but not the upper one.
3758  * (For cpu port must be single rate)
3759  * Access: RW for unbounded policer. RO for bounded policer.
3760  */
3761 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3762 
3763 /* reg_qpc_cbs
3764  * Policer's committed burst size.
3765  * The policer is working with time slices of 50 nano sec. By default every
3766  * slice is granted the proportionate share of the committed rate. If we want to
3767  * allow a slice to exceed that share (while still keeping the rate per sec) we
3768  * can allow burst. The burst size is between the default proportionate share
3769  * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
3770  * committed rate will result in exceeding the rate). The burst size must be a
3771  * log of 2 and will be determined by 2^cbs.
3772  * Access: RW
3773  */
3774 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3775 
3776 /* reg_qpcr_cir
3777  * Policer's committed rate.
3778  * The rate used for sungle rate, the lower rate for double rate.
3779  * For bytes limits, the rate will be this value * the unit from ir_units.
3780  * (Resolution error is up to 1%).
3781  * Access: RW
3782  */
3783 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3784 
3785 /* reg_qpcr_eir
3786  * Policer's exceed rate.
3787  * The higher rate for double rate, reserved for single rate.
3788  * Lower rate for double rate policer.
3789  * For bytes limits, the rate will be this value * the unit from ir_units.
3790  * (Resolution error is up to 1%).
3791  * Access: RW
3792  */
3793 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3794 
3795 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3796 
3797 /* reg_qpcr_exceed_action.
3798  * What to do with packets between the 2 limits for double rate.
3799  * Access: RW for unbounded policer. RO for bounded policer.
3800  */
3801 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3802 
3803 enum mlxsw_reg_qpcr_action {
3804 	/* Discard */
3805 	MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3806 	/* Forward and set color to red.
3807 	 * If the packet is intended to cpu port, it will be dropped.
3808 	 */
3809 	MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3810 };
3811 
3812 /* reg_qpcr_violate_action
3813  * What to do with packets that cross the cir limit (for single rate) or the eir
3814  * limit (for double rate).
3815  * Access: RW for unbounded policer. RO for bounded policer.
3816  */
3817 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3818 
3819 /* reg_qpcr_violate_count
3820  * Counts the number of times violate_action happened on this PID.
3821  * Access: RW
3822  */
3823 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64);
3824 
3825 /* Packets */
3826 #define MLXSW_REG_QPCR_LOWEST_CIR	1
3827 #define MLXSW_REG_QPCR_HIGHEST_CIR	(2 * 1000 * 1000 * 1000) /* 2Gpps */
3828 #define MLXSW_REG_QPCR_LOWEST_CBS	4
3829 #define MLXSW_REG_QPCR_HIGHEST_CBS	24
3830 
3831 /* Bandwidth */
3832 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS		1024 /* bps */
3833 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS		2000000000000ULL /* 2Tbps */
3834 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1	4
3835 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2	4
3836 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1	25
3837 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2	31
3838 
mlxsw_reg_qpcr_pack(char * payload,u16 pid,enum mlxsw_reg_qpcr_ir_units ir_units,bool bytes,u32 cir,u16 cbs)3839 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3840 				       enum mlxsw_reg_qpcr_ir_units ir_units,
3841 				       bool bytes, u32 cir, u16 cbs)
3842 {
3843 	MLXSW_REG_ZERO(qpcr, payload);
3844 	mlxsw_reg_qpcr_pid_set(payload, pid);
3845 	mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3846 	mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3847 	mlxsw_reg_qpcr_violate_action_set(payload,
3848 					  MLXSW_REG_QPCR_ACTION_DISCARD);
3849 	mlxsw_reg_qpcr_cir_set(payload, cir);
3850 	mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3851 	mlxsw_reg_qpcr_bytes_set(payload, bytes);
3852 	mlxsw_reg_qpcr_cbs_set(payload, cbs);
3853 }
3854 
3855 /* QTCT - QoS Switch Traffic Class Table
3856  * -------------------------------------
3857  * Configures the mapping between the packet switch priority and the
3858  * traffic class on the transmit port.
3859  */
3860 #define MLXSW_REG_QTCT_ID 0x400A
3861 #define MLXSW_REG_QTCT_LEN 0x08
3862 
3863 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3864 
3865 /* reg_qtct_local_port
3866  * Local port number.
3867  * Access: Index
3868  *
3869  * Note: CPU port is not supported.
3870  */
3871 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12);
3872 
3873 /* reg_qtct_sub_port
3874  * Virtual port within the physical port.
3875  * Should be set to 0 when virtual ports are not enabled on the port.
3876  * Access: Index
3877  */
3878 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3879 
3880 /* reg_qtct_switch_prio
3881  * Switch priority.
3882  * Access: Index
3883  */
3884 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3885 
3886 /* reg_qtct_tclass
3887  * Traffic class.
3888  * Default values:
3889  * switch_prio 0 : tclass 1
3890  * switch_prio 1 : tclass 0
3891  * switch_prio i : tclass i, for i > 1
3892  * Access: RW
3893  */
3894 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3895 
mlxsw_reg_qtct_pack(char * payload,u16 local_port,u8 switch_prio,u8 tclass)3896 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port,
3897 				       u8 switch_prio, u8 tclass)
3898 {
3899 	MLXSW_REG_ZERO(qtct, payload);
3900 	mlxsw_reg_qtct_local_port_set(payload, local_port);
3901 	mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3902 	mlxsw_reg_qtct_tclass_set(payload, tclass);
3903 }
3904 
3905 /* QEEC - QoS ETS Element Configuration Register
3906  * ---------------------------------------------
3907  * Configures the ETS elements.
3908  */
3909 #define MLXSW_REG_QEEC_ID 0x400D
3910 #define MLXSW_REG_QEEC_LEN 0x20
3911 
3912 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3913 
3914 /* reg_qeec_local_port
3915  * Local port number.
3916  * Access: Index
3917  *
3918  * Note: CPU port is supported.
3919  */
3920 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12);
3921 
3922 enum mlxsw_reg_qeec_hr {
3923 	MLXSW_REG_QEEC_HR_PORT,
3924 	MLXSW_REG_QEEC_HR_GROUP,
3925 	MLXSW_REG_QEEC_HR_SUBGROUP,
3926 	MLXSW_REG_QEEC_HR_TC,
3927 };
3928 
3929 /* reg_qeec_element_hierarchy
3930  * 0 - Port
3931  * 1 - Group
3932  * 2 - Subgroup
3933  * 3 - Traffic Class
3934  * Access: Index
3935  */
3936 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3937 
3938 /* reg_qeec_element_index
3939  * The index of the element in the hierarchy.
3940  * Access: Index
3941  */
3942 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3943 
3944 /* reg_qeec_next_element_index
3945  * The index of the next (lower) element in the hierarchy.
3946  * Access: RW
3947  *
3948  * Note: Reserved for element_hierarchy 0.
3949  */
3950 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3951 
3952 /* reg_qeec_mise
3953  * Min shaper configuration enable. Enables configuration of the min
3954  * shaper on this ETS element
3955  * 0 - Disable
3956  * 1 - Enable
3957  * Access: RW
3958  */
3959 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3960 
3961 /* reg_qeec_ptps
3962  * PTP shaper
3963  * 0: regular shaper mode
3964  * 1: PTP oriented shaper
3965  * Allowed only for hierarchy 0
3966  * Not supported for CPU port
3967  * Note that ptps mode may affect the shaper rates of all hierarchies
3968  * Supported only on Spectrum-1
3969  * Access: RW
3970  */
3971 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
3972 
3973 enum {
3974 	MLXSW_REG_QEEC_BYTES_MODE,
3975 	MLXSW_REG_QEEC_PACKETS_MODE,
3976 };
3977 
3978 /* reg_qeec_pb
3979  * Packets or bytes mode.
3980  * 0 - Bytes mode
3981  * 1 - Packets mode
3982  * Access: RW
3983  *
3984  * Note: Used for max shaper configuration. For Spectrum, packets mode
3985  * is supported only for traffic classes of CPU port.
3986  */
3987 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3988 
3989 /* The smallest permitted min shaper rate. */
3990 #define MLXSW_REG_QEEC_MIS_MIN	200000		/* Kbps */
3991 
3992 /* reg_qeec_min_shaper_rate
3993  * Min shaper information rate.
3994  * For CPU port, can only be configured for port hierarchy.
3995  * When in bytes mode, value is specified in units of 1000bps.
3996  * Access: RW
3997  */
3998 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3999 
4000 /* reg_qeec_mase
4001  * Max shaper configuration enable. Enables configuration of the max
4002  * shaper on this ETS element.
4003  * 0 - Disable
4004  * 1 - Enable
4005  * Access: RW
4006  */
4007 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
4008 
4009 /* The largest max shaper value possible to disable the shaper. */
4010 #define MLXSW_REG_QEEC_MAS_DIS	((1u << 31) - 1)	/* Kbps */
4011 
4012 /* reg_qeec_max_shaper_rate
4013  * Max shaper information rate.
4014  * For CPU port, can only be configured for port hierarchy.
4015  * When in bytes mode, value is specified in units of 1000bps.
4016  * Access: RW
4017  */
4018 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31);
4019 
4020 /* reg_qeec_de
4021  * DWRR configuration enable. Enables configuration of the dwrr and
4022  * dwrr_weight.
4023  * 0 - Disable
4024  * 1 - Enable
4025  * Access: RW
4026  */
4027 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
4028 
4029 /* reg_qeec_dwrr
4030  * Transmission selection algorithm to use on the link going down from
4031  * the ETS element.
4032  * 0 - Strict priority
4033  * 1 - DWRR
4034  * Access: RW
4035  */
4036 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
4037 
4038 /* reg_qeec_dwrr_weight
4039  * DWRR weight on the link going down from the ETS element. The
4040  * percentage of bandwidth guaranteed to an ETS element within
4041  * its hierarchy. The sum of all weights across all ETS elements
4042  * within one hierarchy should be equal to 100. Reserved when
4043  * transmission selection algorithm is strict priority.
4044  * Access: RW
4045  */
4046 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
4047 
4048 /* reg_qeec_max_shaper_bs
4049  * Max shaper burst size
4050  * Burst size is 2^max_shaper_bs * 512 bits
4051  * For Spectrum-1: Range is: 5..25
4052  * For Spectrum-2: Range is: 11..25
4053  * Reserved when ptps = 1
4054  * Access: RW
4055  */
4056 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);
4057 
4058 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS	25
4059 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1	5
4060 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2	11
4061 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3	11
4062 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4	11
4063 
mlxsw_reg_qeec_pack(char * payload,u16 local_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index)4064 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port,
4065 				       enum mlxsw_reg_qeec_hr hr, u8 index,
4066 				       u8 next_index)
4067 {
4068 	MLXSW_REG_ZERO(qeec, payload);
4069 	mlxsw_reg_qeec_local_port_set(payload, local_port);
4070 	mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
4071 	mlxsw_reg_qeec_element_index_set(payload, index);
4072 	mlxsw_reg_qeec_next_element_index_set(payload, next_index);
4073 }
4074 
mlxsw_reg_qeec_ptps_pack(char * payload,u16 local_port,bool ptps)4075 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port,
4076 					    bool ptps)
4077 {
4078 	MLXSW_REG_ZERO(qeec, payload);
4079 	mlxsw_reg_qeec_local_port_set(payload, local_port);
4080 	mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT);
4081 	mlxsw_reg_qeec_ptps_set(payload, ptps);
4082 }
4083 
4084 /* QRWE - QoS ReWrite Enable
4085  * -------------------------
4086  * This register configures the rewrite enable per receive port.
4087  */
4088 #define MLXSW_REG_QRWE_ID 0x400F
4089 #define MLXSW_REG_QRWE_LEN 0x08
4090 
4091 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
4092 
4093 /* reg_qrwe_local_port
4094  * Local port number.
4095  * Access: Index
4096  *
4097  * Note: CPU port is supported. No support for router port.
4098  */
4099 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12);
4100 
4101 /* reg_qrwe_dscp
4102  * Whether to enable DSCP rewrite (default is 0, don't rewrite).
4103  * Access: RW
4104  */
4105 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
4106 
4107 /* reg_qrwe_pcp
4108  * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
4109  * Access: RW
4110  */
4111 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
4112 
mlxsw_reg_qrwe_pack(char * payload,u16 local_port,bool rewrite_pcp,bool rewrite_dscp)4113 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port,
4114 				       bool rewrite_pcp, bool rewrite_dscp)
4115 {
4116 	MLXSW_REG_ZERO(qrwe, payload);
4117 	mlxsw_reg_qrwe_local_port_set(payload, local_port);
4118 	mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
4119 	mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
4120 }
4121 
4122 /* QPDSM - QoS Priority to DSCP Mapping
4123  * ------------------------------------
4124  * QoS Priority to DSCP Mapping Register
4125  */
4126 #define MLXSW_REG_QPDSM_ID 0x4011
4127 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */
4128 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */
4129 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
4130 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN +			\
4131 			     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN *	\
4132 			     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
4133 
4134 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
4135 
4136 /* reg_qpdsm_local_port
4137  * Local Port. Supported for data packets from CPU port.
4138  * Access: Index
4139  */
4140 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12);
4141 
4142 /* reg_qpdsm_prio_entry_color0_e
4143  * Enable update of the entry for color 0 and a given port.
4144  * Access: WO
4145  */
4146 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
4147 		     MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
4148 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4149 
4150 /* reg_qpdsm_prio_entry_color0_dscp
4151  * DSCP field in the outer label of the packet for color 0 and a given port.
4152  * Reserved when e=0.
4153  * Access: RW
4154  */
4155 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
4156 		     MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
4157 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4158 
4159 /* reg_qpdsm_prio_entry_color1_e
4160  * Enable update of the entry for color 1 and a given port.
4161  * Access: WO
4162  */
4163 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
4164 		     MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
4165 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4166 
4167 /* reg_qpdsm_prio_entry_color1_dscp
4168  * DSCP field in the outer label of the packet for color 1 and a given port.
4169  * Reserved when e=0.
4170  * Access: RW
4171  */
4172 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
4173 		     MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
4174 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4175 
4176 /* reg_qpdsm_prio_entry_color2_e
4177  * Enable update of the entry for color 2 and a given port.
4178  * Access: WO
4179  */
4180 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
4181 		     MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
4182 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4183 
4184 /* reg_qpdsm_prio_entry_color2_dscp
4185  * DSCP field in the outer label of the packet for color 2 and a given port.
4186  * Reserved when e=0.
4187  * Access: RW
4188  */
4189 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
4190 		     MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
4191 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4192 
mlxsw_reg_qpdsm_pack(char * payload,u16 local_port)4193 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port)
4194 {
4195 	MLXSW_REG_ZERO(qpdsm, payload);
4196 	mlxsw_reg_qpdsm_local_port_set(payload, local_port);
4197 }
4198 
4199 static inline void
mlxsw_reg_qpdsm_prio_pack(char * payload,unsigned short prio,u8 dscp)4200 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
4201 {
4202 	mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
4203 	mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
4204 	mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
4205 	mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
4206 	mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
4207 	mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
4208 }
4209 
4210 /* QPDP - QoS Port DSCP to Priority Mapping Register
4211  * -------------------------------------------------
4212  * This register controls the port default Switch Priority and Color. The
4213  * default Switch Priority and Color are used for frames where the trust state
4214  * uses default values. All member ports of a LAG should be configured with the
4215  * same default values.
4216  */
4217 #define MLXSW_REG_QPDP_ID 0x4007
4218 #define MLXSW_REG_QPDP_LEN 0x8
4219 
4220 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN);
4221 
4222 /* reg_qpdp_local_port
4223  * Local Port. Supported for data packets from CPU port.
4224  * Access: Index
4225  */
4226 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12);
4227 
4228 /* reg_qpdp_switch_prio
4229  * Default port Switch Priority (default 0)
4230  * Access: RW
4231  */
4232 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4);
4233 
mlxsw_reg_qpdp_pack(char * payload,u16 local_port,u8 switch_prio)4234 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port,
4235 				       u8 switch_prio)
4236 {
4237 	MLXSW_REG_ZERO(qpdp, payload);
4238 	mlxsw_reg_qpdp_local_port_set(payload, local_port);
4239 	mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio);
4240 }
4241 
4242 /* QPDPM - QoS Port DSCP to Priority Mapping Register
4243  * --------------------------------------------------
4244  * This register controls the mapping from DSCP field to
4245  * Switch Priority for IP packets.
4246  */
4247 #define MLXSW_REG_QPDPM_ID 0x4013
4248 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */
4249 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */
4250 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
4251 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN +			\
4252 			     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN *	\
4253 			     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
4254 
4255 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
4256 
4257 /* reg_qpdpm_local_port
4258  * Local Port. Supported for data packets from CPU port.
4259  * Access: Index
4260  */
4261 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12);
4262 
4263 /* reg_qpdpm_dscp_e
4264  * Enable update of the specific entry. When cleared, the switch_prio and color
4265  * fields are ignored and the previous switch_prio and color values are
4266  * preserved.
4267  * Access: WO
4268  */
4269 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
4270 		     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4271 
4272 /* reg_qpdpm_dscp_prio
4273  * The new Switch Priority value for the relevant DSCP value.
4274  * Access: RW
4275  */
4276 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
4277 		     MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
4278 		     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4279 
mlxsw_reg_qpdpm_pack(char * payload,u16 local_port)4280 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port)
4281 {
4282 	MLXSW_REG_ZERO(qpdpm, payload);
4283 	mlxsw_reg_qpdpm_local_port_set(payload, local_port);
4284 }
4285 
4286 static inline void
mlxsw_reg_qpdpm_dscp_pack(char * payload,unsigned short dscp,u8 prio)4287 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
4288 {
4289 	mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
4290 	mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
4291 }
4292 
4293 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register
4294  * ------------------------------------------------------------------
4295  * This register configures if the Switch Priority to Traffic Class mapping is
4296  * based on Multicast packet indication. If so, then multicast packets will get
4297  * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by
4298  * QTCT.
4299  * By default, Switch Priority to Traffic Class mapping is not based on
4300  * Multicast packet indication.
4301  */
4302 #define MLXSW_REG_QTCTM_ID 0x401A
4303 #define MLXSW_REG_QTCTM_LEN 0x08
4304 
4305 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
4306 
4307 /* reg_qtctm_local_port
4308  * Local port number.
4309  * No support for CPU port.
4310  * Access: Index
4311  */
4312 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12);
4313 
4314 /* reg_qtctm_mc
4315  * Multicast Mode
4316  * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
4317  * indication (default is 0, not based on Multicast packet indication).
4318  */
4319 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
4320 
4321 static inline void
mlxsw_reg_qtctm_pack(char * payload,u16 local_port,bool mc)4322 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc)
4323 {
4324 	MLXSW_REG_ZERO(qtctm, payload);
4325 	mlxsw_reg_qtctm_local_port_set(payload, local_port);
4326 	mlxsw_reg_qtctm_mc_set(payload, mc);
4327 }
4328 
4329 /* QPSC - QoS PTP Shaper Configuration Register
4330  * --------------------------------------------
4331  * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1.
4332  * Supported only on Spectrum-1.
4333  */
4334 #define MLXSW_REG_QPSC_ID 0x401B
4335 #define MLXSW_REG_QPSC_LEN 0x28
4336 
4337 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN);
4338 
4339 enum mlxsw_reg_qpsc_port_speed {
4340 	MLXSW_REG_QPSC_PORT_SPEED_100M,
4341 	MLXSW_REG_QPSC_PORT_SPEED_1G,
4342 	MLXSW_REG_QPSC_PORT_SPEED_10G,
4343 	MLXSW_REG_QPSC_PORT_SPEED_25G,
4344 };
4345 
4346 /* reg_qpsc_port_speed
4347  * Port speed.
4348  * Access: Index
4349  */
4350 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);
4351 
4352 /* reg_qpsc_shaper_time_exp
4353  * The base-time-interval for updating the shapers tokens (for all hierarchies).
4354  * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
4355  * shaper_rate = 64bit * shaper_inc / shaper_update_rate
4356  * Access: RW
4357  */
4358 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);
4359 
4360 /* reg_qpsc_shaper_time_mantissa
4361  * The base-time-interval for updating the shapers tokens (for all hierarchies).
4362  * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
4363  * shaper_rate = 64bit * shaper_inc / shaper_update_rate
4364  * Access: RW
4365  */
4366 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);
4367 
4368 /* reg_qpsc_shaper_inc
4369  * Number of tokens added to shaper on each update.
4370  * Units of 8B.
4371  * Access: RW
4372  */
4373 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
4374 
4375 /* reg_qpsc_shaper_bs
4376  * Max shaper Burst size.
4377  * Burst size is 2 ^ max_shaper_bs * 512 [bits]
4378  * Range is: 5..25 (from 2KB..2GB)
4379  * Access: RW
4380  */
4381 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
4382 
4383 /* reg_qpsc_ptsc_we
4384  * Write enable to port_to_shaper_credits.
4385  * Access: WO
4386  */
4387 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
4388 
4389 /* reg_qpsc_port_to_shaper_credits
4390  * For split ports: range 1..57
4391  * For non-split ports: range 1..112
4392  * Written only when ptsc_we is set.
4393  * Access: RW
4394  */
4395 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
4396 
4397 /* reg_qpsc_ing_timestamp_inc
4398  * Ingress timestamp increment.
4399  * 2's complement.
4400  * The timestamp of MTPPTR at ingress will be incremented by this value. Global
4401  * value for all ports.
4402  * Same units as used by MTPPTR.
4403  * Access: RW
4404  */
4405 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
4406 
4407 /* reg_qpsc_egr_timestamp_inc
4408  * Egress timestamp increment.
4409  * 2's complement.
4410  * The timestamp of MTPPTR at egress will be incremented by this value. Global
4411  * value for all ports.
4412  * Same units as used by MTPPTR.
4413  * Access: RW
4414  */
4415 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
4416 
4417 static inline void
mlxsw_reg_qpsc_pack(char * payload,enum mlxsw_reg_qpsc_port_speed port_speed,u8 shaper_time_exp,u8 shaper_time_mantissa,u8 shaper_inc,u8 shaper_bs,u8 port_to_shaper_credits,int ing_timestamp_inc,int egr_timestamp_inc)4418 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed,
4419 		    u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc,
4420 		    u8 shaper_bs, u8 port_to_shaper_credits,
4421 		    int ing_timestamp_inc, int egr_timestamp_inc)
4422 {
4423 	MLXSW_REG_ZERO(qpsc, payload);
4424 	mlxsw_reg_qpsc_port_speed_set(payload, port_speed);
4425 	mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp);
4426 	mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa);
4427 	mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc);
4428 	mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs);
4429 	mlxsw_reg_qpsc_ptsc_we_set(payload, true);
4430 	mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits);
4431 	mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc);
4432 	mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc);
4433 }
4434 
4435 /* PMLP - Ports Module to Local Port Register
4436  * ------------------------------------------
4437  * Configures the assignment of modules to local ports.
4438  */
4439 #define MLXSW_REG_PMLP_ID 0x5002
4440 #define MLXSW_REG_PMLP_LEN 0x40
4441 
4442 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
4443 
4444 /* reg_pmlp_rxtx
4445  * 0 - Tx value is used for both Tx and Rx.
4446  * 1 - Rx value is taken from a separte field.
4447  * Access: RW
4448  */
4449 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
4450 
4451 /* reg_pmlp_local_port
4452  * Local port number.
4453  * Access: Index
4454  */
4455 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12);
4456 
4457 /* reg_pmlp_width
4458  * 0 - Unmap local port.
4459  * 1 - Lane 0 is used.
4460  * 2 - Lanes 0 and 1 are used.
4461  * 4 - Lanes 0, 1, 2 and 3 are used.
4462  * 8 - Lanes 0-7 are used.
4463  * Access: RW
4464  */
4465 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
4466 
4467 /* reg_pmlp_module
4468  * Module number.
4469  * Access: RW
4470  */
4471 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
4472 
4473 /* reg_pmlp_slot_index
4474  * Module number.
4475  * Slot_index
4476  * Slot_index = 0 represent the onboard (motherboard).
4477  * In case of non-modular system only slot_index = 0 is available.
4478  * Access: RW
4479  */
4480 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false);
4481 
4482 /* reg_pmlp_tx_lane
4483  * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
4484  * Access: RW
4485  */
4486 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false);
4487 
4488 /* reg_pmlp_rx_lane
4489  * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
4490  * equal to Tx lane.
4491  * Access: RW
4492  */
4493 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);
4494 
mlxsw_reg_pmlp_pack(char * payload,u16 local_port)4495 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port)
4496 {
4497 	MLXSW_REG_ZERO(pmlp, payload);
4498 	mlxsw_reg_pmlp_local_port_set(payload, local_port);
4499 }
4500 
4501 /* PMTU - Port MTU Register
4502  * ------------------------
4503  * Configures and reports the port MTU.
4504  */
4505 #define MLXSW_REG_PMTU_ID 0x5003
4506 #define MLXSW_REG_PMTU_LEN 0x10
4507 
4508 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
4509 
4510 /* reg_pmtu_local_port
4511  * Local port number.
4512  * Access: Index
4513  */
4514 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12);
4515 
4516 /* reg_pmtu_max_mtu
4517  * Maximum MTU.
4518  * When port type (e.g. Ethernet) is configured, the relevant MTU is
4519  * reported, otherwise the minimum between the max_mtu of the different
4520  * types is reported.
4521  * Access: RO
4522  */
4523 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
4524 
4525 /* reg_pmtu_admin_mtu
4526  * MTU value to set port to. Must be smaller or equal to max_mtu.
4527  * Note: If port type is Infiniband, then port must be disabled, when its
4528  * MTU is set.
4529  * Access: RW
4530  */
4531 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
4532 
4533 /* reg_pmtu_oper_mtu
4534  * The actual MTU configured on the port. Packets exceeding this size
4535  * will be dropped.
4536  * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
4537  * oper_mtu might be smaller than admin_mtu.
4538  * Access: RO
4539  */
4540 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4541 
mlxsw_reg_pmtu_pack(char * payload,u16 local_port,u16 new_mtu)4542 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port,
4543 				       u16 new_mtu)
4544 {
4545 	MLXSW_REG_ZERO(pmtu, payload);
4546 	mlxsw_reg_pmtu_local_port_set(payload, local_port);
4547 	mlxsw_reg_pmtu_max_mtu_set(payload, 0);
4548 	mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
4549 	mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
4550 }
4551 
4552 /* PTYS - Port Type and Speed Register
4553  * -----------------------------------
4554  * Configures and reports the port speed type.
4555  *
4556  * Note: When set while the link is up, the changes will not take effect
4557  * until the port transitions from down to up state.
4558  */
4559 #define MLXSW_REG_PTYS_ID 0x5004
4560 #define MLXSW_REG_PTYS_LEN 0x40
4561 
4562 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
4563 
4564 /* an_disable_admin
4565  * Auto negotiation disable administrative configuration
4566  * 0 - Device doesn't support AN disable.
4567  * 1 - Device supports AN disable.
4568  * Access: RW
4569  */
4570 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
4571 
4572 /* reg_ptys_local_port
4573  * Local port number.
4574  * Access: Index
4575  */
4576 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12);
4577 
4578 #define MLXSW_REG_PTYS_PROTO_MASK_IB	BIT(0)
4579 #define MLXSW_REG_PTYS_PROTO_MASK_ETH	BIT(2)
4580 
4581 /* reg_ptys_proto_mask
4582  * Protocol mask. Indicates which protocol is used.
4583  * 0 - Infiniband.
4584  * 1 - Fibre Channel.
4585  * 2 - Ethernet.
4586  * Access: Index
4587  */
4588 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
4589 
4590 enum {
4591 	MLXSW_REG_PTYS_AN_STATUS_NA,
4592 	MLXSW_REG_PTYS_AN_STATUS_OK,
4593 	MLXSW_REG_PTYS_AN_STATUS_FAIL,
4594 };
4595 
4596 /* reg_ptys_an_status
4597  * Autonegotiation status.
4598  * Access: RO
4599  */
4600 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
4601 
4602 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M				BIT(0)
4603 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII			BIT(1)
4604 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R				BIT(3)
4605 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G			BIT(4)
4606 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G		BIT(5)
4607 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR		BIT(6)
4608 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2	BIT(7)
4609 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR	BIT(8)
4610 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4		BIT(9)
4611 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2		BIT(10)
4612 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4		BIT(12)
4613 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8				BIT(15)
4614 
4615 /* reg_ptys_ext_eth_proto_cap
4616  * Extended Ethernet port supported speeds and protocols.
4617  * Access: RO
4618  */
4619 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
4620 
4621 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII			BIT(0)
4622 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX		BIT(1)
4623 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4		BIT(2)
4624 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4		BIT(3)
4625 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR		BIT(4)
4626 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4		BIT(6)
4627 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4		BIT(7)
4628 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR		BIT(12)
4629 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR		BIT(13)
4630 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR		BIT(14)
4631 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4		BIT(15)
4632 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4	BIT(16)
4633 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2		BIT(18)
4634 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4		BIT(19)
4635 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4		BIT(20)
4636 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4		BIT(21)
4637 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4		BIT(22)
4638 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4	BIT(23)
4639 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T		BIT(24)
4640 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T		BIT(25)
4641 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR		BIT(27)
4642 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR		BIT(28)
4643 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR		BIT(29)
4644 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2		BIT(30)
4645 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2		BIT(31)
4646 
4647 /* reg_ptys_eth_proto_cap
4648  * Ethernet port supported speeds and protocols.
4649  * Access: RO
4650  */
4651 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4652 
4653 /* reg_ptys_ext_eth_proto_admin
4654  * Extended speed and protocol to set port to.
4655  * Access: RW
4656  */
4657 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4658 
4659 /* reg_ptys_eth_proto_admin
4660  * Speed and protocol to set port to.
4661  * Access: RW
4662  */
4663 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4664 
4665 /* reg_ptys_ext_eth_proto_oper
4666  * The extended current speed and protocol configured for the port.
4667  * Access: RO
4668  */
4669 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4670 
4671 /* reg_ptys_eth_proto_oper
4672  * The current speed and protocol configured for the port.
4673  * Access: RO
4674  */
4675 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4676 
4677 enum mlxsw_reg_ptys_connector_type {
4678 	MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4679 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4680 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4681 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4682 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4683 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4684 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4685 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4686 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4687 };
4688 
4689 /* reg_ptys_connector_type
4690  * Connector type indication.
4691  * Access: RO
4692  */
4693 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4694 
mlxsw_reg_ptys_eth_pack(char * payload,u16 local_port,u32 proto_admin,bool autoneg)4695 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port,
4696 					   u32 proto_admin, bool autoneg)
4697 {
4698 	MLXSW_REG_ZERO(ptys, payload);
4699 	mlxsw_reg_ptys_local_port_set(payload, local_port);
4700 	mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4701 	mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4702 	mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4703 }
4704 
mlxsw_reg_ptys_ext_eth_pack(char * payload,u16 local_port,u32 proto_admin,bool autoneg)4705 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port,
4706 					       u32 proto_admin, bool autoneg)
4707 {
4708 	MLXSW_REG_ZERO(ptys, payload);
4709 	mlxsw_reg_ptys_local_port_set(payload, local_port);
4710 	mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4711 	mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4712 	mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4713 }
4714 
mlxsw_reg_ptys_eth_unpack(char * payload,u32 * p_eth_proto_cap,u32 * p_eth_proto_admin,u32 * p_eth_proto_oper)4715 static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
4716 					     u32 *p_eth_proto_cap,
4717 					     u32 *p_eth_proto_admin,
4718 					     u32 *p_eth_proto_oper)
4719 {
4720 	if (p_eth_proto_cap)
4721 		*p_eth_proto_cap =
4722 			mlxsw_reg_ptys_eth_proto_cap_get(payload);
4723 	if (p_eth_proto_admin)
4724 		*p_eth_proto_admin =
4725 			mlxsw_reg_ptys_eth_proto_admin_get(payload);
4726 	if (p_eth_proto_oper)
4727 		*p_eth_proto_oper =
4728 			mlxsw_reg_ptys_eth_proto_oper_get(payload);
4729 }
4730 
mlxsw_reg_ptys_ext_eth_unpack(char * payload,u32 * p_eth_proto_cap,u32 * p_eth_proto_admin,u32 * p_eth_proto_oper)4731 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4732 						 u32 *p_eth_proto_cap,
4733 						 u32 *p_eth_proto_admin,
4734 						 u32 *p_eth_proto_oper)
4735 {
4736 	if (p_eth_proto_cap)
4737 		*p_eth_proto_cap =
4738 			mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4739 	if (p_eth_proto_admin)
4740 		*p_eth_proto_admin =
4741 			mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4742 	if (p_eth_proto_oper)
4743 		*p_eth_proto_oper =
4744 			mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4745 }
4746 
4747 /* PPAD - Port Physical Address Register
4748  * -------------------------------------
4749  * The PPAD register configures the per port physical MAC address.
4750  */
4751 #define MLXSW_REG_PPAD_ID 0x5005
4752 #define MLXSW_REG_PPAD_LEN 0x10
4753 
4754 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
4755 
4756 /* reg_ppad_single_base_mac
4757  * 0: base_mac, local port should be 0 and mac[7:0] is
4758  * reserved. HW will set incremental
4759  * 1: single_mac - mac of the local_port
4760  * Access: RW
4761  */
4762 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4763 
4764 /* reg_ppad_local_port
4765  * port number, if single_base_mac = 0 then local_port is reserved
4766  * Access: RW
4767  */
4768 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24);
4769 
4770 /* reg_ppad_mac
4771  * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
4772  * If single_base_mac = 1 - the per port MAC address
4773  * Access: RW
4774  */
4775 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4776 
mlxsw_reg_ppad_pack(char * payload,bool single_base_mac,u16 local_port)4777 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4778 				       u16 local_port)
4779 {
4780 	MLXSW_REG_ZERO(ppad, payload);
4781 	mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4782 	mlxsw_reg_ppad_local_port_set(payload, local_port);
4783 }
4784 
4785 /* PAOS - Ports Administrative and Operational Status Register
4786  * -----------------------------------------------------------
4787  * Configures and retrieves per port administrative and operational status.
4788  */
4789 #define MLXSW_REG_PAOS_ID 0x5006
4790 #define MLXSW_REG_PAOS_LEN 0x10
4791 
4792 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
4793 
4794 /* reg_paos_swid
4795  * Switch partition ID with which to associate the port.
4796  * Note: while external ports uses unique local port numbers (and thus swid is
4797  * redundant), router ports use the same local port number where swid is the
4798  * only indication for the relevant port.
4799  * Access: Index
4800  */
4801 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4802 
4803 /* reg_paos_local_port
4804  * Local port number.
4805  * Access: Index
4806  */
4807 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12);
4808 
4809 /* reg_paos_admin_status
4810  * Port administrative state (the desired state of the port):
4811  * 1 - Up.
4812  * 2 - Down.
4813  * 3 - Up once. This means that in case of link failure, the port won't go
4814  *     into polling mode, but will wait to be re-enabled by software.
4815  * 4 - Disabled by system. Can only be set by hardware.
4816  * Access: RW
4817  */
4818 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4819 
4820 /* reg_paos_oper_status
4821  * Port operational state (the current state):
4822  * 1 - Up.
4823  * 2 - Down.
4824  * 3 - Down by port failure. This means that the device will not let the
4825  *     port up again until explicitly specified by software.
4826  * Access: RO
4827  */
4828 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4829 
4830 /* reg_paos_ase
4831  * Admin state update enabled.
4832  * Access: WO
4833  */
4834 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4835 
4836 /* reg_paos_ee
4837  * Event update enable. If this bit is set, event generation will be
4838  * updated based on the e field.
4839  * Access: WO
4840  */
4841 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4842 
4843 /* reg_paos_e
4844  * Event generation on operational state change:
4845  * 0 - Do not generate event.
4846  * 1 - Generate Event.
4847  * 2 - Generate Single Event.
4848  * Access: RW
4849  */
4850 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4851 
mlxsw_reg_paos_pack(char * payload,u16 local_port,enum mlxsw_port_admin_status status)4852 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port,
4853 				       enum mlxsw_port_admin_status status)
4854 {
4855 	MLXSW_REG_ZERO(paos, payload);
4856 	mlxsw_reg_paos_swid_set(payload, 0);
4857 	mlxsw_reg_paos_local_port_set(payload, local_port);
4858 	mlxsw_reg_paos_admin_status_set(payload, status);
4859 	mlxsw_reg_paos_oper_status_set(payload, 0);
4860 	mlxsw_reg_paos_ase_set(payload, 1);
4861 	mlxsw_reg_paos_ee_set(payload, 1);
4862 	mlxsw_reg_paos_e_set(payload, 1);
4863 }
4864 
4865 /* PFCC - Ports Flow Control Configuration Register
4866  * ------------------------------------------------
4867  * Configures and retrieves the per port flow control configuration.
4868  */
4869 #define MLXSW_REG_PFCC_ID 0x5007
4870 #define MLXSW_REG_PFCC_LEN 0x20
4871 
4872 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4873 
4874 /* reg_pfcc_local_port
4875  * Local port number.
4876  * Access: Index
4877  */
4878 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12);
4879 
4880 /* reg_pfcc_pnat
4881  * Port number access type. Determines the way local_port is interpreted:
4882  * 0 - Local port number.
4883  * 1 - IB / label port number.
4884  * Access: Index
4885  */
4886 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4887 
4888 /* reg_pfcc_shl_cap
4889  * Send to higher layers capabilities:
4890  * 0 - No capability of sending Pause and PFC frames to higher layers.
4891  * 1 - Device has capability of sending Pause and PFC frames to higher
4892  *     layers.
4893  * Access: RO
4894  */
4895 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4896 
4897 /* reg_pfcc_shl_opr
4898  * Send to higher layers operation:
4899  * 0 - Pause and PFC frames are handled by the port (default).
4900  * 1 - Pause and PFC frames are handled by the port and also sent to
4901  *     higher layers. Only valid if shl_cap = 1.
4902  * Access: RW
4903  */
4904 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4905 
4906 /* reg_pfcc_ppan
4907  * Pause policy auto negotiation.
4908  * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
4909  * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
4910  *     based on the auto-negotiation resolution.
4911  * Access: RW
4912  *
4913  * Note: The auto-negotiation advertisement is set according to pptx and
4914  * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
4915  */
4916 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4917 
4918 /* reg_pfcc_prio_mask_tx
4919  * Bit per priority indicating if Tx flow control policy should be
4920  * updated based on bit pfctx.
4921  * Access: WO
4922  */
4923 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4924 
4925 /* reg_pfcc_prio_mask_rx
4926  * Bit per priority indicating if Rx flow control policy should be
4927  * updated based on bit pfcrx.
4928  * Access: WO
4929  */
4930 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4931 
4932 /* reg_pfcc_pptx
4933  * Admin Pause policy on Tx.
4934  * 0 - Never generate Pause frames (default).
4935  * 1 - Generate Pause frames according to Rx buffer threshold.
4936  * Access: RW
4937  */
4938 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4939 
4940 /* reg_pfcc_aptx
4941  * Active (operational) Pause policy on Tx.
4942  * 0 - Never generate Pause frames.
4943  * 1 - Generate Pause frames according to Rx buffer threshold.
4944  * Access: RO
4945  */
4946 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4947 
4948 /* reg_pfcc_pfctx
4949  * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
4950  * 0 - Never generate priority Pause frames on the specified priority
4951  *     (default).
4952  * 1 - Generate priority Pause frames according to Rx buffer threshold on
4953  *     the specified priority.
4954  * Access: RW
4955  *
4956  * Note: pfctx and pptx must be mutually exclusive.
4957  */
4958 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4959 
4960 /* reg_pfcc_pprx
4961  * Admin Pause policy on Rx.
4962  * 0 - Ignore received Pause frames (default).
4963  * 1 - Respect received Pause frames.
4964  * Access: RW
4965  */
4966 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4967 
4968 /* reg_pfcc_aprx
4969  * Active (operational) Pause policy on Rx.
4970  * 0 - Ignore received Pause frames.
4971  * 1 - Respect received Pause frames.
4972  * Access: RO
4973  */
4974 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4975 
4976 /* reg_pfcc_pfcrx
4977  * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
4978  * 0 - Ignore incoming priority Pause frames on the specified priority
4979  *     (default).
4980  * 1 - Respect incoming priority Pause frames on the specified priority.
4981  * Access: RW
4982  */
4983 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4984 
4985 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4986 
mlxsw_reg_pfcc_prio_pack(char * payload,u8 pfc_en)4987 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4988 {
4989 	mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4990 	mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4991 	mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4992 	mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4993 }
4994 
mlxsw_reg_pfcc_pack(char * payload,u16 local_port)4995 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port)
4996 {
4997 	MLXSW_REG_ZERO(pfcc, payload);
4998 	mlxsw_reg_pfcc_local_port_set(payload, local_port);
4999 }
5000 
5001 /* PPCNT - Ports Performance Counters Register
5002  * -------------------------------------------
5003  * The PPCNT register retrieves per port performance counters.
5004  */
5005 #define MLXSW_REG_PPCNT_ID 0x5008
5006 #define MLXSW_REG_PPCNT_LEN 0x100
5007 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
5008 
5009 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
5010 
5011 /* reg_ppcnt_swid
5012  * For HCA: must be always 0.
5013  * Switch partition ID to associate port with.
5014  * Switch partitions are numbered from 0 to 7 inclusively.
5015  * Switch partition 254 indicates stacking ports.
5016  * Switch partition 255 indicates all switch partitions.
5017  * Only valid on Set() operation with local_port=255.
5018  * Access: Index
5019  */
5020 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
5021 
5022 /* reg_ppcnt_local_port
5023  * Local port number.
5024  * Access: Index
5025  */
5026 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12);
5027 
5028 /* reg_ppcnt_pnat
5029  * Port number access type:
5030  * 0 - Local port number
5031  * 1 - IB port number
5032  * Access: Index
5033  */
5034 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
5035 
5036 enum mlxsw_reg_ppcnt_grp {
5037 	MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
5038 	MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
5039 	MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
5040 	MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
5041 	MLXSW_REG_PPCNT_EXT_CNT = 0x5,
5042 	MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
5043 	MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
5044 	MLXSW_REG_PPCNT_TC_CNT = 0x11,
5045 	MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13,
5046 };
5047 
5048 /* reg_ppcnt_grp
5049  * Performance counter group.
5050  * Group 63 indicates all groups. Only valid on Set() operation with
5051  * clr bit set.
5052  * 0x0: IEEE 802.3 Counters
5053  * 0x1: RFC 2863 Counters
5054  * 0x2: RFC 2819 Counters
5055  * 0x3: RFC 3635 Counters
5056  * 0x5: Ethernet Extended Counters
5057  * 0x6: Ethernet Discard Counters
5058  * 0x8: Link Level Retransmission Counters
5059  * 0x10: Per Priority Counters
5060  * 0x11: Per Traffic Class Counters
5061  * 0x12: Physical Layer Counters
5062  * 0x13: Per Traffic Class Congestion Counters
5063  * Access: Index
5064  */
5065 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
5066 
5067 /* reg_ppcnt_clr
5068  * Clear counters. Setting the clr bit will reset the counter value
5069  * for all counters in the counter group. This bit can be set
5070  * for both Set() and Get() operation.
5071  * Access: OP
5072  */
5073 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
5074 
5075 /* reg_ppcnt_lp_gl
5076  * Local port global variable.
5077  * 0: local_port 255 = all ports of the device.
5078  * 1: local_port indicates local port number for all ports.
5079  * Access: OP
5080  */
5081 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1);
5082 
5083 /* reg_ppcnt_prio_tc
5084  * Priority for counter set that support per priority, valid values: 0-7.
5085  * Traffic class for counter set that support per traffic class,
5086  * valid values: 0- cap_max_tclass-1 .
5087  * For HCA: cap_max_tclass is always 8.
5088  * Otherwise must be 0.
5089  * Access: Index
5090  */
5091 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
5092 
5093 /* Ethernet IEEE 802.3 Counter Group */
5094 
5095 /* reg_ppcnt_a_frames_transmitted_ok
5096  * Access: RO
5097  */
5098 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
5099 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5100 
5101 /* reg_ppcnt_a_frames_received_ok
5102  * Access: RO
5103  */
5104 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
5105 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5106 
5107 /* reg_ppcnt_a_frame_check_sequence_errors
5108  * Access: RO
5109  */
5110 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
5111 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5112 
5113 /* reg_ppcnt_a_alignment_errors
5114  * Access: RO
5115  */
5116 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
5117 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
5118 
5119 /* reg_ppcnt_a_octets_transmitted_ok
5120  * Access: RO
5121  */
5122 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
5123 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5124 
5125 /* reg_ppcnt_a_octets_received_ok
5126  * Access: RO
5127  */
5128 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
5129 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5130 
5131 /* reg_ppcnt_a_multicast_frames_xmitted_ok
5132  * Access: RO
5133  */
5134 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
5135 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5136 
5137 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
5138  * Access: RO
5139  */
5140 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
5141 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5142 
5143 /* reg_ppcnt_a_multicast_frames_received_ok
5144  * Access: RO
5145  */
5146 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
5147 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5148 
5149 /* reg_ppcnt_a_broadcast_frames_received_ok
5150  * Access: RO
5151  */
5152 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
5153 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5154 
5155 /* reg_ppcnt_a_in_range_length_errors
5156  * Access: RO
5157  */
5158 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
5159 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5160 
5161 /* reg_ppcnt_a_out_of_range_length_field
5162  * Access: RO
5163  */
5164 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
5165 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5166 
5167 /* reg_ppcnt_a_frame_too_long_errors
5168  * Access: RO
5169  */
5170 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
5171 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5172 
5173 /* reg_ppcnt_a_symbol_error_during_carrier
5174  * Access: RO
5175  */
5176 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
5177 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5178 
5179 /* reg_ppcnt_a_mac_control_frames_transmitted
5180  * Access: RO
5181  */
5182 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
5183 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5184 
5185 /* reg_ppcnt_a_mac_control_frames_received
5186  * Access: RO
5187  */
5188 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
5189 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
5190 
5191 /* reg_ppcnt_a_unsupported_opcodes_received
5192  * Access: RO
5193  */
5194 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
5195 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
5196 
5197 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
5198  * Access: RO
5199  */
5200 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
5201 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
5202 
5203 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
5204  * Access: RO
5205  */
5206 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
5207 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
5208 
5209 /* Ethernet RFC 2863 Counter Group */
5210 
5211 /* reg_ppcnt_if_in_discards
5212  * Access: RO
5213  */
5214 MLXSW_ITEM64(reg, ppcnt, if_in_discards,
5215 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5216 
5217 /* reg_ppcnt_if_out_discards
5218  * Access: RO
5219  */
5220 MLXSW_ITEM64(reg, ppcnt, if_out_discards,
5221 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5222 
5223 /* reg_ppcnt_if_out_errors
5224  * Access: RO
5225  */
5226 MLXSW_ITEM64(reg, ppcnt, if_out_errors,
5227 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5228 
5229 /* Ethernet RFC 2819 Counter Group */
5230 
5231 /* reg_ppcnt_ether_stats_undersize_pkts
5232  * Access: RO
5233  */
5234 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
5235 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5236 
5237 /* reg_ppcnt_ether_stats_oversize_pkts
5238  * Access: RO
5239  */
5240 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
5241 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5242 
5243 /* reg_ppcnt_ether_stats_fragments
5244  * Access: RO
5245  */
5246 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
5247 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5248 
5249 /* reg_ppcnt_ether_stats_pkts64octets
5250  * Access: RO
5251  */
5252 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
5253 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5254 
5255 /* reg_ppcnt_ether_stats_pkts65to127octets
5256  * Access: RO
5257  */
5258 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
5259 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5260 
5261 /* reg_ppcnt_ether_stats_pkts128to255octets
5262  * Access: RO
5263  */
5264 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
5265 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5266 
5267 /* reg_ppcnt_ether_stats_pkts256to511octets
5268  * Access: RO
5269  */
5270 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
5271 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5272 
5273 /* reg_ppcnt_ether_stats_pkts512to1023octets
5274  * Access: RO
5275  */
5276 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
5277 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
5278 
5279 /* reg_ppcnt_ether_stats_pkts1024to1518octets
5280  * Access: RO
5281  */
5282 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
5283 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
5284 
5285 /* reg_ppcnt_ether_stats_pkts1519to2047octets
5286  * Access: RO
5287  */
5288 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
5289 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
5290 
5291 /* reg_ppcnt_ether_stats_pkts2048to4095octets
5292  * Access: RO
5293  */
5294 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
5295 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
5296 
5297 /* reg_ppcnt_ether_stats_pkts4096to8191octets
5298  * Access: RO
5299  */
5300 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
5301 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
5302 
5303 /* reg_ppcnt_ether_stats_pkts8192to10239octets
5304  * Access: RO
5305  */
5306 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
5307 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
5308 
5309 /* Ethernet RFC 3635 Counter Group */
5310 
5311 /* reg_ppcnt_dot3stats_fcs_errors
5312  * Access: RO
5313  */
5314 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
5315 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5316 
5317 /* reg_ppcnt_dot3stats_symbol_errors
5318  * Access: RO
5319  */
5320 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
5321 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5322 
5323 /* reg_ppcnt_dot3control_in_unknown_opcodes
5324  * Access: RO
5325  */
5326 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
5327 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5328 
5329 /* reg_ppcnt_dot3in_pause_frames
5330  * Access: RO
5331  */
5332 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
5333 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5334 
5335 /* Ethernet Extended Counter Group Counters */
5336 
5337 /* reg_ppcnt_ecn_marked
5338  * Access: RO
5339  */
5340 MLXSW_ITEM64(reg, ppcnt, ecn_marked,
5341 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5342 
5343 /* Ethernet Discard Counter Group Counters */
5344 
5345 /* reg_ppcnt_ingress_general
5346  * Access: RO
5347  */
5348 MLXSW_ITEM64(reg, ppcnt, ingress_general,
5349 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5350 
5351 /* reg_ppcnt_ingress_policy_engine
5352  * Access: RO
5353  */
5354 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
5355 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5356 
5357 /* reg_ppcnt_ingress_vlan_membership
5358  * Access: RO
5359  */
5360 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
5361 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5362 
5363 /* reg_ppcnt_ingress_tag_frame_type
5364  * Access: RO
5365  */
5366 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
5367 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
5368 
5369 /* reg_ppcnt_egress_vlan_membership
5370  * Access: RO
5371  */
5372 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
5373 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5374 
5375 /* reg_ppcnt_loopback_filter
5376  * Access: RO
5377  */
5378 MLXSW_ITEM64(reg, ppcnt, loopback_filter,
5379 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5380 
5381 /* reg_ppcnt_egress_general
5382  * Access: RO
5383  */
5384 MLXSW_ITEM64(reg, ppcnt, egress_general,
5385 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5386 
5387 /* reg_ppcnt_egress_hoq
5388  * Access: RO
5389  */
5390 MLXSW_ITEM64(reg, ppcnt, egress_hoq,
5391 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5392 
5393 /* reg_ppcnt_egress_policy_engine
5394  * Access: RO
5395  */
5396 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
5397 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5398 
5399 /* reg_ppcnt_ingress_tx_link_down
5400  * Access: RO
5401  */
5402 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
5403 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5404 
5405 /* reg_ppcnt_egress_stp_filter
5406  * Access: RO
5407  */
5408 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
5409 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5410 
5411 /* reg_ppcnt_egress_sll
5412  * Access: RO
5413  */
5414 MLXSW_ITEM64(reg, ppcnt, egress_sll,
5415 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5416 
5417 /* Ethernet Per Priority Group Counters */
5418 
5419 /* reg_ppcnt_rx_octets
5420  * Access: RO
5421  */
5422 MLXSW_ITEM64(reg, ppcnt, rx_octets,
5423 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5424 
5425 /* reg_ppcnt_rx_frames
5426  * Access: RO
5427  */
5428 MLXSW_ITEM64(reg, ppcnt, rx_frames,
5429 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5430 
5431 /* reg_ppcnt_tx_octets
5432  * Access: RO
5433  */
5434 MLXSW_ITEM64(reg, ppcnt, tx_octets,
5435 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5436 
5437 /* reg_ppcnt_tx_frames
5438  * Access: RO
5439  */
5440 MLXSW_ITEM64(reg, ppcnt, tx_frames,
5441 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5442 
5443 /* reg_ppcnt_rx_pause
5444  * Access: RO
5445  */
5446 MLXSW_ITEM64(reg, ppcnt, rx_pause,
5447 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5448 
5449 /* reg_ppcnt_rx_pause_duration
5450  * Access: RO
5451  */
5452 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
5453 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5454 
5455 /* reg_ppcnt_tx_pause
5456  * Access: RO
5457  */
5458 MLXSW_ITEM64(reg, ppcnt, tx_pause,
5459 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5460 
5461 /* reg_ppcnt_tx_pause_duration
5462  * Access: RO
5463  */
5464 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
5465 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5466 
5467 /* reg_ppcnt_rx_pause_transition
5468  * Access: RO
5469  */
5470 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
5471 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5472 
5473 /* Ethernet Per Traffic Class Counters */
5474 
5475 /* reg_ppcnt_tc_transmit_queue
5476  * Contains the transmit queue depth in cells of traffic class
5477  * selected by prio_tc and the port selected by local_port.
5478  * The field cannot be cleared.
5479  * Access: RO
5480  */
5481 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
5482 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5483 
5484 /* reg_ppcnt_tc_no_buffer_discard_uc
5485  * The number of unicast packets dropped due to lack of shared
5486  * buffer resources.
5487  * Access: RO
5488  */
5489 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
5490 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5491 
5492 /* Ethernet Per Traffic Class Congestion Group Counters */
5493 
5494 /* reg_ppcnt_wred_discard
5495  * Access: RO
5496  */
5497 MLXSW_ITEM64(reg, ppcnt, wred_discard,
5498 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5499 
5500 /* reg_ppcnt_ecn_marked_tc
5501  * Access: RO
5502  */
5503 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc,
5504 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5505 
mlxsw_reg_ppcnt_pack(char * payload,u16 local_port,enum mlxsw_reg_ppcnt_grp grp,u8 prio_tc)5506 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port,
5507 					enum mlxsw_reg_ppcnt_grp grp,
5508 					u8 prio_tc)
5509 {
5510 	MLXSW_REG_ZERO(ppcnt, payload);
5511 	mlxsw_reg_ppcnt_swid_set(payload, 0);
5512 	mlxsw_reg_ppcnt_local_port_set(payload, local_port);
5513 	mlxsw_reg_ppcnt_pnat_set(payload, 0);
5514 	mlxsw_reg_ppcnt_grp_set(payload, grp);
5515 	mlxsw_reg_ppcnt_clr_set(payload, 0);
5516 	mlxsw_reg_ppcnt_lp_gl_set(payload, 1);
5517 	mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
5518 }
5519 
5520 /* PPTB - Port Prio To Buffer Register
5521  * -----------------------------------
5522  * Configures the switch priority to buffer table.
5523  */
5524 #define MLXSW_REG_PPTB_ID 0x500B
5525 #define MLXSW_REG_PPTB_LEN 0x10
5526 
5527 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
5528 
5529 enum {
5530 	MLXSW_REG_PPTB_MM_UM,
5531 	MLXSW_REG_PPTB_MM_UNICAST,
5532 	MLXSW_REG_PPTB_MM_MULTICAST,
5533 };
5534 
5535 /* reg_pptb_mm
5536  * Mapping mode.
5537  * 0 - Map both unicast and multicast packets to the same buffer.
5538  * 1 - Map only unicast packets.
5539  * 2 - Map only multicast packets.
5540  * Access: Index
5541  *
5542  * Note: SwitchX-2 only supports the first option.
5543  */
5544 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
5545 
5546 /* reg_pptb_local_port
5547  * Local port number.
5548  * Access: Index
5549  */
5550 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12);
5551 
5552 /* reg_pptb_um
5553  * Enables the update of the untagged_buf field.
5554  * Access: RW
5555  */
5556 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
5557 
5558 /* reg_pptb_pm
5559  * Enables the update of the prio_to_buff field.
5560  * Bit <i> is a flag for updating the mapping for switch priority <i>.
5561  * Access: RW
5562  */
5563 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
5564 
5565 /* reg_pptb_prio_to_buff
5566  * Mapping of switch priority <i> to one of the allocated receive port
5567  * buffers.
5568  * Access: RW
5569  */
5570 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
5571 
5572 /* reg_pptb_pm_msb
5573  * Enables the update of the prio_to_buff field.
5574  * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
5575  * Access: RW
5576  */
5577 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
5578 
5579 /* reg_pptb_untagged_buff
5580  * Mapping of untagged frames to one of the allocated receive port buffers.
5581  * Access: RW
5582  *
5583  * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
5584  * Spectrum, as it maps untagged packets based on the default switch priority.
5585  */
5586 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
5587 
5588 /* reg_pptb_prio_to_buff_msb
5589  * Mapping of switch priority <i+8> to one of the allocated receive port
5590  * buffers.
5591  * Access: RW
5592  */
5593 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5594 
5595 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5596 
mlxsw_reg_pptb_pack(char * payload,u16 local_port)5597 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port)
5598 {
5599 	MLXSW_REG_ZERO(pptb, payload);
5600 	mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5601 	mlxsw_reg_pptb_local_port_set(payload, local_port);
5602 	mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5603 	mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5604 }
5605 
mlxsw_reg_pptb_prio_to_buff_pack(char * payload,u8 prio,u8 buff)5606 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
5607 						    u8 buff)
5608 {
5609 	mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
5610 	mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
5611 }
5612 
5613 /* PBMC - Port Buffer Management Control Register
5614  * ----------------------------------------------
5615  * The PBMC register configures and retrieves the port packet buffer
5616  * allocation for different Prios, and the Pause threshold management.
5617  */
5618 #define MLXSW_REG_PBMC_ID 0x500C
5619 #define MLXSW_REG_PBMC_LEN 0x6C
5620 
5621 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
5622 
5623 /* reg_pbmc_local_port
5624  * Local port number.
5625  * Access: Index
5626  */
5627 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12);
5628 
5629 /* reg_pbmc_xoff_timer_value
5630  * When device generates a pause frame, it uses this value as the pause
5631  * timer (time for the peer port to pause in quota-512 bit time).
5632  * Access: RW
5633  */
5634 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
5635 
5636 /* reg_pbmc_xoff_refresh
5637  * The time before a new pause frame should be sent to refresh the pause RW
5638  * state. Using the same units as xoff_timer_value above (in quota-512 bit
5639  * time).
5640  * Access: RW
5641  */
5642 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
5643 
5644 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
5645 
5646 /* reg_pbmc_buf_lossy
5647  * The field indicates if the buffer is lossy.
5648  * 0 - Lossless
5649  * 1 - Lossy
5650  * Access: RW
5651  */
5652 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
5653 
5654 /* reg_pbmc_buf_epsb
5655  * Eligible for Port Shared buffer.
5656  * If epsb is set, packets assigned to buffer are allowed to insert the port
5657  * shared buffer.
5658  * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
5659  * Access: RW
5660  */
5661 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
5662 
5663 /* reg_pbmc_buf_size
5664  * The part of the packet buffer array is allocated for the specific buffer.
5665  * Units are represented in cells.
5666  * Access: RW
5667  */
5668 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
5669 
5670 /* reg_pbmc_buf_xoff_threshold
5671  * Once the amount of data in the buffer goes above this value, device
5672  * starts sending PFC frames for all priorities associated with the
5673  * buffer. Units are represented in cells. Reserved in case of lossy
5674  * buffer.
5675  * Access: RW
5676  *
5677  * Note: In Spectrum, reserved for buffer[9].
5678  */
5679 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
5680 		     0x08, 0x04, false);
5681 
5682 /* reg_pbmc_buf_xon_threshold
5683  * When the amount of data in the buffer goes below this value, device
5684  * stops sending PFC frames for the priorities associated with the
5685  * buffer. Units are represented in cells. Reserved in case of lossy
5686  * buffer.
5687  * Access: RW
5688  *
5689  * Note: In Spectrum, reserved for buffer[9].
5690  */
5691 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5692 		     0x08, 0x04, false);
5693 
mlxsw_reg_pbmc_pack(char * payload,u16 local_port,u16 xoff_timer_value,u16 xoff_refresh)5694 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port,
5695 				       u16 xoff_timer_value, u16 xoff_refresh)
5696 {
5697 	MLXSW_REG_ZERO(pbmc, payload);
5698 	mlxsw_reg_pbmc_local_port_set(payload, local_port);
5699 	mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5700 	mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5701 }
5702 
mlxsw_reg_pbmc_lossy_buffer_pack(char * payload,int buf_index,u16 size)5703 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
5704 						    int buf_index,
5705 						    u16 size)
5706 {
5707 	mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
5708 	mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5709 	mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5710 }
5711 
mlxsw_reg_pbmc_lossless_buffer_pack(char * payload,int buf_index,u16 size,u16 threshold)5712 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
5713 						       int buf_index, u16 size,
5714 						       u16 threshold)
5715 {
5716 	mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
5717 	mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5718 	mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5719 	mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
5720 	mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
5721 }
5722 
5723 /* PSPA - Port Switch Partition Allocation
5724  * ---------------------------------------
5725  * Controls the association of a port with a switch partition and enables
5726  * configuring ports as stacking ports.
5727  */
5728 #define MLXSW_REG_PSPA_ID 0x500D
5729 #define MLXSW_REG_PSPA_LEN 0x8
5730 
5731 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
5732 
5733 /* reg_pspa_swid
5734  * Switch partition ID.
5735  * Access: RW
5736  */
5737 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
5738 
5739 /* reg_pspa_local_port
5740  * Local port number.
5741  * Access: Index
5742  */
5743 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0);
5744 
5745 /* reg_pspa_sub_port
5746  * Virtual port within the local port. Set to 0 when virtual ports are
5747  * disabled on the local port.
5748  * Access: Index
5749  */
5750 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5751 
mlxsw_reg_pspa_pack(char * payload,u8 swid,u16 local_port)5752 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port)
5753 {
5754 	MLXSW_REG_ZERO(pspa, payload);
5755 	mlxsw_reg_pspa_swid_set(payload, swid);
5756 	mlxsw_reg_pspa_local_port_set(payload, local_port);
5757 	mlxsw_reg_pspa_sub_port_set(payload, 0);
5758 }
5759 
5760 /* PMAOS - Ports Module Administrative and Operational Status
5761  * ----------------------------------------------------------
5762  * This register configures and retrieves the per module status.
5763  */
5764 #define MLXSW_REG_PMAOS_ID 0x5012
5765 #define MLXSW_REG_PMAOS_LEN 0x10
5766 
5767 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN);
5768 
5769 /* reg_pmaos_rst
5770  * Module reset toggle.
5771  * Note: Setting reset while module is plugged-in will result in transition to
5772  * "initializing" operational state.
5773  * Access: OP
5774  */
5775 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1);
5776 
5777 /* reg_pmaos_slot_index
5778  * Slot index.
5779  * Access: Index
5780  */
5781 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4);
5782 
5783 /* reg_pmaos_module
5784  * Module number.
5785  * Access: Index
5786  */
5787 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8);
5788 
5789 enum mlxsw_reg_pmaos_admin_status {
5790 	MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1,
5791 	MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2,
5792 	/* If the module is active and then unplugged, or experienced an error
5793 	 * event, the operational status should go to "disabled" and can only
5794 	 * be enabled upon explicit enable command.
5795 	 */
5796 	MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3,
5797 };
5798 
5799 /* reg_pmaos_admin_status
5800  * Module administrative state (the desired state of the module).
5801  * Note: To disable a module, all ports associated with the port must be
5802  * administatively down first.
5803  * Access: RW
5804  */
5805 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4);
5806 
5807 /* reg_pmaos_ase
5808  * Admin state update enable.
5809  * If this bit is set, admin state will be updated based on admin_state field.
5810  * Only relevant on Set() operations.
5811  * Access: WO
5812  */
5813 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1);
5814 
5815 /* reg_pmaos_ee
5816  * Event update enable.
5817  * If this bit is set, event generation will be updated based on the e field.
5818  * Only relevant on Set operations.
5819  * Access: WO
5820  */
5821 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1);
5822 
5823 enum mlxsw_reg_pmaos_e {
5824 	MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT,
5825 	MLXSW_REG_PMAOS_E_GENERATE_EVENT,
5826 	MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT,
5827 };
5828 
5829 /* reg_pmaos_e
5830  * Event Generation on operational state change.
5831  * Access: RW
5832  */
5833 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2);
5834 
mlxsw_reg_pmaos_pack(char * payload,u8 slot_index,u8 module)5835 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module)
5836 {
5837 	MLXSW_REG_ZERO(pmaos, payload);
5838 	mlxsw_reg_pmaos_slot_index_set(payload, slot_index);
5839 	mlxsw_reg_pmaos_module_set(payload, module);
5840 }
5841 
5842 /* PPLR - Port Physical Loopback Register
5843  * --------------------------------------
5844  * This register allows configuration of the port's loopback mode.
5845  */
5846 #define MLXSW_REG_PPLR_ID 0x5018
5847 #define MLXSW_REG_PPLR_LEN 0x8
5848 
5849 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);
5850 
5851 /* reg_pplr_local_port
5852  * Local port number.
5853  * Access: Index
5854  */
5855 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12);
5856 
5857 /* Phy local loopback. When set the port's egress traffic is looped back
5858  * to the receiver and the port transmitter is disabled.
5859  */
5860 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
5861 
5862 /* reg_pplr_lb_en
5863  * Loopback enable.
5864  * Access: RW
5865  */
5866 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5867 
mlxsw_reg_pplr_pack(char * payload,u16 local_port,bool phy_local)5868 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port,
5869 				       bool phy_local)
5870 {
5871 	MLXSW_REG_ZERO(pplr, payload);
5872 	mlxsw_reg_pplr_local_port_set(payload, local_port);
5873 	mlxsw_reg_pplr_lb_en_set(payload,
5874 				 phy_local ?
5875 				 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
5876 }
5877 
5878 /* PMTDB - Port Module To local DataBase Register
5879  * ----------------------------------------------
5880  * The PMTDB register allows to query the possible module<->local port
5881  * mapping than can be used in PMLP. It does not represent the actual/current
5882  * mapping of the local to module. Actual mapping is only defined by PMLP.
5883  */
5884 #define MLXSW_REG_PMTDB_ID 0x501A
5885 #define MLXSW_REG_PMTDB_LEN 0x40
5886 
5887 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN);
5888 
5889 /* reg_pmtdb_slot_index
5890  * Slot index (0: Main board).
5891  * Access: Index
5892  */
5893 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4);
5894 
5895 /* reg_pmtdb_module
5896  * Module number.
5897  * Access: Index
5898  */
5899 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8);
5900 
5901 /* reg_pmtdb_ports_width
5902  * Port's width
5903  * Access: Index
5904  */
5905 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4);
5906 
5907 /* reg_pmtdb_num_ports
5908  * Number of ports in a single module (split/breakout)
5909  * Access: Index
5910  */
5911 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4);
5912 
5913 enum mlxsw_reg_pmtdb_status {
5914 	MLXSW_REG_PMTDB_STATUS_SUCCESS,
5915 };
5916 
5917 /* reg_pmtdb_status
5918  * Status
5919  * Access: RO
5920  */
5921 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4);
5922 
5923 /* reg_pmtdb_port_num
5924  * The local_port value which can be assigned to the module.
5925  * In case of more than one port, port<x> represent the /<x> port of
5926  * the module.
5927  * Access: RO
5928  */
5929 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false);
5930 
mlxsw_reg_pmtdb_pack(char * payload,u8 slot_index,u8 module,u8 ports_width,u8 num_ports)5931 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module,
5932 					u8 ports_width, u8 num_ports)
5933 {
5934 	MLXSW_REG_ZERO(pmtdb, payload);
5935 	mlxsw_reg_pmtdb_slot_index_set(payload, slot_index);
5936 	mlxsw_reg_pmtdb_module_set(payload, module);
5937 	mlxsw_reg_pmtdb_ports_width_set(payload, ports_width);
5938 	mlxsw_reg_pmtdb_num_ports_set(payload, num_ports);
5939 }
5940 
5941 /* PMECR - Ports Mapping Event Configuration Register
5942  * --------------------------------------------------
5943  * The PMECR register is used to enable/disable event triggering
5944  * in case of local port mapping change.
5945  */
5946 #define MLXSW_REG_PMECR_ID 0x501B
5947 #define MLXSW_REG_PMECR_LEN 0x20
5948 
5949 MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN);
5950 
5951 /* reg_pmecr_local_port
5952  * Local port number.
5953  * Access: Index
5954  */
5955 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12);
5956 
5957 /* reg_pmecr_ee
5958  * Event update enable. If this bit is set, event generation will be updated
5959  * based on the e field. Only relevant on Set operations.
5960  * Access: WO
5961  */
5962 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1);
5963 
5964 /* reg_pmecr_eswi
5965  * Software ignore enable bit. If this bit is set, the value of swi is used.
5966  * If this bit is clear, the value of swi is ignored.
5967  * Only relevant on Set operations.
5968  * Access: WO
5969  */
5970 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1);
5971 
5972 /* reg_pmecr_swi
5973  * Software ignore. If this bit is set, the device shouldn't generate events
5974  * in case of PMLP SET operation but only upon self local port mapping change
5975  * (if applicable according to e configuration). This is supplementary
5976  * configuration on top of e value.
5977  * Access: RW
5978  */
5979 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1);
5980 
5981 enum mlxsw_reg_pmecr_e {
5982 	MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT,
5983 	MLXSW_REG_PMECR_E_GENERATE_EVENT,
5984 	MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT,
5985 };
5986 
5987 /* reg_pmecr_e
5988  * Event generation on local port mapping change.
5989  * Access: RW
5990  */
5991 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2);
5992 
mlxsw_reg_pmecr_pack(char * payload,u16 local_port,enum mlxsw_reg_pmecr_e e)5993 static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port,
5994 					enum mlxsw_reg_pmecr_e e)
5995 {
5996 	MLXSW_REG_ZERO(pmecr, payload);
5997 	mlxsw_reg_pmecr_local_port_set(payload, local_port);
5998 	mlxsw_reg_pmecr_e_set(payload, e);
5999 	mlxsw_reg_pmecr_ee_set(payload, true);
6000 	mlxsw_reg_pmecr_swi_set(payload, true);
6001 	mlxsw_reg_pmecr_eswi_set(payload, true);
6002 }
6003 
6004 /* PMPE - Port Module Plug/Unplug Event Register
6005  * ---------------------------------------------
6006  * This register reports any operational status change of a module.
6007  * A change in the module’s state will generate an event only if the change
6008  * happens after arming the event mechanism. Any changes to the module state
6009  * while the event mechanism is not armed will not be reported. Software can
6010  * query the PMPE register for module status.
6011  */
6012 #define MLXSW_REG_PMPE_ID 0x5024
6013 #define MLXSW_REG_PMPE_LEN 0x10
6014 
6015 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN);
6016 
6017 /* reg_pmpe_slot_index
6018  * Slot index.
6019  * Access: Index
6020  */
6021 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4);
6022 
6023 /* reg_pmpe_module
6024  * Module number.
6025  * Access: Index
6026  */
6027 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8);
6028 
6029 enum mlxsw_reg_pmpe_module_status {
6030 	MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1,
6031 	MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED,
6032 	MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR,
6033 	MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED,
6034 };
6035 
6036 /* reg_pmpe_module_status
6037  * Module status.
6038  * Access: RO
6039  */
6040 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4);
6041 
6042 /* reg_pmpe_error_type
6043  * Module error details.
6044  * Access: RO
6045  */
6046 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4);
6047 
6048 /* PDDR - Port Diagnostics Database Register
6049  * -----------------------------------------
6050  * The PDDR enables to read the Phy debug database
6051  */
6052 #define MLXSW_REG_PDDR_ID 0x5031
6053 #define MLXSW_REG_PDDR_LEN 0x100
6054 
6055 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN);
6056 
6057 /* reg_pddr_local_port
6058  * Local port number.
6059  * Access: Index
6060  */
6061 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12);
6062 
6063 enum mlxsw_reg_pddr_page_select {
6064 	MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1,
6065 };
6066 
6067 /* reg_pddr_page_select
6068  * Page select index.
6069  * Access: Index
6070  */
6071 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8);
6072 
6073 enum mlxsw_reg_pddr_trblsh_group_opcode {
6074 	/* Monitor opcodes */
6075 	MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR,
6076 };
6077 
6078 /* reg_pddr_group_opcode
6079  * Group selector.
6080  * Access: Index
6081  */
6082 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16);
6083 
6084 /* reg_pddr_status_opcode
6085  * Group selector.
6086  * Access: RO
6087  */
6088 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16);
6089 
mlxsw_reg_pddr_pack(char * payload,u16 local_port,u8 page_select)6090 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port,
6091 				       u8 page_select)
6092 {
6093 	MLXSW_REG_ZERO(pddr, payload);
6094 	mlxsw_reg_pddr_local_port_set(payload, local_port);
6095 	mlxsw_reg_pddr_page_select_set(payload, page_select);
6096 }
6097 
6098 /* PMMP - Port Module Memory Map Properties Register
6099  * -------------------------------------------------
6100  * The PMMP register allows to override the module memory map advertisement.
6101  * The register can only be set when the module is disabled by PMAOS register.
6102  */
6103 #define MLXSW_REG_PMMP_ID 0x5044
6104 #define MLXSW_REG_PMMP_LEN 0x2C
6105 
6106 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN);
6107 
6108 /* reg_pmmp_module
6109  * Module number.
6110  * Access: Index
6111  */
6112 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8);
6113 
6114 /* reg_pmmp_slot_index
6115  * Slot index.
6116  * Access: Index
6117  */
6118 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4);
6119 
6120 /* reg_pmmp_sticky
6121  * When set, will keep eeprom_override values after plug-out event.
6122  * Access: OP
6123  */
6124 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1);
6125 
6126 /* reg_pmmp_eeprom_override_mask
6127  * Write mask bit (negative polarity).
6128  * 0 - Allow write
6129  * 1 - Ignore write
6130  * On write, indicates which of the bits from eeprom_override field are
6131  * updated.
6132  * Access: WO
6133  */
6134 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16);
6135 
6136 enum {
6137 	/* Set module to low power mode */
6138 	MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8),
6139 };
6140 
6141 /* reg_pmmp_eeprom_override
6142  * Override / ignore EEPROM advertisement properties bitmask
6143  * Access: RW
6144  */
6145 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16);
6146 
mlxsw_reg_pmmp_pack(char * payload,u8 slot_index,u8 module)6147 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module)
6148 {
6149 	MLXSW_REG_ZERO(pmmp, payload);
6150 	mlxsw_reg_pmmp_slot_index_set(payload, slot_index);
6151 	mlxsw_reg_pmmp_module_set(payload, module);
6152 }
6153 
6154 /* PLLP - Port Local port to Label Port mapping Register
6155  * -----------------------------------------------------
6156  * The PLLP register returns the mapping from Local Port into Label Port.
6157  */
6158 #define MLXSW_REG_PLLP_ID 0x504A
6159 #define MLXSW_REG_PLLP_LEN 0x10
6160 
6161 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN);
6162 
6163 /* reg_pllp_local_port
6164  * Local port number.
6165  * Access: Index
6166  */
6167 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12);
6168 
6169 /* reg_pllp_label_port
6170  * Front panel label of the port.
6171  * Access: RO
6172  */
6173 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8);
6174 
6175 /* reg_pllp_split_num
6176  * Label split mapping for local_port.
6177  * Access: RO
6178  */
6179 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4);
6180 
6181 /* reg_pllp_slot_index
6182  * Slot index (0: Main board).
6183  * Access: RO
6184  */
6185 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4);
6186 
mlxsw_reg_pllp_pack(char * payload,u16 local_port)6187 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port)
6188 {
6189 	MLXSW_REG_ZERO(pllp, payload);
6190 	mlxsw_reg_pllp_local_port_set(payload, local_port);
6191 }
6192 
mlxsw_reg_pllp_unpack(char * payload,u8 * label_port,u8 * split_num,u8 * slot_index)6193 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port,
6194 					 u8 *split_num, u8 *slot_index)
6195 {
6196 	*label_port = mlxsw_reg_pllp_label_port_get(payload);
6197 	*split_num = mlxsw_reg_pllp_split_num_get(payload);
6198 	*slot_index = mlxsw_reg_pllp_slot_index_get(payload);
6199 }
6200 
6201 /* PMTM - Port Module Type Mapping Register
6202  * ----------------------------------------
6203  * The PMTM register allows query or configuration of module types.
6204  * The register can only be set when the module is disabled by PMAOS register
6205  */
6206 #define MLXSW_REG_PMTM_ID 0x5067
6207 #define MLXSW_REG_PMTM_LEN 0x10
6208 
6209 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN);
6210 
6211 /* reg_pmtm_slot_index
6212  * Slot index.
6213  * Access: Index
6214  */
6215 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4);
6216 
6217 /* reg_pmtm_module
6218  * Module number.
6219  * Access: Index
6220  */
6221 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8);
6222 
6223 enum mlxsw_reg_pmtm_module_type {
6224 	MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0,
6225 	MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1,
6226 	MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2,
6227 	MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4,
6228 	MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8,
6229 	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10,
6230 	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11,
6231 	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12,
6232 	MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14,
6233 	MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15,
6234 	MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16,
6235 	MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17,
6236 	MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18,
6237 	MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19,
6238 };
6239 
6240 /* reg_pmtm_module_type
6241  * Module type.
6242  * Access: RW
6243  */
6244 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5);
6245 
mlxsw_reg_pmtm_pack(char * payload,u8 slot_index,u8 module)6246 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module)
6247 {
6248 	MLXSW_REG_ZERO(pmtm, payload);
6249 	mlxsw_reg_pmtm_slot_index_set(payload, slot_index);
6250 	mlxsw_reg_pmtm_module_set(payload, module);
6251 }
6252 
6253 /* HTGT - Host Trap Group Table
6254  * ----------------------------
6255  * Configures the properties for forwarding to CPU.
6256  */
6257 #define MLXSW_REG_HTGT_ID 0x7002
6258 #define MLXSW_REG_HTGT_LEN 0x20
6259 
6260 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
6261 
6262 /* reg_htgt_swid
6263  * Switch partition ID.
6264  * Access: Index
6265  */
6266 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
6267 
6268 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0	/* For locally attached CPU */
6269 
6270 /* reg_htgt_type
6271  * CPU path type.
6272  * Access: RW
6273  */
6274 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
6275 
6276 enum mlxsw_reg_htgt_trap_group {
6277 	MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
6278 	MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT,
6279 	MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
6280 	MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
6281 	MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
6282 	MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING,
6283 	MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
6284 	MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
6285 	MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
6286 	MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
6287 	MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY,
6288 	MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
6289 	MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE,
6290 	MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
6291 	MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
6292 	MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
6293 	MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6,
6294 	MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
6295 	MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,
6296 	MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,
6297 	MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP,
6298 	MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE,
6299 	MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING,
6300 	MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS,
6301 	MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD,
6302 	MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY,
6303 	MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS,
6304 	MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS,
6305 	MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS,
6306 	MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS,
6307 	MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS,
6308 	MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS,
6309 
6310 	__MLXSW_REG_HTGT_TRAP_GROUP_MAX,
6311 	MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1
6312 };
6313 
6314 /* reg_htgt_trap_group
6315  * Trap group number. User defined number specifying which trap groups
6316  * should be forwarded to the CPU. The mapping between trap IDs and trap
6317  * groups is configured using HPKT register.
6318  * Access: Index
6319  */
6320 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
6321 
6322 enum {
6323 	MLXSW_REG_HTGT_POLICER_DISABLE,
6324 	MLXSW_REG_HTGT_POLICER_ENABLE,
6325 };
6326 
6327 /* reg_htgt_pide
6328  * Enable policer ID specified using 'pid' field.
6329  * Access: RW
6330  */
6331 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
6332 
6333 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff
6334 
6335 /* reg_htgt_pid
6336  * Policer ID for the trap group.
6337  * Access: RW
6338  */
6339 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
6340 
6341 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
6342 
6343 /* reg_htgt_mirror_action
6344  * Mirror action to use.
6345  * 0 - Trap to CPU.
6346  * 1 - Trap to CPU and mirror to a mirroring agent.
6347  * 2 - Mirror to a mirroring agent and do not trap to CPU.
6348  * Access: RW
6349  *
6350  * Note: Mirroring to a mirroring agent is only supported in Spectrum.
6351  */
6352 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
6353 
6354 /* reg_htgt_mirroring_agent
6355  * Mirroring agent.
6356  * Access: RW
6357  */
6358 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
6359 
6360 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
6361 
6362 /* reg_htgt_priority
6363  * Trap group priority.
6364  * In case a packet matches multiple classification rules, the packet will
6365  * only be trapped once, based on the trap ID associated with the group (via
6366  * register HPKT) with the highest priority.
6367  * Supported values are 0-7, with 7 represnting the highest priority.
6368  * Access: RW
6369  *
6370  * Note: In SwitchX-2 this field is ignored and the priority value is replaced
6371  * by the 'trap_group' field.
6372  */
6373 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
6374 
6375 #define MLXSW_REG_HTGT_DEFAULT_TC 7
6376 
6377 /* reg_htgt_local_path_cpu_tclass
6378  * CPU ingress traffic class for the trap group.
6379  * Access: RW
6380  */
6381 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
6382 
6383 enum mlxsw_reg_htgt_local_path_rdq {
6384 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
6385 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
6386 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
6387 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
6388 };
6389 /* reg_htgt_local_path_rdq
6390  * Receive descriptor queue (RDQ) to use for the trap group.
6391  * Access: RW
6392  */
6393 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
6394 
mlxsw_reg_htgt_pack(char * payload,u8 group,u8 policer_id,u8 priority,u8 tc)6395 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
6396 				       u8 priority, u8 tc)
6397 {
6398 	MLXSW_REG_ZERO(htgt, payload);
6399 
6400 	if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
6401 		mlxsw_reg_htgt_pide_set(payload,
6402 					MLXSW_REG_HTGT_POLICER_DISABLE);
6403 	} else {
6404 		mlxsw_reg_htgt_pide_set(payload,
6405 					MLXSW_REG_HTGT_POLICER_ENABLE);
6406 		mlxsw_reg_htgt_pid_set(payload, policer_id);
6407 	}
6408 
6409 	mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
6410 	mlxsw_reg_htgt_trap_group_set(payload, group);
6411 	mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
6412 	mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
6413 	mlxsw_reg_htgt_priority_set(payload, priority);
6414 	mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
6415 	mlxsw_reg_htgt_local_path_rdq_set(payload, group);
6416 }
6417 
6418 /* HPKT - Host Packet Trap
6419  * -----------------------
6420  * Configures trap IDs inside trap groups.
6421  */
6422 #define MLXSW_REG_HPKT_ID 0x7003
6423 #define MLXSW_REG_HPKT_LEN 0x10
6424 
6425 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
6426 
6427 enum {
6428 	MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
6429 	MLXSW_REG_HPKT_ACK_REQUIRED,
6430 };
6431 
6432 /* reg_hpkt_ack
6433  * Require acknowledgements from the host for events.
6434  * If set, then the device will wait for the event it sent to be acknowledged
6435  * by the host. This option is only relevant for event trap IDs.
6436  * Access: RW
6437  *
6438  * Note: Currently not supported by firmware.
6439  */
6440 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
6441 
6442 enum mlxsw_reg_hpkt_action {
6443 	MLXSW_REG_HPKT_ACTION_FORWARD,
6444 	MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
6445 	MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
6446 	MLXSW_REG_HPKT_ACTION_DISCARD,
6447 	MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
6448 	MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
6449 	MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU,
6450 	MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15,
6451 };
6452 
6453 /* reg_hpkt_action
6454  * Action to perform on packet when trapped.
6455  * 0 - No action. Forward to CPU based on switching rules.
6456  * 1 - Trap to CPU (CPU receives sole copy).
6457  * 2 - Mirror to CPU (CPU receives a replica of the packet).
6458  * 3 - Discard.
6459  * 4 - Soft discard (allow other traps to act on the packet).
6460  * 5 - Trap and soft discard (allow other traps to overwrite this trap).
6461  * 6 - Trap to CPU (CPU receives sole copy) and count it as error.
6462  * 15 - Restore the firmware's default action.
6463  * Access: RW
6464  *
6465  * Note: Must be set to 0 (forward) for event trap IDs, as they are already
6466  * addressed to the CPU.
6467  */
6468 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
6469 
6470 /* reg_hpkt_trap_group
6471  * Trap group to associate the trap with.
6472  * Access: RW
6473  */
6474 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
6475 
6476 /* reg_hpkt_trap_id
6477  * Trap ID.
6478  * Access: Index
6479  *
6480  * Note: A trap ID can only be associated with a single trap group. The device
6481  * will associate the trap ID with the last trap group configured.
6482  */
6483 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10);
6484 
6485 enum {
6486 	MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
6487 	MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
6488 	MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
6489 };
6490 
6491 /* reg_hpkt_ctrl
6492  * Configure dedicated buffer resources for control packets.
6493  * Ignored by SwitchX-2.
6494  * 0 - Keep factory defaults.
6495  * 1 - Do not use control buffer for this trap ID.
6496  * 2 - Use control buffer for this trap ID.
6497  * Access: RW
6498  */
6499 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
6500 
mlxsw_reg_hpkt_pack(char * payload,u8 action,u16 trap_id,enum mlxsw_reg_htgt_trap_group trap_group,bool is_ctrl)6501 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
6502 				       enum mlxsw_reg_htgt_trap_group trap_group,
6503 				       bool is_ctrl)
6504 {
6505 	MLXSW_REG_ZERO(hpkt, payload);
6506 	mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
6507 	mlxsw_reg_hpkt_action_set(payload, action);
6508 	mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
6509 	mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
6510 	mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
6511 				MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
6512 				MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
6513 }
6514 
6515 /* RGCR - Router General Configuration Register
6516  * --------------------------------------------
6517  * The register is used for setting up the router configuration.
6518  */
6519 #define MLXSW_REG_RGCR_ID 0x8001
6520 #define MLXSW_REG_RGCR_LEN 0x28
6521 
6522 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
6523 
6524 /* reg_rgcr_ipv4_en
6525  * IPv4 router enable.
6526  * Access: RW
6527  */
6528 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
6529 
6530 /* reg_rgcr_ipv6_en
6531  * IPv6 router enable.
6532  * Access: RW
6533  */
6534 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
6535 
6536 /* reg_rgcr_max_router_interfaces
6537  * Defines the maximum number of active router interfaces for all virtual
6538  * routers.
6539  * Access: RW
6540  */
6541 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
6542 
6543 /* reg_rgcr_usp
6544  * Update switch priority and packet color.
6545  * 0 - Preserve the value of Switch Priority and packet color.
6546  * 1 - Recalculate the value of Switch Priority and packet color.
6547  * Access: RW
6548  *
6549  * Note: Not supported by SwitchX and SwitchX-2.
6550  */
6551 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
6552 
6553 /* reg_rgcr_pcp_rw
6554  * Indicates how to handle the pcp_rewrite_en value:
6555  * 0 - Preserve the value of pcp_rewrite_en.
6556  * 2 - Disable PCP rewrite.
6557  * 3 - Enable PCP rewrite.
6558  * Access: RW
6559  *
6560  * Note: Not supported by SwitchX and SwitchX-2.
6561  */
6562 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
6563 
6564 /* reg_rgcr_activity_dis
6565  * Activity disable:
6566  * 0 - Activity will be set when an entry is hit (default).
6567  * 1 - Activity will not be set when an entry is hit.
6568  *
6569  * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
6570  * (RALUE).
6571  * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
6572  * Entry (RAUHT).
6573  * Bits 2:7 are reserved.
6574  * Access: RW
6575  *
6576  * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
6577  */
6578 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
6579 
mlxsw_reg_rgcr_pack(char * payload,bool ipv4_en,bool ipv6_en)6580 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
6581 				       bool ipv6_en)
6582 {
6583 	MLXSW_REG_ZERO(rgcr, payload);
6584 	mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
6585 	mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
6586 }
6587 
6588 /* RITR - Router Interface Table Register
6589  * --------------------------------------
6590  * The register is used to configure the router interface table.
6591  */
6592 #define MLXSW_REG_RITR_ID 0x8002
6593 #define MLXSW_REG_RITR_LEN 0x40
6594 
6595 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
6596 
6597 /* reg_ritr_enable
6598  * Enables routing on the router interface.
6599  * Access: RW
6600  */
6601 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
6602 
6603 /* reg_ritr_ipv4
6604  * IPv4 routing enable. Enables routing of IPv4 traffic on the router
6605  * interface.
6606  * Access: RW
6607  */
6608 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
6609 
6610 /* reg_ritr_ipv6
6611  * IPv6 routing enable. Enables routing of IPv6 traffic on the router
6612  * interface.
6613  * Access: RW
6614  */
6615 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
6616 
6617 /* reg_ritr_ipv4_mc
6618  * IPv4 multicast routing enable.
6619  * Access: RW
6620  */
6621 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
6622 
6623 /* reg_ritr_ipv6_mc
6624  * IPv6 multicast routing enable.
6625  * Access: RW
6626  */
6627 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
6628 
6629 enum mlxsw_reg_ritr_if_type {
6630 	/* VLAN interface. */
6631 	MLXSW_REG_RITR_VLAN_IF,
6632 	/* FID interface. */
6633 	MLXSW_REG_RITR_FID_IF,
6634 	/* Sub-port interface. */
6635 	MLXSW_REG_RITR_SP_IF,
6636 	/* Loopback Interface. */
6637 	MLXSW_REG_RITR_LOOPBACK_IF,
6638 };
6639 
6640 /* reg_ritr_type
6641  * Router interface type as per enum mlxsw_reg_ritr_if_type.
6642  * Access: RW
6643  */
6644 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
6645 
6646 enum {
6647 	MLXSW_REG_RITR_RIF_CREATE,
6648 	MLXSW_REG_RITR_RIF_DEL,
6649 };
6650 
6651 /* reg_ritr_op
6652  * Opcode:
6653  * 0 - Create or edit RIF.
6654  * 1 - Delete RIF.
6655  * Reserved for SwitchX-2. For Spectrum, editing of interface properties
6656  * is not supported. An interface must be deleted and re-created in order
6657  * to update properties.
6658  * Access: WO
6659  */
6660 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
6661 
6662 /* reg_ritr_rif
6663  * Router interface index. A pointer to the Router Interface Table.
6664  * Access: Index
6665  */
6666 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
6667 
6668 /* reg_ritr_ipv4_fe
6669  * IPv4 Forwarding Enable.
6670  * Enables routing of IPv4 traffic on the router interface. When disabled,
6671  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
6672  * Not supported in SwitchX-2.
6673  * Access: RW
6674  */
6675 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
6676 
6677 /* reg_ritr_ipv6_fe
6678  * IPv6 Forwarding Enable.
6679  * Enables routing of IPv6 traffic on the router interface. When disabled,
6680  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
6681  * Not supported in SwitchX-2.
6682  * Access: RW
6683  */
6684 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
6685 
6686 /* reg_ritr_ipv4_mc_fe
6687  * IPv4 Multicast Forwarding Enable.
6688  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
6689  * will be enabled.
6690  * Access: RW
6691  */
6692 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
6693 
6694 /* reg_ritr_ipv6_mc_fe
6695  * IPv6 Multicast Forwarding Enable.
6696  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
6697  * will be enabled.
6698  * Access: RW
6699  */
6700 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
6701 
6702 /* reg_ritr_lb_en
6703  * Loop-back filter enable for unicast packets.
6704  * If the flag is set then loop-back filter for unicast packets is
6705  * implemented on the RIF. Multicast packets are always subject to
6706  * loop-back filtering.
6707  * Access: RW
6708  */
6709 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
6710 
6711 /* reg_ritr_virtual_router
6712  * Virtual router ID associated with the router interface.
6713  * Access: RW
6714  */
6715 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
6716 
6717 /* reg_ritr_mtu
6718  * Router interface MTU.
6719  * Access: RW
6720  */
6721 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
6722 
6723 /* reg_ritr_if_swid
6724  * Switch partition ID.
6725  * Access: RW
6726  */
6727 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
6728 
6729 /* reg_ritr_if_mac_profile_id
6730  * MAC msb profile ID.
6731  * Access: RW
6732  */
6733 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4);
6734 
6735 /* reg_ritr_if_mac
6736  * Router interface MAC address.
6737  * In Spectrum, all MAC addresses must have the same 38 MSBits.
6738  * Access: RW
6739  */
6740 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
6741 
6742 /* reg_ritr_if_vrrp_id_ipv6
6743  * VRRP ID for IPv6
6744  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
6745  * Access: RW
6746  */
6747 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
6748 
6749 /* reg_ritr_if_vrrp_id_ipv4
6750  * VRRP ID for IPv4
6751  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
6752  * Access: RW
6753  */
6754 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
6755 
6756 /* VLAN Interface */
6757 
6758 /* reg_ritr_vlan_if_vlan_id
6759  * VLAN ID.
6760  * Access: RW
6761  */
6762 MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12);
6763 
6764 /* reg_ritr_vlan_if_efid
6765  * Egress FID.
6766  * Used to connect the RIF to a bridge.
6767  * Access: RW
6768  *
6769  * Note: Reserved when legacy bridge model is used and on Spectrum-1.
6770  */
6771 MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16);
6772 
6773 /* FID Interface */
6774 
6775 /* reg_ritr_fid_if_fid
6776  * Filtering ID. Used to connect a bridge to the router.
6777  * When legacy bridge model is used, only FIDs from the vFID range are
6778  * supported. When unified bridge model is used, this is the egress FID for
6779  * router to bridge.
6780  * Access: RW
6781  */
6782 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
6783 
6784 /* Sub-port Interface */
6785 
6786 /* reg_ritr_sp_if_lag
6787  * LAG indication. When this bit is set the system_port field holds the
6788  * LAG identifier.
6789  * Access: RW
6790  */
6791 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
6792 
6793 /* reg_ritr_sp_system_port
6794  * Port unique indentifier. When lag bit is set, this field holds the
6795  * lag_id in bits 0:9.
6796  * Access: RW
6797  */
6798 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
6799 
6800 /* reg_ritr_sp_if_efid
6801  * Egress filtering ID.
6802  * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or
6803  * the VID.
6804  * Access: RW
6805  *
6806  * Note: Reserved when legacy bridge model is used.
6807  */
6808 MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16);
6809 
6810 /* reg_ritr_sp_if_vid
6811  * VLAN ID.
6812  * Access: RW
6813  */
6814 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
6815 
6816 /* Loopback Interface */
6817 
6818 enum mlxsw_reg_ritr_loopback_protocol {
6819 	/* IPinIP IPv4 underlay Unicast */
6820 	MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
6821 	/* IPinIP IPv6 underlay Unicast */
6822 	MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
6823 	/* IPinIP generic - used for Spectrum-2 underlay RIF */
6824 	MLXSW_REG_RITR_LOOPBACK_GENERIC,
6825 };
6826 
6827 /* reg_ritr_loopback_protocol
6828  * Access: RW
6829  */
6830 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
6831 
6832 enum mlxsw_reg_ritr_loopback_ipip_type {
6833 	/* Tunnel is IPinIP. */
6834 	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
6835 	/* Tunnel is GRE, no key. */
6836 	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
6837 	/* Tunnel is GRE, with a key. */
6838 	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
6839 };
6840 
6841 /* reg_ritr_loopback_ipip_type
6842  * Encapsulation type.
6843  * Access: RW
6844  */
6845 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
6846 
6847 enum mlxsw_reg_ritr_loopback_ipip_options {
6848 	/* The key is defined by gre_key. */
6849 	MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
6850 };
6851 
6852 /* reg_ritr_loopback_ipip_options
6853  * Access: RW
6854  */
6855 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
6856 
6857 /* reg_ritr_loopback_ipip_uvr
6858  * Underlay Virtual Router ID.
6859  * Range is 0..cap_max_virtual_routers-1.
6860  * Reserved for Spectrum-2.
6861  * Access: RW
6862  */
6863 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
6864 
6865 /* reg_ritr_loopback_ipip_underlay_rif
6866  * Underlay ingress router interface.
6867  * Reserved for Spectrum.
6868  * Access: RW
6869  */
6870 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
6871 
6872 /* reg_ritr_loopback_ipip_usip*
6873  * Encapsulation Underlay source IP.
6874  * Access: RW
6875  */
6876 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
6877 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
6878 
6879 /* reg_ritr_loopback_ipip_gre_key
6880  * GRE Key.
6881  * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP.
6882  * Access: RW
6883  */
6884 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
6885 
6886 /* Shared between ingress/egress */
6887 enum mlxsw_reg_ritr_counter_set_type {
6888 	/* No Count. */
6889 	MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
6890 	/* Basic. Used for router interfaces, counting the following:
6891 	 *	- Error and Discard counters.
6892 	 *	- Unicast, Multicast and Broadcast counters. Sharing the
6893 	 *	  same set of counters for the different type of traffic
6894 	 *	  (IPv4, IPv6 and mpls).
6895 	 */
6896 	MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
6897 };
6898 
6899 /* reg_ritr_ingress_counter_index
6900  * Counter Index for flow counter.
6901  * Access: RW
6902  */
6903 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
6904 
6905 /* reg_ritr_ingress_counter_set_type
6906  * Igress Counter Set Type for router interface counter.
6907  * Access: RW
6908  */
6909 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
6910 
6911 /* reg_ritr_egress_counter_index
6912  * Counter Index for flow counter.
6913  * Access: RW
6914  */
6915 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
6916 
6917 /* reg_ritr_egress_counter_set_type
6918  * Egress Counter Set Type for router interface counter.
6919  * Access: RW
6920  */
6921 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
6922 
mlxsw_reg_ritr_counter_pack(char * payload,u32 index,bool enable,bool egress)6923 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
6924 					       bool enable, bool egress)
6925 {
6926 	enum mlxsw_reg_ritr_counter_set_type set_type;
6927 
6928 	if (enable)
6929 		set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
6930 	else
6931 		set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
6932 
6933 	if (egress) {
6934 		mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
6935 		mlxsw_reg_ritr_egress_counter_index_set(payload, index);
6936 	} else {
6937 		mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type);
6938 		mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
6939 	}
6940 }
6941 
mlxsw_reg_ritr_rif_pack(char * payload,u16 rif)6942 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
6943 {
6944 	MLXSW_REG_ZERO(ritr, payload);
6945 	mlxsw_reg_ritr_rif_set(payload, rif);
6946 }
6947 
mlxsw_reg_ritr_sp_if_pack(char * payload,bool lag,u16 system_port,u16 efid,u16 vid)6948 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
6949 					     u16 system_port, u16 efid, u16 vid)
6950 {
6951 	mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
6952 	mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
6953 	mlxsw_reg_ritr_sp_if_efid_set(payload, efid);
6954 	mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
6955 }
6956 
mlxsw_reg_ritr_pack(char * payload,bool enable,enum mlxsw_reg_ritr_if_type type,u16 rif,u16 vr_id,u16 mtu)6957 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
6958 				       enum mlxsw_reg_ritr_if_type type,
6959 				       u16 rif, u16 vr_id, u16 mtu)
6960 {
6961 	bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
6962 
6963 	MLXSW_REG_ZERO(ritr, payload);
6964 	mlxsw_reg_ritr_enable_set(payload, enable);
6965 	mlxsw_reg_ritr_ipv4_set(payload, 1);
6966 	mlxsw_reg_ritr_ipv6_set(payload, 1);
6967 	mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
6968 	mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
6969 	mlxsw_reg_ritr_type_set(payload, type);
6970 	mlxsw_reg_ritr_op_set(payload, op);
6971 	mlxsw_reg_ritr_rif_set(payload, rif);
6972 	mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
6973 	mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
6974 	mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
6975 	mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
6976 	mlxsw_reg_ritr_lb_en_set(payload, 1);
6977 	mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
6978 	mlxsw_reg_ritr_mtu_set(payload, mtu);
6979 }
6980 
mlxsw_reg_ritr_mac_pack(char * payload,const char * mac)6981 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
6982 {
6983 	mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
6984 }
6985 
6986 static inline void
mlxsw_reg_ritr_vlan_if_pack(char * payload,bool enable,u16 rif,u16 vr_id,u16 mtu,const char * mac,u8 mac_profile_id,u16 vlan_id,u16 efid)6987 mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id,
6988 			    u16 mtu, const char *mac, u8 mac_profile_id,
6989 			    u16 vlan_id, u16 efid)
6990 {
6991 	enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF;
6992 
6993 	mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu);
6994 	mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
6995 	mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id);
6996 	mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id);
6997 	mlxsw_reg_ritr_vlan_if_efid_set(payload, efid);
6998 }
6999 
7000 static inline void
mlxsw_reg_ritr_loopback_ipip_common_pack(char * payload,enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,enum mlxsw_reg_ritr_loopback_ipip_options options,u16 uvr_id,u16 underlay_rif,u32 gre_key)7001 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
7002 			    enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
7003 			    enum mlxsw_reg_ritr_loopback_ipip_options options,
7004 			    u16 uvr_id, u16 underlay_rif, u32 gre_key)
7005 {
7006 	mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
7007 	mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
7008 	mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
7009 	mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);
7010 	mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
7011 }
7012 
7013 static inline void
mlxsw_reg_ritr_loopback_ipip4_pack(char * payload,enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,enum mlxsw_reg_ritr_loopback_ipip_options options,u16 uvr_id,u16 underlay_rif,u32 usip,u32 gre_key)7014 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
7015 			    enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
7016 			    enum mlxsw_reg_ritr_loopback_ipip_options options,
7017 			    u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)
7018 {
7019 	mlxsw_reg_ritr_loopback_protocol_set(payload,
7020 				    MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
7021 	mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
7022 						 uvr_id, underlay_rif, gre_key);
7023 	mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
7024 }
7025 
7026 static inline void
mlxsw_reg_ritr_loopback_ipip6_pack(char * payload,enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,enum mlxsw_reg_ritr_loopback_ipip_options options,u16 uvr_id,u16 underlay_rif,const struct in6_addr * usip,u32 gre_key)7027 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload,
7028 				   enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
7029 				   enum mlxsw_reg_ritr_loopback_ipip_options options,
7030 				   u16 uvr_id, u16 underlay_rif,
7031 				   const struct in6_addr *usip, u32 gre_key)
7032 {
7033 	enum mlxsw_reg_ritr_loopback_protocol protocol =
7034 		MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6;
7035 
7036 	mlxsw_reg_ritr_loopback_protocol_set(payload, protocol);
7037 	mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
7038 						 uvr_id, underlay_rif, gre_key);
7039 	mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload,
7040 						     (const char *)usip);
7041 }
7042 
7043 /* RTAR - Router TCAM Allocation Register
7044  * --------------------------------------
7045  * This register is used for allocation of regions in the TCAM table.
7046  */
7047 #define MLXSW_REG_RTAR_ID 0x8004
7048 #define MLXSW_REG_RTAR_LEN 0x20
7049 
7050 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
7051 
7052 enum mlxsw_reg_rtar_op {
7053 	MLXSW_REG_RTAR_OP_ALLOCATE,
7054 	MLXSW_REG_RTAR_OP_RESIZE,
7055 	MLXSW_REG_RTAR_OP_DEALLOCATE,
7056 };
7057 
7058 /* reg_rtar_op
7059  * Access: WO
7060  */
7061 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
7062 
7063 enum mlxsw_reg_rtar_key_type {
7064 	MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
7065 	MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
7066 };
7067 
7068 /* reg_rtar_key_type
7069  * TCAM key type for the region.
7070  * Access: WO
7071  */
7072 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
7073 
7074 /* reg_rtar_region_size
7075  * TCAM region size. When allocating/resizing this is the requested
7076  * size, the response is the actual size.
7077  * Note: Actual size may be larger than requested.
7078  * Reserved for op = Deallocate
7079  * Access: WO
7080  */
7081 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
7082 
mlxsw_reg_rtar_pack(char * payload,enum mlxsw_reg_rtar_op op,enum mlxsw_reg_rtar_key_type key_type,u16 region_size)7083 static inline void mlxsw_reg_rtar_pack(char *payload,
7084 				       enum mlxsw_reg_rtar_op op,
7085 				       enum mlxsw_reg_rtar_key_type key_type,
7086 				       u16 region_size)
7087 {
7088 	MLXSW_REG_ZERO(rtar, payload);
7089 	mlxsw_reg_rtar_op_set(payload, op);
7090 	mlxsw_reg_rtar_key_type_set(payload, key_type);
7091 	mlxsw_reg_rtar_region_size_set(payload, region_size);
7092 }
7093 
7094 /* RATR - Router Adjacency Table Register
7095  * --------------------------------------
7096  * The RATR register is used to configure the Router Adjacency (next-hop)
7097  * Table.
7098  */
7099 #define MLXSW_REG_RATR_ID 0x8008
7100 #define MLXSW_REG_RATR_LEN 0x2C
7101 
7102 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
7103 
7104 enum mlxsw_reg_ratr_op {
7105 	/* Read */
7106 	MLXSW_REG_RATR_OP_QUERY_READ = 0,
7107 	/* Read and clear activity */
7108 	MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
7109 	/* Write Adjacency entry */
7110 	MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
7111 	/* Write Adjacency entry only if the activity is cleared.
7112 	 * The write may not succeed if the activity is set. There is not
7113 	 * direct feedback if the write has succeeded or not, however
7114 	 * the get will reveal the actual entry (SW can compare the get
7115 	 * response to the set command).
7116 	 */
7117 	MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
7118 };
7119 
7120 /* reg_ratr_op
7121  * Note that Write operation may also be used for updating
7122  * counter_set_type and counter_index. In this case all other
7123  * fields must not be updated.
7124  * Access: OP
7125  */
7126 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
7127 
7128 /* reg_ratr_v
7129  * Valid bit. Indicates if the adjacency entry is valid.
7130  * Note: the device may need some time before reusing an invalidated
7131  * entry. During this time the entry can not be reused. It is
7132  * recommended to use another entry before reusing an invalidated
7133  * entry (e.g. software can put it at the end of the list for
7134  * reusing). Trying to access an invalidated entry not yet cleared
7135  * by the device results with failure indicating "Try Again" status.
7136  * When valid is '0' then egress_router_interface,trap_action,
7137  * adjacency_parameters and counters are reserved
7138  * Access: RW
7139  */
7140 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
7141 
7142 /* reg_ratr_a
7143  * Activity. Set for new entries. Set if a packet lookup has hit on
7144  * the specific entry. To clear the a bit, use "clear activity".
7145  * Access: RO
7146  */
7147 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
7148 
7149 enum mlxsw_reg_ratr_type {
7150 	/* Ethernet */
7151 	MLXSW_REG_RATR_TYPE_ETHERNET,
7152 	/* IPoIB Unicast without GRH.
7153 	 * Reserved for Spectrum.
7154 	 */
7155 	MLXSW_REG_RATR_TYPE_IPOIB_UC,
7156 	/* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast
7157 	 * adjacency).
7158 	 * Reserved for Spectrum.
7159 	 */
7160 	MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
7161 	/* IPoIB Multicast.
7162 	 * Reserved for Spectrum.
7163 	 */
7164 	MLXSW_REG_RATR_TYPE_IPOIB_MC,
7165 	/* MPLS.
7166 	 * Reserved for SwitchX/-2.
7167 	 */
7168 	MLXSW_REG_RATR_TYPE_MPLS,
7169 	/* IPinIP Encap.
7170 	 * Reserved for SwitchX/-2.
7171 	 */
7172 	MLXSW_REG_RATR_TYPE_IPIP,
7173 };
7174 
7175 /* reg_ratr_type
7176  * Adjacency entry type.
7177  * Access: RW
7178  */
7179 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
7180 
7181 /* reg_ratr_adjacency_index_low
7182  * Bits 15:0 of index into the adjacency table.
7183  * For SwitchX and SwitchX-2, the adjacency table is linear and
7184  * used for adjacency entries only.
7185  * For Spectrum, the index is to the KVD linear.
7186  * Access: Index
7187  */
7188 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
7189 
7190 /* reg_ratr_egress_router_interface
7191  * Range is 0 .. cap_max_router_interfaces - 1
7192  * Access: RW
7193  */
7194 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
7195 
7196 enum mlxsw_reg_ratr_trap_action {
7197 	MLXSW_REG_RATR_TRAP_ACTION_NOP,
7198 	MLXSW_REG_RATR_TRAP_ACTION_TRAP,
7199 	MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
7200 	MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
7201 	MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
7202 };
7203 
7204 /* reg_ratr_trap_action
7205  * see mlxsw_reg_ratr_trap_action
7206  * Access: RW
7207  */
7208 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
7209 
7210 /* reg_ratr_adjacency_index_high
7211  * Bits 23:16 of the adjacency_index.
7212  * Access: Index
7213  */
7214 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
7215 
7216 enum mlxsw_reg_ratr_trap_id {
7217 	MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
7218 	MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
7219 };
7220 
7221 /* reg_ratr_trap_id
7222  * Trap ID to be reported to CPU.
7223  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
7224  * For trap_action of NOP, MIRROR and DISCARD_ERROR
7225  * Access: RW
7226  */
7227 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
7228 
7229 /* reg_ratr_eth_destination_mac
7230  * MAC address of the destination next-hop.
7231  * Access: RW
7232  */
7233 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
7234 
7235 enum mlxsw_reg_ratr_ipip_type {
7236 	/* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */
7237 	MLXSW_REG_RATR_IPIP_TYPE_IPV4,
7238 	/* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */
7239 	MLXSW_REG_RATR_IPIP_TYPE_IPV6,
7240 };
7241 
7242 /* reg_ratr_ipip_type
7243  * Underlay destination ip type.
7244  * Note: the type field must match the protocol of the router interface.
7245  * Access: RW
7246  */
7247 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
7248 
7249 /* reg_ratr_ipip_ipv4_udip
7250  * Underlay ipv4 dip.
7251  * Reserved when ipip_type is IPv6.
7252  * Access: RW
7253  */
7254 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
7255 
7256 /* reg_ratr_ipip_ipv6_ptr
7257  * Pointer to IPv6 underlay destination ip address.
7258  * For Spectrum: Pointer to KVD linear space.
7259  * Access: RW
7260  */
7261 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
7262 
7263 enum mlxsw_reg_flow_counter_set_type {
7264 	/* No count */
7265 	MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
7266 	/* Count packets and bytes */
7267 	MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
7268 	/* Count only packets */
7269 	MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
7270 };
7271 
7272 /* reg_ratr_counter_set_type
7273  * Counter set type for flow counters
7274  * Access: RW
7275  */
7276 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
7277 
7278 /* reg_ratr_counter_index
7279  * Counter index for flow counters
7280  * Access: RW
7281  */
7282 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
7283 
7284 static inline void
mlxsw_reg_ratr_pack(char * payload,enum mlxsw_reg_ratr_op op,bool valid,enum mlxsw_reg_ratr_type type,u32 adjacency_index,u16 egress_rif)7285 mlxsw_reg_ratr_pack(char *payload,
7286 		    enum mlxsw_reg_ratr_op op, bool valid,
7287 		    enum mlxsw_reg_ratr_type type,
7288 		    u32 adjacency_index, u16 egress_rif)
7289 {
7290 	MLXSW_REG_ZERO(ratr, payload);
7291 	mlxsw_reg_ratr_op_set(payload, op);
7292 	mlxsw_reg_ratr_v_set(payload, valid);
7293 	mlxsw_reg_ratr_type_set(payload, type);
7294 	mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
7295 	mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
7296 	mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
7297 }
7298 
mlxsw_reg_ratr_eth_entry_pack(char * payload,const char * dest_mac)7299 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
7300 						 const char *dest_mac)
7301 {
7302 	mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
7303 }
7304 
mlxsw_reg_ratr_ipip4_entry_pack(char * payload,u32 ipv4_udip)7305 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
7306 {
7307 	mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
7308 	mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
7309 }
7310 
mlxsw_reg_ratr_ipip6_entry_pack(char * payload,u32 ipv6_ptr)7311 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr)
7312 {
7313 	mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6);
7314 	mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr);
7315 }
7316 
mlxsw_reg_ratr_counter_pack(char * payload,u64 counter_index,bool counter_enable)7317 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
7318 					       bool counter_enable)
7319 {
7320 	enum mlxsw_reg_flow_counter_set_type set_type;
7321 
7322 	if (counter_enable)
7323 		set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
7324 	else
7325 		set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
7326 
7327 	mlxsw_reg_ratr_counter_index_set(payload, counter_index);
7328 	mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
7329 }
7330 
7331 /* RDPM - Router DSCP to Priority Mapping
7332  * --------------------------------------
7333  * Controls the mapping from DSCP field to switch priority on routed packets
7334  */
7335 #define MLXSW_REG_RDPM_ID 0x8009
7336 #define MLXSW_REG_RDPM_BASE_LEN 0x00
7337 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
7338 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
7339 #define MLXSW_REG_RDPM_LEN 0x40
7340 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
7341 				   MLXSW_REG_RDPM_LEN - \
7342 				   MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
7343 
7344 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
7345 
7346 /* reg_dscp_entry_e
7347  * Enable update of the specific entry
7348  * Access: Index
7349  */
7350 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
7351 		    -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
7352 
7353 /* reg_dscp_entry_prio
7354  * Switch Priority
7355  * Access: RW
7356  */
7357 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
7358 		    -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
7359 
mlxsw_reg_rdpm_pack(char * payload,unsigned short index,u8 prio)7360 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
7361 				       u8 prio)
7362 {
7363 	mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
7364 	mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
7365 }
7366 
7367 /* RICNT - Router Interface Counter Register
7368  * -----------------------------------------
7369  * The RICNT register retrieves per port performance counters
7370  */
7371 #define MLXSW_REG_RICNT_ID 0x800B
7372 #define MLXSW_REG_RICNT_LEN 0x100
7373 
7374 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
7375 
7376 /* reg_ricnt_counter_index
7377  * Counter index
7378  * Access: RW
7379  */
7380 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
7381 
7382 enum mlxsw_reg_ricnt_counter_set_type {
7383 	/* No Count. */
7384 	MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
7385 	/* Basic. Used for router interfaces, counting the following:
7386 	 *	- Error and Discard counters.
7387 	 *	- Unicast, Multicast and Broadcast counters. Sharing the
7388 	 *	  same set of counters for the different type of traffic
7389 	 *	  (IPv4, IPv6 and mpls).
7390 	 */
7391 	MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
7392 };
7393 
7394 /* reg_ricnt_counter_set_type
7395  * Counter Set Type for router interface counter
7396  * Access: RW
7397  */
7398 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
7399 
7400 enum mlxsw_reg_ricnt_opcode {
7401 	/* Nop. Supported only for read access*/
7402 	MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
7403 	/* Clear. Setting the clr bit will reset the counter value for
7404 	 * all counters of the specified Router Interface.
7405 	 */
7406 	MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
7407 };
7408 
7409 /* reg_ricnt_opcode
7410  * Opcode
7411  * Access: RW
7412  */
7413 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
7414 
7415 /* reg_ricnt_good_unicast_packets
7416  * good unicast packets.
7417  * Access: RW
7418  */
7419 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
7420 
7421 /* reg_ricnt_good_multicast_packets
7422  * good multicast packets.
7423  * Access: RW
7424  */
7425 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
7426 
7427 /* reg_ricnt_good_broadcast_packets
7428  * good broadcast packets
7429  * Access: RW
7430  */
7431 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
7432 
7433 /* reg_ricnt_good_unicast_bytes
7434  * A count of L3 data and padding octets not including L2 headers
7435  * for good unicast frames.
7436  * Access: RW
7437  */
7438 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
7439 
7440 /* reg_ricnt_good_multicast_bytes
7441  * A count of L3 data and padding octets not including L2 headers
7442  * for good multicast frames.
7443  * Access: RW
7444  */
7445 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
7446 
7447 /* reg_ritr_good_broadcast_bytes
7448  * A count of L3 data and padding octets not including L2 headers
7449  * for good broadcast frames.
7450  * Access: RW
7451  */
7452 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
7453 
7454 /* reg_ricnt_error_packets
7455  * A count of errored frames that do not pass the router checks.
7456  * Access: RW
7457  */
7458 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
7459 
7460 /* reg_ricnt_discrad_packets
7461  * A count of non-errored frames that do not pass the router checks.
7462  * Access: RW
7463  */
7464 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
7465 
7466 /* reg_ricnt_error_bytes
7467  * A count of L3 data and padding octets not including L2 headers
7468  * for errored frames.
7469  * Access: RW
7470  */
7471 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
7472 
7473 /* reg_ricnt_discard_bytes
7474  * A count of L3 data and padding octets not including L2 headers
7475  * for non-errored frames that do not pass the router checks.
7476  * Access: RW
7477  */
7478 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
7479 
mlxsw_reg_ricnt_pack(char * payload,u32 index,enum mlxsw_reg_ricnt_opcode op)7480 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
7481 					enum mlxsw_reg_ricnt_opcode op)
7482 {
7483 	MLXSW_REG_ZERO(ricnt, payload);
7484 	mlxsw_reg_ricnt_op_set(payload, op);
7485 	mlxsw_reg_ricnt_counter_index_set(payload, index);
7486 	mlxsw_reg_ricnt_counter_set_type_set(payload,
7487 					     MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
7488 }
7489 
7490 /* RRCR - Router Rules Copy Register Layout
7491  * ----------------------------------------
7492  * This register is used for moving and copying route entry rules.
7493  */
7494 #define MLXSW_REG_RRCR_ID 0x800F
7495 #define MLXSW_REG_RRCR_LEN 0x24
7496 
7497 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
7498 
7499 enum mlxsw_reg_rrcr_op {
7500 	/* Move rules */
7501 	MLXSW_REG_RRCR_OP_MOVE,
7502 	/* Copy rules */
7503 	MLXSW_REG_RRCR_OP_COPY,
7504 };
7505 
7506 /* reg_rrcr_op
7507  * Access: WO
7508  */
7509 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
7510 
7511 /* reg_rrcr_offset
7512  * Offset within the region from which to copy/move.
7513  * Access: Index
7514  */
7515 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
7516 
7517 /* reg_rrcr_size
7518  * The number of rules to copy/move.
7519  * Access: WO
7520  */
7521 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
7522 
7523 /* reg_rrcr_table_id
7524  * Identifier of the table on which to perform the operation. Encoding is the
7525  * same as in RTAR.key_type
7526  * Access: Index
7527  */
7528 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
7529 
7530 /* reg_rrcr_dest_offset
7531  * Offset within the region to which to copy/move
7532  * Access: Index
7533  */
7534 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
7535 
mlxsw_reg_rrcr_pack(char * payload,enum mlxsw_reg_rrcr_op op,u16 offset,u16 size,enum mlxsw_reg_rtar_key_type table_id,u16 dest_offset)7536 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
7537 				       u16 offset, u16 size,
7538 				       enum mlxsw_reg_rtar_key_type table_id,
7539 				       u16 dest_offset)
7540 {
7541 	MLXSW_REG_ZERO(rrcr, payload);
7542 	mlxsw_reg_rrcr_op_set(payload, op);
7543 	mlxsw_reg_rrcr_offset_set(payload, offset);
7544 	mlxsw_reg_rrcr_size_set(payload, size);
7545 	mlxsw_reg_rrcr_table_id_set(payload, table_id);
7546 	mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
7547 }
7548 
7549 /* RALTA - Router Algorithmic LPM Tree Allocation Register
7550  * -------------------------------------------------------
7551  * RALTA is used to allocate the LPM trees of the SHSPM method.
7552  */
7553 #define MLXSW_REG_RALTA_ID 0x8010
7554 #define MLXSW_REG_RALTA_LEN 0x04
7555 
7556 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
7557 
7558 /* reg_ralta_op
7559  * opcode (valid for Write, must be 0 on Read)
7560  * 0 - allocate a tree
7561  * 1 - deallocate a tree
7562  * Access: OP
7563  */
7564 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
7565 
7566 enum mlxsw_reg_ralxx_protocol {
7567 	MLXSW_REG_RALXX_PROTOCOL_IPV4,
7568 	MLXSW_REG_RALXX_PROTOCOL_IPV6,
7569 };
7570 
7571 /* reg_ralta_protocol
7572  * Protocol.
7573  * Deallocation opcode: Reserved.
7574  * Access: RW
7575  */
7576 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
7577 
7578 /* reg_ralta_tree_id
7579  * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
7580  * the tree identifier (managed by software).
7581  * Note that tree_id 0 is allocated for a default-route tree.
7582  * Access: Index
7583  */
7584 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
7585 
mlxsw_reg_ralta_pack(char * payload,bool alloc,enum mlxsw_reg_ralxx_protocol protocol,u8 tree_id)7586 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
7587 					enum mlxsw_reg_ralxx_protocol protocol,
7588 					u8 tree_id)
7589 {
7590 	MLXSW_REG_ZERO(ralta, payload);
7591 	mlxsw_reg_ralta_op_set(payload, !alloc);
7592 	mlxsw_reg_ralta_protocol_set(payload, protocol);
7593 	mlxsw_reg_ralta_tree_id_set(payload, tree_id);
7594 }
7595 
7596 /* RALST - Router Algorithmic LPM Structure Tree Register
7597  * ------------------------------------------------------
7598  * RALST is used to set and query the structure of an LPM tree.
7599  * The structure of the tree must be sorted as a sorted binary tree, while
7600  * each node is a bin that is tagged as the length of the prefixes the lookup
7601  * will refer to. Therefore, bin X refers to a set of entries with prefixes
7602  * of X bits to match with the destination address. The bin 0 indicates
7603  * the default action, when there is no match of any prefix.
7604  */
7605 #define MLXSW_REG_RALST_ID 0x8011
7606 #define MLXSW_REG_RALST_LEN 0x104
7607 
7608 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
7609 
7610 /* reg_ralst_root_bin
7611  * The bin number of the root bin.
7612  * 0<root_bin=<(length of IP address)
7613  * For a default-route tree configure 0xff
7614  * Access: RW
7615  */
7616 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
7617 
7618 /* reg_ralst_tree_id
7619  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
7620  * Access: Index
7621  */
7622 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
7623 
7624 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
7625 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
7626 #define MLXSW_REG_RALST_BIN_COUNT 128
7627 
7628 /* reg_ralst_left_child_bin
7629  * Holding the children of the bin according to the stored tree's structure.
7630  * For trees composed of less than 4 blocks, the bins in excess are reserved.
7631  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
7632  * Access: RW
7633  */
7634 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
7635 
7636 /* reg_ralst_right_child_bin
7637  * Holding the children of the bin according to the stored tree's structure.
7638  * For trees composed of less than 4 blocks, the bins in excess are reserved.
7639  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
7640  * Access: RW
7641  */
7642 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
7643 		     false);
7644 
mlxsw_reg_ralst_pack(char * payload,u8 root_bin,u8 tree_id)7645 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
7646 {
7647 	MLXSW_REG_ZERO(ralst, payload);
7648 
7649 	/* Initialize all bins to have no left or right child */
7650 	memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
7651 	       MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
7652 
7653 	mlxsw_reg_ralst_root_bin_set(payload, root_bin);
7654 	mlxsw_reg_ralst_tree_id_set(payload, tree_id);
7655 }
7656 
mlxsw_reg_ralst_bin_pack(char * payload,u8 bin_number,u8 left_child_bin,u8 right_child_bin)7657 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
7658 					    u8 left_child_bin,
7659 					    u8 right_child_bin)
7660 {
7661 	int bin_index = bin_number - 1;
7662 
7663 	mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
7664 	mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
7665 					    right_child_bin);
7666 }
7667 
7668 /* RALTB - Router Algorithmic LPM Tree Binding Register
7669  * ----------------------------------------------------
7670  * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
7671  */
7672 #define MLXSW_REG_RALTB_ID 0x8012
7673 #define MLXSW_REG_RALTB_LEN 0x04
7674 
7675 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
7676 
7677 /* reg_raltb_virtual_router
7678  * Virtual Router ID
7679  * Range is 0..cap_max_virtual_routers-1
7680  * Access: Index
7681  */
7682 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
7683 
7684 /* reg_raltb_protocol
7685  * Protocol.
7686  * Access: Index
7687  */
7688 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
7689 
7690 /* reg_raltb_tree_id
7691  * Tree to be used for the {virtual_router, protocol}
7692  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
7693  * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
7694  * Access: RW
7695  */
7696 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
7697 
mlxsw_reg_raltb_pack(char * payload,u16 virtual_router,enum mlxsw_reg_ralxx_protocol protocol,u8 tree_id)7698 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
7699 					enum mlxsw_reg_ralxx_protocol protocol,
7700 					u8 tree_id)
7701 {
7702 	MLXSW_REG_ZERO(raltb, payload);
7703 	mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
7704 	mlxsw_reg_raltb_protocol_set(payload, protocol);
7705 	mlxsw_reg_raltb_tree_id_set(payload, tree_id);
7706 }
7707 
7708 /* RALUE - Router Algorithmic LPM Unicast Entry Register
7709  * -----------------------------------------------------
7710  * RALUE is used to configure and query LPM entries that serve
7711  * the Unicast protocols.
7712  */
7713 #define MLXSW_REG_RALUE_ID 0x8013
7714 #define MLXSW_REG_RALUE_LEN 0x38
7715 
7716 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
7717 
7718 /* reg_ralue_protocol
7719  * Protocol.
7720  * Access: Index
7721  */
7722 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
7723 
7724 enum mlxsw_reg_ralue_op {
7725 	/* Read operation. If entry doesn't exist, the operation fails. */
7726 	MLXSW_REG_RALUE_OP_QUERY_READ = 0,
7727 	/* Clear on read operation. Used to read entry and
7728 	 * clear Activity bit.
7729 	 */
7730 	MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
7731 	/* Write operation. Used to write a new entry to the table. All RW
7732 	 * fields are written for new entry. Activity bit is set
7733 	 * for new entries.
7734 	 */
7735 	MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
7736 	/* Update operation. Used to update an existing route entry and
7737 	 * only update the RW fields that are detailed in the field
7738 	 * op_u_mask. If entry doesn't exist, the operation fails.
7739 	 */
7740 	MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
7741 	/* Clear activity. The Activity bit (the field a) is cleared
7742 	 * for the entry.
7743 	 */
7744 	MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
7745 	/* Delete operation. Used to delete an existing entry. If entry
7746 	 * doesn't exist, the operation fails.
7747 	 */
7748 	MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
7749 };
7750 
7751 /* reg_ralue_op
7752  * Operation.
7753  * Access: OP
7754  */
7755 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
7756 
7757 /* reg_ralue_a
7758  * Activity. Set for new entries. Set if a packet lookup has hit on the
7759  * specific entry, only if the entry is a route. To clear the a bit, use
7760  * "clear activity" op.
7761  * Enabled by activity_dis in RGCR
7762  * Access: RO
7763  */
7764 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
7765 
7766 /* reg_ralue_virtual_router
7767  * Virtual Router ID
7768  * Range is 0..cap_max_virtual_routers-1
7769  * Access: Index
7770  */
7771 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
7772 
7773 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE	BIT(0)
7774 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN	BIT(1)
7775 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION	BIT(2)
7776 
7777 /* reg_ralue_op_u_mask
7778  * opcode update mask.
7779  * On read operation, this field is reserved.
7780  * This field is valid for update opcode, otherwise - reserved.
7781  * This field is a bitmask of the fields that should be updated.
7782  * Access: WO
7783  */
7784 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
7785 
7786 /* reg_ralue_prefix_len
7787  * Number of bits in the prefix of the LPM route.
7788  * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
7789  * two entries in the physical HW table.
7790  * Access: Index
7791  */
7792 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
7793 
7794 /* reg_ralue_dip*
7795  * The prefix of the route or of the marker that the object of the LPM
7796  * is compared with. The most significant bits of the dip are the prefix.
7797  * The least significant bits must be '0' if the prefix_len is smaller
7798  * than 128 for IPv6 or smaller than 32 for IPv4.
7799  * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
7800  * Access: Index
7801  */
7802 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
7803 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
7804 
7805 enum mlxsw_reg_ralue_entry_type {
7806 	MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
7807 	MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
7808 	MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
7809 };
7810 
7811 /* reg_ralue_entry_type
7812  * Entry type.
7813  * Note - for Marker entries, the action_type and action fields are reserved.
7814  * Access: RW
7815  */
7816 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
7817 
7818 /* reg_ralue_bmp_len
7819  * The best match prefix length in the case that there is no match for
7820  * longer prefixes.
7821  * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
7822  * Note for any update operation with entry_type modification this
7823  * field must be set.
7824  * Access: RW
7825  */
7826 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
7827 
7828 enum mlxsw_reg_ralue_action_type {
7829 	MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
7830 	MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
7831 	MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
7832 };
7833 
7834 /* reg_ralue_action_type
7835  * Action Type
7836  * Indicates how the IP address is connected.
7837  * It can be connected to a local subnet through local_erif or can be
7838  * on a remote subnet connected through a next-hop router,
7839  * or transmitted to the CPU.
7840  * Reserved when entry_type = MARKER_ENTRY
7841  * Access: RW
7842  */
7843 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
7844 
7845 enum mlxsw_reg_ralue_trap_action {
7846 	MLXSW_REG_RALUE_TRAP_ACTION_NOP,
7847 	MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
7848 	MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
7849 	MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
7850 	MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
7851 };
7852 
7853 /* reg_ralue_trap_action
7854  * Trap action.
7855  * For IP2ME action, only NOP and MIRROR are possible.
7856  * Access: RW
7857  */
7858 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
7859 
7860 /* reg_ralue_trap_id
7861  * Trap ID to be reported to CPU.
7862  * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
7863  * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
7864  * Access: RW
7865  */
7866 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
7867 
7868 /* reg_ralue_adjacency_index
7869  * Points to the first entry of the group-based ECMP.
7870  * Only relevant in case of REMOTE action.
7871  * Access: RW
7872  */
7873 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
7874 
7875 /* reg_ralue_ecmp_size
7876  * Amount of sequential entries starting
7877  * from the adjacency_index (the number of ECMPs).
7878  * The valid range is 1-64, 512, 1024, 2048 and 4096.
7879  * Reserved when trap_action is TRAP or DISCARD_ERROR.
7880  * Only relevant in case of REMOTE action.
7881  * Access: RW
7882  */
7883 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
7884 
7885 /* reg_ralue_local_erif
7886  * Egress Router Interface.
7887  * Only relevant in case of LOCAL action.
7888  * Access: RW
7889  */
7890 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
7891 
7892 /* reg_ralue_ip2me_v
7893  * Valid bit for the tunnel_ptr field.
7894  * If valid = 0 then trap to CPU as IP2ME trap ID.
7895  * If valid = 1 and the packet format allows NVE or IPinIP tunnel
7896  * decapsulation then tunnel decapsulation is done.
7897  * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
7898  * decapsulation then trap as IP2ME trap ID.
7899  * Only relevant in case of IP2ME action.
7900  * Access: RW
7901  */
7902 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
7903 
7904 /* reg_ralue_ip2me_tunnel_ptr
7905  * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
7906  * For Spectrum, pointer to KVD Linear.
7907  * Only relevant in case of IP2ME action.
7908  * Access: RW
7909  */
7910 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
7911 
mlxsw_reg_ralue_pack(char * payload,enum mlxsw_reg_ralxx_protocol protocol,enum mlxsw_reg_ralue_op op,u16 virtual_router,u8 prefix_len)7912 static inline void mlxsw_reg_ralue_pack(char *payload,
7913 					enum mlxsw_reg_ralxx_protocol protocol,
7914 					enum mlxsw_reg_ralue_op op,
7915 					u16 virtual_router, u8 prefix_len)
7916 {
7917 	MLXSW_REG_ZERO(ralue, payload);
7918 	mlxsw_reg_ralue_protocol_set(payload, protocol);
7919 	mlxsw_reg_ralue_op_set(payload, op);
7920 	mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
7921 	mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
7922 	mlxsw_reg_ralue_entry_type_set(payload,
7923 				       MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
7924 	mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
7925 }
7926 
mlxsw_reg_ralue_pack4(char * payload,enum mlxsw_reg_ralxx_protocol protocol,enum mlxsw_reg_ralue_op op,u16 virtual_router,u8 prefix_len,u32 dip)7927 static inline void mlxsw_reg_ralue_pack4(char *payload,
7928 					 enum mlxsw_reg_ralxx_protocol protocol,
7929 					 enum mlxsw_reg_ralue_op op,
7930 					 u16 virtual_router, u8 prefix_len,
7931 					 u32 dip)
7932 {
7933 	mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
7934 	mlxsw_reg_ralue_dip4_set(payload, dip);
7935 }
7936 
mlxsw_reg_ralue_pack6(char * payload,enum mlxsw_reg_ralxx_protocol protocol,enum mlxsw_reg_ralue_op op,u16 virtual_router,u8 prefix_len,const void * dip)7937 static inline void mlxsw_reg_ralue_pack6(char *payload,
7938 					 enum mlxsw_reg_ralxx_protocol protocol,
7939 					 enum mlxsw_reg_ralue_op op,
7940 					 u16 virtual_router, u8 prefix_len,
7941 					 const void *dip)
7942 {
7943 	mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
7944 	mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
7945 }
7946 
7947 static inline void
mlxsw_reg_ralue_act_remote_pack(char * payload,enum mlxsw_reg_ralue_trap_action trap_action,u16 trap_id,u32 adjacency_index,u16 ecmp_size)7948 mlxsw_reg_ralue_act_remote_pack(char *payload,
7949 				enum mlxsw_reg_ralue_trap_action trap_action,
7950 				u16 trap_id, u32 adjacency_index, u16 ecmp_size)
7951 {
7952 	mlxsw_reg_ralue_action_type_set(payload,
7953 					MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
7954 	mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7955 	mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7956 	mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
7957 	mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
7958 }
7959 
7960 static inline void
mlxsw_reg_ralue_act_local_pack(char * payload,enum mlxsw_reg_ralue_trap_action trap_action,u16 trap_id,u16 local_erif)7961 mlxsw_reg_ralue_act_local_pack(char *payload,
7962 			       enum mlxsw_reg_ralue_trap_action trap_action,
7963 			       u16 trap_id, u16 local_erif)
7964 {
7965 	mlxsw_reg_ralue_action_type_set(payload,
7966 					MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
7967 	mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7968 	mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7969 	mlxsw_reg_ralue_local_erif_set(payload, local_erif);
7970 }
7971 
7972 static inline void
mlxsw_reg_ralue_act_ip2me_pack(char * payload)7973 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
7974 {
7975 	mlxsw_reg_ralue_action_type_set(payload,
7976 					MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7977 }
7978 
7979 static inline void
mlxsw_reg_ralue_act_ip2me_tun_pack(char * payload,u32 tunnel_ptr)7980 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
7981 {
7982 	mlxsw_reg_ralue_action_type_set(payload,
7983 					MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7984 	mlxsw_reg_ralue_ip2me_v_set(payload, 1);
7985 	mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
7986 }
7987 
7988 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
7989  * ----------------------------------------------------------
7990  * The RAUHT register is used to configure and query the Unicast Host table in
7991  * devices that implement the Algorithmic LPM.
7992  */
7993 #define MLXSW_REG_RAUHT_ID 0x8014
7994 #define MLXSW_REG_RAUHT_LEN 0x74
7995 
7996 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
7997 
7998 enum mlxsw_reg_rauht_type {
7999 	MLXSW_REG_RAUHT_TYPE_IPV4,
8000 	MLXSW_REG_RAUHT_TYPE_IPV6,
8001 };
8002 
8003 /* reg_rauht_type
8004  * Access: Index
8005  */
8006 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
8007 
8008 enum mlxsw_reg_rauht_op {
8009 	MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
8010 	/* Read operation */
8011 	MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
8012 	/* Clear on read operation. Used to read entry and clear
8013 	 * activity bit.
8014 	 */
8015 	MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
8016 	/* Add. Used to write a new entry to the table. All R/W fields are
8017 	 * relevant for new entry. Activity bit is set for new entries.
8018 	 */
8019 	MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
8020 	/* Update action. Used to update an existing route entry and
8021 	 * only update the following fields:
8022 	 * trap_action, trap_id, mac, counter_set_type, counter_index
8023 	 */
8024 	MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
8025 	/* Clear activity. A bit is cleared for the entry. */
8026 	MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
8027 	/* Delete entry */
8028 	MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
8029 	/* Delete all host entries on a RIF. In this command, dip
8030 	 * field is reserved.
8031 	 */
8032 };
8033 
8034 /* reg_rauht_op
8035  * Access: OP
8036  */
8037 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
8038 
8039 /* reg_rauht_a
8040  * Activity. Set for new entries. Set if a packet lookup has hit on
8041  * the specific entry.
8042  * To clear the a bit, use "clear activity" op.
8043  * Enabled by activity_dis in RGCR
8044  * Access: RO
8045  */
8046 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
8047 
8048 /* reg_rauht_rif
8049  * Router Interface
8050  * Access: Index
8051  */
8052 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
8053 
8054 /* reg_rauht_dip*
8055  * Destination address.
8056  * Access: Index
8057  */
8058 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
8059 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
8060 
8061 enum mlxsw_reg_rauht_trap_action {
8062 	MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
8063 	MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
8064 	MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
8065 	MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
8066 	MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
8067 };
8068 
8069 /* reg_rauht_trap_action
8070  * Access: RW
8071  */
8072 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
8073 
8074 enum mlxsw_reg_rauht_trap_id {
8075 	MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
8076 	MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
8077 };
8078 
8079 /* reg_rauht_trap_id
8080  * Trap ID to be reported to CPU.
8081  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
8082  * For trap_action of NOP, MIRROR and DISCARD_ERROR,
8083  * trap_id is reserved.
8084  * Access: RW
8085  */
8086 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
8087 
8088 /* reg_rauht_counter_set_type
8089  * Counter set type for flow counters
8090  * Access: RW
8091  */
8092 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
8093 
8094 /* reg_rauht_counter_index
8095  * Counter index for flow counters
8096  * Access: RW
8097  */
8098 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
8099 
8100 /* reg_rauht_mac
8101  * MAC address.
8102  * Access: RW
8103  */
8104 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
8105 
mlxsw_reg_rauht_pack(char * payload,enum mlxsw_reg_rauht_op op,u16 rif,const char * mac)8106 static inline void mlxsw_reg_rauht_pack(char *payload,
8107 					enum mlxsw_reg_rauht_op op, u16 rif,
8108 					const char *mac)
8109 {
8110 	MLXSW_REG_ZERO(rauht, payload);
8111 	mlxsw_reg_rauht_op_set(payload, op);
8112 	mlxsw_reg_rauht_rif_set(payload, rif);
8113 	mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
8114 }
8115 
mlxsw_reg_rauht_pack4(char * payload,enum mlxsw_reg_rauht_op op,u16 rif,const char * mac,u32 dip)8116 static inline void mlxsw_reg_rauht_pack4(char *payload,
8117 					 enum mlxsw_reg_rauht_op op, u16 rif,
8118 					 const char *mac, u32 dip)
8119 {
8120 	mlxsw_reg_rauht_pack(payload, op, rif, mac);
8121 	mlxsw_reg_rauht_dip4_set(payload, dip);
8122 }
8123 
mlxsw_reg_rauht_pack6(char * payload,enum mlxsw_reg_rauht_op op,u16 rif,const char * mac,const char * dip)8124 static inline void mlxsw_reg_rauht_pack6(char *payload,
8125 					 enum mlxsw_reg_rauht_op op, u16 rif,
8126 					 const char *mac, const char *dip)
8127 {
8128 	mlxsw_reg_rauht_pack(payload, op, rif, mac);
8129 	mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
8130 	mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
8131 }
8132 
mlxsw_reg_rauht_pack_counter(char * payload,u64 counter_index)8133 static inline void mlxsw_reg_rauht_pack_counter(char *payload,
8134 						u64 counter_index)
8135 {
8136 	mlxsw_reg_rauht_counter_index_set(payload, counter_index);
8137 	mlxsw_reg_rauht_counter_set_type_set(payload,
8138 					     MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
8139 }
8140 
8141 /* RALEU - Router Algorithmic LPM ECMP Update Register
8142  * ---------------------------------------------------
8143  * The register enables updating the ECMP section in the action for multiple
8144  * LPM Unicast entries in a single operation. The update is executed to
8145  * all entries of a {virtual router, protocol} tuple using the same ECMP group.
8146  */
8147 #define MLXSW_REG_RALEU_ID 0x8015
8148 #define MLXSW_REG_RALEU_LEN 0x28
8149 
8150 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
8151 
8152 /* reg_raleu_protocol
8153  * Protocol.
8154  * Access: Index
8155  */
8156 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
8157 
8158 /* reg_raleu_virtual_router
8159  * Virtual Router ID
8160  * Range is 0..cap_max_virtual_routers-1
8161  * Access: Index
8162  */
8163 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
8164 
8165 /* reg_raleu_adjacency_index
8166  * Adjacency Index used for matching on the existing entries.
8167  * Access: Index
8168  */
8169 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
8170 
8171 /* reg_raleu_ecmp_size
8172  * ECMP Size used for matching on the existing entries.
8173  * Access: Index
8174  */
8175 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
8176 
8177 /* reg_raleu_new_adjacency_index
8178  * New Adjacency Index.
8179  * Access: WO
8180  */
8181 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
8182 
8183 /* reg_raleu_new_ecmp_size
8184  * New ECMP Size.
8185  * Access: WO
8186  */
8187 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
8188 
mlxsw_reg_raleu_pack(char * payload,enum mlxsw_reg_ralxx_protocol protocol,u16 virtual_router,u32 adjacency_index,u16 ecmp_size,u32 new_adjacency_index,u16 new_ecmp_size)8189 static inline void mlxsw_reg_raleu_pack(char *payload,
8190 					enum mlxsw_reg_ralxx_protocol protocol,
8191 					u16 virtual_router,
8192 					u32 adjacency_index, u16 ecmp_size,
8193 					u32 new_adjacency_index,
8194 					u16 new_ecmp_size)
8195 {
8196 	MLXSW_REG_ZERO(raleu, payload);
8197 	mlxsw_reg_raleu_protocol_set(payload, protocol);
8198 	mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
8199 	mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
8200 	mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
8201 	mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
8202 	mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
8203 }
8204 
8205 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
8206  * ----------------------------------------------------------------
8207  * The RAUHTD register allows dumping entries from the Router Unicast Host
8208  * Table. For a given session an entry is dumped no more than one time. The
8209  * first RAUHTD access after reset is a new session. A session ends when the
8210  * num_rec response is smaller than num_rec request or for IPv4 when the
8211  * num_entries is smaller than 4. The clear activity affect the current session
8212  * or the last session if a new session has not started.
8213  */
8214 #define MLXSW_REG_RAUHTD_ID 0x8018
8215 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
8216 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
8217 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
8218 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
8219 		MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
8220 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
8221 
8222 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
8223 
8224 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
8225 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
8226 
8227 /* reg_rauhtd_filter_fields
8228  * if a bit is '0' then the relevant field is ignored and dump is done
8229  * regardless of the field value
8230  * Bit0 - filter by activity: entry_a
8231  * Bit3 - filter by entry rip: entry_rif
8232  * Access: Index
8233  */
8234 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
8235 
8236 enum mlxsw_reg_rauhtd_op {
8237 	MLXSW_REG_RAUHTD_OP_DUMP,
8238 	MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
8239 };
8240 
8241 /* reg_rauhtd_op
8242  * Access: OP
8243  */
8244 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
8245 
8246 /* reg_rauhtd_num_rec
8247  * At request: number of records requested
8248  * At response: number of records dumped
8249  * For IPv4, each record has 4 entries at request and up to 4 entries
8250  * at response
8251  * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
8252  * Access: Index
8253  */
8254 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
8255 
8256 /* reg_rauhtd_entry_a
8257  * Dump only if activity has value of entry_a
8258  * Reserved if filter_fields bit0 is '0'
8259  * Access: Index
8260  */
8261 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
8262 
8263 enum mlxsw_reg_rauhtd_type {
8264 	MLXSW_REG_RAUHTD_TYPE_IPV4,
8265 	MLXSW_REG_RAUHTD_TYPE_IPV6,
8266 };
8267 
8268 /* reg_rauhtd_type
8269  * Dump only if record type is:
8270  * 0 - IPv4
8271  * 1 - IPv6
8272  * Access: Index
8273  */
8274 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
8275 
8276 /* reg_rauhtd_entry_rif
8277  * Dump only if RIF has value of entry_rif
8278  * Reserved if filter_fields bit3 is '0'
8279  * Access: Index
8280  */
8281 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
8282 
mlxsw_reg_rauhtd_pack(char * payload,enum mlxsw_reg_rauhtd_type type)8283 static inline void mlxsw_reg_rauhtd_pack(char *payload,
8284 					 enum mlxsw_reg_rauhtd_type type)
8285 {
8286 	MLXSW_REG_ZERO(rauhtd, payload);
8287 	mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
8288 	mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
8289 	mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
8290 	mlxsw_reg_rauhtd_entry_a_set(payload, 1);
8291 	mlxsw_reg_rauhtd_type_set(payload, type);
8292 }
8293 
8294 /* reg_rauhtd_ipv4_rec_num_entries
8295  * Number of valid entries in this record:
8296  * 0 - 1 valid entry
8297  * 1 - 2 valid entries
8298  * 2 - 3 valid entries
8299  * 3 - 4 valid entries
8300  * Access: RO
8301  */
8302 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
8303 		     MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
8304 		     MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
8305 
8306 /* reg_rauhtd_rec_type
8307  * Record type.
8308  * 0 - IPv4
8309  * 1 - IPv6
8310  * Access: RO
8311  */
8312 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
8313 		     MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
8314 
8315 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
8316 
8317 /* reg_rauhtd_ipv4_ent_a
8318  * Activity. Set for new entries. Set if a packet lookup has hit on the
8319  * specific entry.
8320  * Access: RO
8321  */
8322 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
8323 		     MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
8324 
8325 /* reg_rauhtd_ipv4_ent_rif
8326  * Router interface.
8327  * Access: RO
8328  */
8329 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8330 		     16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
8331 
8332 /* reg_rauhtd_ipv4_ent_dip
8333  * Destination IPv4 address.
8334  * Access: RO
8335  */
8336 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8337 		     32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
8338 
8339 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
8340 
8341 /* reg_rauhtd_ipv6_ent_a
8342  * Activity. Set for new entries. Set if a packet lookup has hit on the
8343  * specific entry.
8344  * Access: RO
8345  */
8346 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
8347 		     MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
8348 
8349 /* reg_rauhtd_ipv6_ent_rif
8350  * Router interface.
8351  * Access: RO
8352  */
8353 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8354 		     16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
8355 
8356 /* reg_rauhtd_ipv6_ent_dip
8357  * Destination IPv6 address.
8358  * Access: RO
8359  */
8360 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
8361 		       16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
8362 
mlxsw_reg_rauhtd_ent_ipv4_unpack(char * payload,int ent_index,u16 * p_rif,u32 * p_dip)8363 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
8364 						    int ent_index, u16 *p_rif,
8365 						    u32 *p_dip)
8366 {
8367 	*p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
8368 	*p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
8369 }
8370 
mlxsw_reg_rauhtd_ent_ipv6_unpack(char * payload,int rec_index,u16 * p_rif,char * p_dip)8371 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
8372 						    int rec_index, u16 *p_rif,
8373 						    char *p_dip)
8374 {
8375 	*p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
8376 	mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
8377 }
8378 
8379 /* RTDP - Routing Tunnel Decap Properties Register
8380  * -----------------------------------------------
8381  * The RTDP register is used for configuring the tunnel decap properties of NVE
8382  * and IPinIP.
8383  */
8384 #define MLXSW_REG_RTDP_ID 0x8020
8385 #define MLXSW_REG_RTDP_LEN 0x44
8386 
8387 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
8388 
8389 enum mlxsw_reg_rtdp_type {
8390 	MLXSW_REG_RTDP_TYPE_NVE,
8391 	MLXSW_REG_RTDP_TYPE_IPIP,
8392 };
8393 
8394 /* reg_rtdp_type
8395  * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type.
8396  * Access: RW
8397  */
8398 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
8399 
8400 /* reg_rtdp_tunnel_index
8401  * Index to the Decap entry.
8402  * For Spectrum, Index to KVD Linear.
8403  * Access: Index
8404  */
8405 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
8406 
8407 /* reg_rtdp_egress_router_interface
8408  * Underlay egress router interface.
8409  * Valid range is from 0 to cap_max_router_interfaces - 1
8410  * Access: RW
8411  */
8412 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
8413 
8414 /* IPinIP */
8415 
8416 /* reg_rtdp_ipip_irif
8417  * Ingress Router Interface for the overlay router
8418  * Access: RW
8419  */
8420 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
8421 
8422 enum mlxsw_reg_rtdp_ipip_sip_check {
8423 	/* No sip checks. */
8424 	MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
8425 	/* Filter packet if underlay is not IPv4 or if underlay SIP does not
8426 	 * equal ipv4_usip.
8427 	 */
8428 	MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
8429 	/* Filter packet if underlay is not IPv6 or if underlay SIP does not
8430 	 * equal ipv6_usip.
8431 	 */
8432 	MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
8433 };
8434 
8435 /* reg_rtdp_ipip_sip_check
8436  * SIP check to perform. If decapsulation failed due to these configurations
8437  * then trap_id is IPIP_DECAP_ERROR.
8438  * Access: RW
8439  */
8440 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
8441 
8442 /* If set, allow decapsulation of IPinIP (without GRE). */
8443 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP	BIT(0)
8444 /* If set, allow decapsulation of IPinGREinIP without a key. */
8445 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE	BIT(1)
8446 /* If set, allow decapsulation of IPinGREinIP with a key. */
8447 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY	BIT(2)
8448 
8449 /* reg_rtdp_ipip_type_check
8450  * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to
8451  * these configurations then trap_id is IPIP_DECAP_ERROR.
8452  * Access: RW
8453  */
8454 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
8455 
8456 /* reg_rtdp_ipip_gre_key_check
8457  * Whether GRE key should be checked. When check is enabled:
8458  * - A packet received as IPinIP (without GRE) will always pass.
8459  * - A packet received as IPinGREinIP without a key will not pass the check.
8460  * - A packet received as IPinGREinIP with a key will pass the check only if the
8461  *   key in the packet is equal to expected_gre_key.
8462  * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR.
8463  * Access: RW
8464  */
8465 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
8466 
8467 /* reg_rtdp_ipip_ipv4_usip
8468  * Underlay IPv4 address for ipv4 source address check.
8469  * Reserved when sip_check is not '1'.
8470  * Access: RW
8471  */
8472 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
8473 
8474 /* reg_rtdp_ipip_ipv6_usip_ptr
8475  * This field is valid when sip_check is "sipv6 check explicitly". This is a
8476  * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index
8477  * is to the KVD linear.
8478  * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6.
8479  * Access: RW
8480  */
8481 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
8482 
8483 /* reg_rtdp_ipip_expected_gre_key
8484  * GRE key for checking.
8485  * Reserved when gre_key_check is '0'.
8486  * Access: RW
8487  */
8488 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
8489 
mlxsw_reg_rtdp_pack(char * payload,enum mlxsw_reg_rtdp_type type,u32 tunnel_index)8490 static inline void mlxsw_reg_rtdp_pack(char *payload,
8491 				       enum mlxsw_reg_rtdp_type type,
8492 				       u32 tunnel_index)
8493 {
8494 	MLXSW_REG_ZERO(rtdp, payload);
8495 	mlxsw_reg_rtdp_type_set(payload, type);
8496 	mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
8497 }
8498 
8499 static inline void
mlxsw_reg_rtdp_ipip_pack(char * payload,u16 irif,enum mlxsw_reg_rtdp_ipip_sip_check sip_check,unsigned int type_check,bool gre_key_check,u32 expected_gre_key)8500 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif,
8501 			 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
8502 			 unsigned int type_check, bool gre_key_check,
8503 			 u32 expected_gre_key)
8504 {
8505 	mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
8506 	mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
8507 	mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
8508 	mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
8509 	mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
8510 }
8511 
8512 static inline void
mlxsw_reg_rtdp_ipip4_pack(char * payload,u16 irif,enum mlxsw_reg_rtdp_ipip_sip_check sip_check,unsigned int type_check,bool gre_key_check,u32 ipv4_usip,u32 expected_gre_key)8513 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
8514 			  enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
8515 			  unsigned int type_check, bool gre_key_check,
8516 			  u32 ipv4_usip, u32 expected_gre_key)
8517 {
8518 	mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check,
8519 				 gre_key_check, expected_gre_key);
8520 	mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
8521 }
8522 
8523 static inline void
mlxsw_reg_rtdp_ipip6_pack(char * payload,u16 irif,enum mlxsw_reg_rtdp_ipip_sip_check sip_check,unsigned int type_check,bool gre_key_check,u32 ipv6_usip_ptr,u32 expected_gre_key)8524 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif,
8525 			  enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
8526 			  unsigned int type_check, bool gre_key_check,
8527 			  u32 ipv6_usip_ptr, u32 expected_gre_key)
8528 {
8529 	mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check,
8530 				 gre_key_check, expected_gre_key);
8531 	mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr);
8532 }
8533 
8534 /* RIPS - Router IP version Six Register
8535  * -------------------------------------
8536  * The RIPS register is used to store IPv6 addresses for use by the NVE and
8537  * IPinIP
8538  */
8539 #define MLXSW_REG_RIPS_ID 0x8021
8540 #define MLXSW_REG_RIPS_LEN 0x14
8541 
8542 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN);
8543 
8544 /* reg_rips_index
8545  * Index to IPv6 address.
8546  * For Spectrum, the index is to the KVD linear.
8547  * Access: Index
8548  */
8549 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24);
8550 
8551 /* reg_rips_ipv6
8552  * IPv6 address
8553  * Access: RW
8554  */
8555 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16);
8556 
mlxsw_reg_rips_pack(char * payload,u32 index,const struct in6_addr * ipv6)8557 static inline void mlxsw_reg_rips_pack(char *payload, u32 index,
8558 				       const struct in6_addr *ipv6)
8559 {
8560 	MLXSW_REG_ZERO(rips, payload);
8561 	mlxsw_reg_rips_index_set(payload, index);
8562 	mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6);
8563 }
8564 
8565 /* RATRAD - Router Adjacency Table Activity Dump Register
8566  * ------------------------------------------------------
8567  * The RATRAD register is used to dump and optionally clear activity bits of
8568  * router adjacency table entries.
8569  */
8570 #define MLXSW_REG_RATRAD_ID 0x8022
8571 #define MLXSW_REG_RATRAD_LEN 0x210
8572 
8573 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN);
8574 
8575 enum {
8576 	/* Read activity */
8577 	MLXSW_REG_RATRAD_OP_READ_ACTIVITY,
8578 	/* Read and clear activity */
8579 	MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY,
8580 };
8581 
8582 /* reg_ratrad_op
8583  * Access: Operation
8584  */
8585 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2);
8586 
8587 /* reg_ratrad_ecmp_size
8588  * ecmp_size is the amount of sequential entries from adjacency_index. Valid
8589  * ranges:
8590  * Spectrum-1: 32-64, 512, 1024, 2048, 4096
8591  * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096
8592  * Access: Index
8593  */
8594 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13);
8595 
8596 /* reg_ratrad_adjacency_index
8597  * Index into the adjacency table.
8598  * Access: Index
8599  */
8600 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24);
8601 
8602 /* reg_ratrad_activity_vector
8603  * Activity bit per adjacency index.
8604  * Bits higher than ecmp_size are reserved.
8605  * Access: RO
8606  */
8607 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1);
8608 
mlxsw_reg_ratrad_pack(char * payload,u32 adjacency_index,u16 ecmp_size)8609 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index,
8610 					 u16 ecmp_size)
8611 {
8612 	MLXSW_REG_ZERO(ratrad, payload);
8613 	mlxsw_reg_ratrad_op_set(payload,
8614 				MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY);
8615 	mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size);
8616 	mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index);
8617 }
8618 
8619 /* RIGR-V2 - Router Interface Group Register Version 2
8620  * ---------------------------------------------------
8621  * The RIGR_V2 register is used to add, remove and query egress interface list
8622  * of a multicast forwarding entry.
8623  */
8624 #define MLXSW_REG_RIGR2_ID 0x8023
8625 #define MLXSW_REG_RIGR2_LEN 0xB0
8626 
8627 #define MLXSW_REG_RIGR2_MAX_ERIFS 32
8628 
8629 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
8630 
8631 /* reg_rigr2_rigr_index
8632  * KVD Linear index.
8633  * Access: Index
8634  */
8635 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
8636 
8637 /* reg_rigr2_vnext
8638  * Next RIGR Index is valid.
8639  * Access: RW
8640  */
8641 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
8642 
8643 /* reg_rigr2_next_rigr_index
8644  * Next RIGR Index. The index is to the KVD linear.
8645  * Reserved when vnxet = '0'.
8646  * Access: RW
8647  */
8648 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
8649 
8650 /* reg_rigr2_vrmid
8651  * RMID Index is valid.
8652  * Access: RW
8653  */
8654 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
8655 
8656 /* reg_rigr2_rmid_index
8657  * RMID Index.
8658  * Range 0 .. max_mid - 1
8659  * Reserved when vrmid = '0'.
8660  * The index is to the Port Group Table (PGT)
8661  * Access: RW
8662  */
8663 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
8664 
8665 /* reg_rigr2_erif_entry_v
8666  * Egress Router Interface is valid.
8667  * Note that low-entries must be set if high-entries are set. For
8668  * example: if erif_entry[2].v is set then erif_entry[1].v and
8669  * erif_entry[0].v must be set.
8670  * Index can be from 0 to cap_mc_erif_list_entries-1
8671  * Access: RW
8672  */
8673 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
8674 
8675 /* reg_rigr2_erif_entry_erif
8676  * Egress Router Interface.
8677  * Valid range is from 0 to cap_max_router_interfaces - 1
8678  * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1
8679  * Access: RW
8680  */
8681 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
8682 
mlxsw_reg_rigr2_pack(char * payload,u32 rigr_index,bool vnext,u32 next_rigr_index)8683 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
8684 					bool vnext, u32 next_rigr_index)
8685 {
8686 	MLXSW_REG_ZERO(rigr2, payload);
8687 	mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
8688 	mlxsw_reg_rigr2_vnext_set(payload, vnext);
8689 	mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
8690 	mlxsw_reg_rigr2_vrmid_set(payload, 0);
8691 	mlxsw_reg_rigr2_rmid_index_set(payload, 0);
8692 }
8693 
mlxsw_reg_rigr2_erif_entry_pack(char * payload,int index,bool v,u16 erif)8694 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
8695 						   bool v, u16 erif)
8696 {
8697 	mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
8698 	mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
8699 }
8700 
8701 /* RECR-V2 - Router ECMP Configuration Version 2 Register
8702  * ------------------------------------------------------
8703  */
8704 #define MLXSW_REG_RECR2_ID 0x8025
8705 #define MLXSW_REG_RECR2_LEN 0x38
8706 
8707 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
8708 
8709 /* reg_recr2_pp
8710  * Per-port configuration
8711  * Access: Index
8712  */
8713 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
8714 
8715 /* reg_recr2_sh
8716  * Symmetric hash
8717  * Access: RW
8718  */
8719 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
8720 
8721 /* reg_recr2_seed
8722  * Seed
8723  * Access: RW
8724  */
8725 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
8726 
8727 enum {
8728 	/* Enable IPv4 fields if packet is not TCP and not UDP */
8729 	MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP	= 3,
8730 	/* Enable IPv4 fields if packet is TCP or UDP */
8731 	MLXSW_REG_RECR2_IPV4_EN_TCP_UDP		= 4,
8732 	/* Enable IPv6 fields if packet is not TCP and not UDP */
8733 	MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP	= 5,
8734 	/* Enable IPv6 fields if packet is TCP or UDP */
8735 	MLXSW_REG_RECR2_IPV6_EN_TCP_UDP		= 6,
8736 	/* Enable TCP/UDP header fields if packet is IPv4 */
8737 	MLXSW_REG_RECR2_TCP_UDP_EN_IPV4		= 7,
8738 	/* Enable TCP/UDP header fields if packet is IPv6 */
8739 	MLXSW_REG_RECR2_TCP_UDP_EN_IPV6		= 8,
8740 
8741 	__MLXSW_REG_RECR2_HEADER_CNT,
8742 };
8743 
8744 /* reg_recr2_outer_header_enables
8745  * Bit mask where each bit enables a specific layer to be included in
8746  * the hash calculation.
8747  * Access: RW
8748  */
8749 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
8750 
8751 enum {
8752 	/* IPv4 Source IP */
8753 	MLXSW_REG_RECR2_IPV4_SIP0			= 9,
8754 	MLXSW_REG_RECR2_IPV4_SIP3			= 12,
8755 	/* IPv4 Destination IP */
8756 	MLXSW_REG_RECR2_IPV4_DIP0			= 13,
8757 	MLXSW_REG_RECR2_IPV4_DIP3			= 16,
8758 	/* IP Protocol */
8759 	MLXSW_REG_RECR2_IPV4_PROTOCOL			= 17,
8760 	/* IPv6 Source IP */
8761 	MLXSW_REG_RECR2_IPV6_SIP0_7			= 21,
8762 	MLXSW_REG_RECR2_IPV6_SIP8			= 29,
8763 	MLXSW_REG_RECR2_IPV6_SIP15			= 36,
8764 	/* IPv6 Destination IP */
8765 	MLXSW_REG_RECR2_IPV6_DIP0_7			= 37,
8766 	MLXSW_REG_RECR2_IPV6_DIP8			= 45,
8767 	MLXSW_REG_RECR2_IPV6_DIP15			= 52,
8768 	/* IPv6 Next Header */
8769 	MLXSW_REG_RECR2_IPV6_NEXT_HEADER		= 53,
8770 	/* IPv6 Flow Label */
8771 	MLXSW_REG_RECR2_IPV6_FLOW_LABEL			= 57,
8772 	/* TCP/UDP Source Port */
8773 	MLXSW_REG_RECR2_TCP_UDP_SPORT			= 74,
8774 	/* TCP/UDP Destination Port */
8775 	MLXSW_REG_RECR2_TCP_UDP_DPORT			= 75,
8776 
8777 	__MLXSW_REG_RECR2_FIELD_CNT,
8778 };
8779 
8780 /* reg_recr2_outer_header_fields_enable
8781  * Packet fields to enable for ECMP hash subject to outer_header_enable.
8782  * Access: RW
8783  */
8784 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
8785 
8786 /* reg_recr2_inner_header_enables
8787  * Bit mask where each bit enables a specific inner layer to be included in the
8788  * hash calculation. Same values as reg_recr2_outer_header_enables.
8789  * Access: RW
8790  */
8791 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1);
8792 
8793 enum {
8794 	/* Inner IPv4 Source IP */
8795 	MLXSW_REG_RECR2_INNER_IPV4_SIP0			= 3,
8796 	MLXSW_REG_RECR2_INNER_IPV4_SIP3			= 6,
8797 	/* Inner IPv4 Destination IP */
8798 	MLXSW_REG_RECR2_INNER_IPV4_DIP0			= 7,
8799 	MLXSW_REG_RECR2_INNER_IPV4_DIP3			= 10,
8800 	/* Inner IP Protocol */
8801 	MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL		= 11,
8802 	/* Inner IPv6 Source IP */
8803 	MLXSW_REG_RECR2_INNER_IPV6_SIP0_7		= 12,
8804 	MLXSW_REG_RECR2_INNER_IPV6_SIP8			= 20,
8805 	MLXSW_REG_RECR2_INNER_IPV6_SIP15		= 27,
8806 	/* Inner IPv6 Destination IP */
8807 	MLXSW_REG_RECR2_INNER_IPV6_DIP0_7		= 28,
8808 	MLXSW_REG_RECR2_INNER_IPV6_DIP8			= 36,
8809 	MLXSW_REG_RECR2_INNER_IPV6_DIP15		= 43,
8810 	/* Inner IPv6 Next Header */
8811 	MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER		= 44,
8812 	/* Inner IPv6 Flow Label */
8813 	MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL		= 45,
8814 	/* Inner TCP/UDP Source Port */
8815 	MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT		= 46,
8816 	/* Inner TCP/UDP Destination Port */
8817 	MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT		= 47,
8818 
8819 	__MLXSW_REG_RECR2_INNER_FIELD_CNT,
8820 };
8821 
8822 /* reg_recr2_inner_header_fields_enable
8823  * Inner packet fields to enable for ECMP hash subject to inner_header_enables.
8824  * Access: RW
8825  */
8826 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1);
8827 
mlxsw_reg_recr2_pack(char * payload,u32 seed)8828 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
8829 {
8830 	MLXSW_REG_ZERO(recr2, payload);
8831 	mlxsw_reg_recr2_pp_set(payload, false);
8832 	mlxsw_reg_recr2_sh_set(payload, true);
8833 	mlxsw_reg_recr2_seed_set(payload, seed);
8834 }
8835 
8836 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register
8837  * --------------------------------------------------------------
8838  * The RMFT_V2 register is used to configure and query the multicast table.
8839  */
8840 #define MLXSW_REG_RMFT2_ID 0x8027
8841 #define MLXSW_REG_RMFT2_LEN 0x174
8842 
8843 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
8844 
8845 /* reg_rmft2_v
8846  * Valid
8847  * Access: RW
8848  */
8849 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
8850 
8851 enum mlxsw_reg_rmft2_type {
8852 	MLXSW_REG_RMFT2_TYPE_IPV4,
8853 	MLXSW_REG_RMFT2_TYPE_IPV6
8854 };
8855 
8856 /* reg_rmft2_type
8857  * Access: Index
8858  */
8859 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
8860 
8861 enum mlxsw_sp_reg_rmft2_op {
8862 	/* For Write:
8863 	 * Write operation. Used to write a new entry to the table. All RW
8864 	 * fields are relevant for new entry. Activity bit is set for new
8865 	 * entries - Note write with v (Valid) 0 will delete the entry.
8866 	 * For Query:
8867 	 * Read operation
8868 	 */
8869 	MLXSW_REG_RMFT2_OP_READ_WRITE,
8870 };
8871 
8872 /* reg_rmft2_op
8873  * Operation.
8874  * Access: OP
8875  */
8876 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
8877 
8878 /* reg_rmft2_a
8879  * Activity. Set for new entries. Set if a packet lookup has hit on the specific
8880  * entry.
8881  * Access: RO
8882  */
8883 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
8884 
8885 /* reg_rmft2_offset
8886  * Offset within the multicast forwarding table to write to.
8887  * Access: Index
8888  */
8889 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
8890 
8891 /* reg_rmft2_virtual_router
8892  * Virtual Router ID. Range from 0..cap_max_virtual_routers-1
8893  * Access: RW
8894  */
8895 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
8896 
8897 enum mlxsw_reg_rmft2_irif_mask {
8898 	MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
8899 	MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
8900 };
8901 
8902 /* reg_rmft2_irif_mask
8903  * Ingress RIF mask.
8904  * Access: RW
8905  */
8906 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
8907 
8908 /* reg_rmft2_irif
8909  * Ingress RIF index.
8910  * Access: RW
8911  */
8912 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
8913 
8914 /* reg_rmft2_dip{4,6}
8915  * Destination IPv4/6 address
8916  * Access: RW
8917  */
8918 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
8919 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
8920 
8921 /* reg_rmft2_dip{4,6}_mask
8922  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
8923  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
8924  * Access: RW
8925  */
8926 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
8927 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
8928 
8929 /* reg_rmft2_sip{4,6}
8930  * Source IPv4/6 address
8931  * Access: RW
8932  */
8933 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
8934 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
8935 
8936 /* reg_rmft2_sip{4,6}_mask
8937  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
8938  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
8939  * Access: RW
8940  */
8941 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
8942 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
8943 
8944 /* reg_rmft2_flexible_action_set
8945  * ACL action set. The only supported action types in this field and in any
8946  * action-set pointed from here are as follows:
8947  * 00h: ACTION_NULL
8948  * 01h: ACTION_MAC_TTL, only TTL configuration is supported.
8949  * 03h: ACTION_TRAP
8950  * 06h: ACTION_QOS
8951  * 08h: ACTION_POLICING_MONITORING
8952  * 10h: ACTION_ROUTER_MC
8953  * Access: RW
8954  */
8955 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
8956 	       MLXSW_REG_FLEX_ACTION_SET_LEN);
8957 
8958 static inline void
mlxsw_reg_rmft2_common_pack(char * payload,bool v,u16 offset,u16 virtual_router,enum mlxsw_reg_rmft2_irif_mask irif_mask,u16 irif,const char * flex_action_set)8959 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
8960 			    u16 virtual_router,
8961 			    enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8962 			    const char *flex_action_set)
8963 {
8964 	MLXSW_REG_ZERO(rmft2, payload);
8965 	mlxsw_reg_rmft2_v_set(payload, v);
8966 	mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
8967 	mlxsw_reg_rmft2_offset_set(payload, offset);
8968 	mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
8969 	mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
8970 	mlxsw_reg_rmft2_irif_set(payload, irif);
8971 	if (flex_action_set)
8972 		mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
8973 							      flex_action_set);
8974 }
8975 
8976 static inline void
mlxsw_reg_rmft2_ipv4_pack(char * payload,bool v,u16 offset,u16 virtual_router,enum mlxsw_reg_rmft2_irif_mask irif_mask,u16 irif,u32 dip4,u32 dip4_mask,u32 sip4,u32 sip4_mask,const char * flexible_action_set)8977 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
8978 			  enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8979 			  u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
8980 			  const char *flexible_action_set)
8981 {
8982 	mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
8983 				    irif_mask, irif, flexible_action_set);
8984 	mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
8985 	mlxsw_reg_rmft2_dip4_set(payload, dip4);
8986 	mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
8987 	mlxsw_reg_rmft2_sip4_set(payload, sip4);
8988 	mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
8989 }
8990 
8991 static inline void
mlxsw_reg_rmft2_ipv6_pack(char * payload,bool v,u16 offset,u16 virtual_router,enum mlxsw_reg_rmft2_irif_mask irif_mask,u16 irif,struct in6_addr dip6,struct in6_addr dip6_mask,struct in6_addr sip6,struct in6_addr sip6_mask,const char * flexible_action_set)8992 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
8993 			  enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8994 			  struct in6_addr dip6, struct in6_addr dip6_mask,
8995 			  struct in6_addr sip6, struct in6_addr sip6_mask,
8996 			  const char *flexible_action_set)
8997 {
8998 	mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
8999 				    irif_mask, irif, flexible_action_set);
9000 	mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
9001 	mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
9002 	mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
9003 	mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
9004 	mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
9005 }
9006 
9007 /* REIV - Router Egress Interface to VID Register
9008  * ----------------------------------------------
9009  * The REIV register maps {eRIF, egress_port} -> VID.
9010  * This mapping is done at the egress, after the ACLs.
9011  * This mapping always takes effect after router, regardless of cast
9012  * (for unicast/multicast/port-base multicast), regardless of eRIF type and
9013  * regardless of bridge decisions (e.g. SFD for unicast or SMPE).
9014  * Reserved when the RIF is a loopback RIF.
9015  *
9016  * Note: Reserved when legacy bridge model is used.
9017  */
9018 #define MLXSW_REG_REIV_ID 0x8034
9019 #define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */
9020 #define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */
9021 #define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */
9022 #define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN +	\
9023 			    MLXSW_REG_REIV_REC_LEN *	\
9024 			    MLXSW_REG_REIV_REC_MAX_COUNT)
9025 
9026 MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN);
9027 
9028 /* reg_reiv_port_page
9029  * Port page - elport_record[0] is 256*port_page.
9030  * Access: Index
9031  */
9032 MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4);
9033 
9034 /* reg_reiv_erif
9035  * Egress RIF.
9036  * Range is 0..cap_max_router_interfaces-1.
9037  * Access: Index
9038  */
9039 MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16);
9040 
9041 /* reg_reiv_rec_update
9042  * Update enable (when write):
9043  * 0 - Do not update the entry.
9044  * 1 - Update the entry.
9045  * Access: OP
9046  */
9047 MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1,
9048 		     MLXSW_REG_REIV_REC_LEN, 0x00, false);
9049 
9050 /* reg_reiv_rec_evid
9051  * Egress VID.
9052  * Range is 0..4095.
9053  * Access: RW
9054  */
9055 MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12,
9056 		     MLXSW_REG_REIV_REC_LEN, 0x00, false);
9057 
mlxsw_reg_reiv_pack(char * payload,u8 port_page,u16 erif)9058 static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif)
9059 {
9060 	MLXSW_REG_ZERO(reiv, payload);
9061 	mlxsw_reg_reiv_port_page_set(payload, port_page);
9062 	mlxsw_reg_reiv_erif_set(payload, erif);
9063 }
9064 
9065 /* MFCR - Management Fan Control Register
9066  * --------------------------------------
9067  * This register controls the settings of the Fan Speed PWM mechanism.
9068  */
9069 #define MLXSW_REG_MFCR_ID 0x9001
9070 #define MLXSW_REG_MFCR_LEN 0x08
9071 
9072 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
9073 
9074 enum mlxsw_reg_mfcr_pwm_frequency {
9075 	MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
9076 	MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
9077 	MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
9078 	MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
9079 	MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
9080 	MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
9081 	MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
9082 	MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
9083 };
9084 
9085 /* reg_mfcr_pwm_frequency
9086  * Controls the frequency of the PWM signal.
9087  * Access: RW
9088  */
9089 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
9090 
9091 #define MLXSW_MFCR_TACHOS_MAX 10
9092 
9093 /* reg_mfcr_tacho_active
9094  * Indicates which of the tachometer is active (bit per tachometer).
9095  * Access: RO
9096  */
9097 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
9098 
9099 #define MLXSW_MFCR_PWMS_MAX 5
9100 
9101 /* reg_mfcr_pwm_active
9102  * Indicates which of the PWM control is active (bit per PWM).
9103  * Access: RO
9104  */
9105 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
9106 
9107 static inline void
mlxsw_reg_mfcr_pack(char * payload,enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)9108 mlxsw_reg_mfcr_pack(char *payload,
9109 		    enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
9110 {
9111 	MLXSW_REG_ZERO(mfcr, payload);
9112 	mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
9113 }
9114 
9115 static inline void
mlxsw_reg_mfcr_unpack(char * payload,enum mlxsw_reg_mfcr_pwm_frequency * p_pwm_frequency,u16 * p_tacho_active,u8 * p_pwm_active)9116 mlxsw_reg_mfcr_unpack(char *payload,
9117 		      enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
9118 		      u16 *p_tacho_active, u8 *p_pwm_active)
9119 {
9120 	*p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
9121 	*p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
9122 	*p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
9123 }
9124 
9125 /* MFSC - Management Fan Speed Control Register
9126  * --------------------------------------------
9127  * This register controls the settings of the Fan Speed PWM mechanism.
9128  */
9129 #define MLXSW_REG_MFSC_ID 0x9002
9130 #define MLXSW_REG_MFSC_LEN 0x08
9131 
9132 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
9133 
9134 /* reg_mfsc_pwm
9135  * Fan pwm to control / monitor.
9136  * Access: Index
9137  */
9138 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
9139 
9140 /* reg_mfsc_pwm_duty_cycle
9141  * Controls the duty cycle of the PWM. Value range from 0..255 to
9142  * represent duty cycle of 0%...100%.
9143  * Access: RW
9144  */
9145 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
9146 
mlxsw_reg_mfsc_pack(char * payload,u8 pwm,u8 pwm_duty_cycle)9147 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
9148 				       u8 pwm_duty_cycle)
9149 {
9150 	MLXSW_REG_ZERO(mfsc, payload);
9151 	mlxsw_reg_mfsc_pwm_set(payload, pwm);
9152 	mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
9153 }
9154 
9155 /* MFSM - Management Fan Speed Measurement
9156  * ---------------------------------------
9157  * This register controls the settings of the Tacho measurements and
9158  * enables reading the Tachometer measurements.
9159  */
9160 #define MLXSW_REG_MFSM_ID 0x9003
9161 #define MLXSW_REG_MFSM_LEN 0x08
9162 
9163 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
9164 
9165 /* reg_mfsm_tacho
9166  * Fan tachometer index.
9167  * Access: Index
9168  */
9169 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
9170 
9171 /* reg_mfsm_rpm
9172  * Fan speed (round per minute).
9173  * Access: RO
9174  */
9175 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
9176 
mlxsw_reg_mfsm_pack(char * payload,u8 tacho)9177 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
9178 {
9179 	MLXSW_REG_ZERO(mfsm, payload);
9180 	mlxsw_reg_mfsm_tacho_set(payload, tacho);
9181 }
9182 
9183 /* MFSL - Management Fan Speed Limit Register
9184  * ------------------------------------------
9185  * The Fan Speed Limit register is used to configure the fan speed
9186  * event / interrupt notification mechanism. Fan speed threshold are
9187  * defined for both under-speed and over-speed.
9188  */
9189 #define MLXSW_REG_MFSL_ID 0x9004
9190 #define MLXSW_REG_MFSL_LEN 0x0C
9191 
9192 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
9193 
9194 /* reg_mfsl_tacho
9195  * Fan tachometer index.
9196  * Access: Index
9197  */
9198 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
9199 
9200 /* reg_mfsl_tach_min
9201  * Tachometer minimum value (minimum RPM).
9202  * Access: RW
9203  */
9204 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
9205 
9206 /* reg_mfsl_tach_max
9207  * Tachometer maximum value (maximum RPM).
9208  * Access: RW
9209  */
9210 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
9211 
mlxsw_reg_mfsl_pack(char * payload,u8 tacho,u16 tach_min,u16 tach_max)9212 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
9213 				       u16 tach_min, u16 tach_max)
9214 {
9215 	MLXSW_REG_ZERO(mfsl, payload);
9216 	mlxsw_reg_mfsl_tacho_set(payload, tacho);
9217 	mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
9218 	mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
9219 }
9220 
mlxsw_reg_mfsl_unpack(char * payload,u8 tacho,u16 * p_tach_min,u16 * p_tach_max)9221 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
9222 					 u16 *p_tach_min, u16 *p_tach_max)
9223 {
9224 	if (p_tach_min)
9225 		*p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
9226 
9227 	if (p_tach_max)
9228 		*p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
9229 }
9230 
9231 /* FORE - Fan Out of Range Event Register
9232  * --------------------------------------
9233  * This register reports the status of the controlled fans compared to the
9234  * range defined by the MFSL register.
9235  */
9236 #define MLXSW_REG_FORE_ID 0x9007
9237 #define MLXSW_REG_FORE_LEN 0x0C
9238 
9239 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);
9240 
9241 /* fan_under_limit
9242  * Fan speed is below the low limit defined in MFSL register. Each bit relates
9243  * to a single tachometer and indicates the specific tachometer reading is
9244  * below the threshold.
9245  * Access: RO
9246  */
9247 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
9248 
mlxsw_reg_fore_unpack(char * payload,u8 tacho,bool * fault)9249 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,
9250 					 bool *fault)
9251 {
9252 	u16 limit;
9253 
9254 	if (fault) {
9255 		limit = mlxsw_reg_fore_fan_under_limit_get(payload);
9256 		*fault = limit & BIT(tacho);
9257 	}
9258 }
9259 
9260 /* MTCAP - Management Temperature Capabilities
9261  * -------------------------------------------
9262  * This register exposes the capabilities of the device and
9263  * system temperature sensing.
9264  */
9265 #define MLXSW_REG_MTCAP_ID 0x9009
9266 #define MLXSW_REG_MTCAP_LEN 0x08
9267 
9268 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
9269 
9270 /* reg_mtcap_sensor_count
9271  * Number of sensors supported by the device.
9272  * This includes the QSFP module sensors (if exists in the QSFP module).
9273  * Access: RO
9274  */
9275 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
9276 
9277 /* MTMP - Management Temperature
9278  * -----------------------------
9279  * This register controls the settings of the temperature measurements
9280  * and enables reading the temperature measurements. Note that temperature
9281  * is in 0.125 degrees Celsius.
9282  */
9283 #define MLXSW_REG_MTMP_ID 0x900A
9284 #define MLXSW_REG_MTMP_LEN 0x20
9285 
9286 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
9287 
9288 /* reg_mtmp_slot_index
9289  * Slot index (0: Main board).
9290  * Access: Index
9291  */
9292 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4);
9293 
9294 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64
9295 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256
9296 /* reg_mtmp_sensor_index
9297  * Sensors index to access.
9298  * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
9299  * (module 0 is mapped to sensor_index 64).
9300  * Access: Index
9301  */
9302 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
9303 
9304 /* Convert to milli degrees Celsius */
9305 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \
9306 					  ((v_) >= 0) ? ((v_) * 125) : \
9307 					  ((s16)((GENMASK(15, 0) + (v_) + 1) \
9308 					   * 125)); })
9309 
9310 /* reg_mtmp_max_operational_temperature
9311  * The highest temperature in the nominal operational range. Reading is in
9312  * 0.125 Celsius degrees units.
9313  * In case of module this is SFF critical temperature threshold.
9314  * Access: RO
9315  */
9316 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16);
9317 
9318 /* reg_mtmp_temperature
9319  * Temperature reading from the sensor. Reading is in 0.125 Celsius
9320  * degrees units.
9321  * Access: RO
9322  */
9323 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
9324 
9325 /* reg_mtmp_mte
9326  * Max Temperature Enable - enables measuring the max temperature on a sensor.
9327  * Access: RW
9328  */
9329 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
9330 
9331 /* reg_mtmp_mtr
9332  * Max Temperature Reset - clears the value of the max temperature register.
9333  * Access: WO
9334  */
9335 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
9336 
9337 /* reg_mtmp_max_temperature
9338  * The highest measured temperature from the sensor.
9339  * When the bit mte is cleared, the field max_temperature is reserved.
9340  * Access: RO
9341  */
9342 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
9343 
9344 /* reg_mtmp_tee
9345  * Temperature Event Enable.
9346  * 0 - Do not generate event
9347  * 1 - Generate event
9348  * 2 - Generate single event
9349  * Access: RW
9350  */
9351 
9352 enum mlxsw_reg_mtmp_tee {
9353 	MLXSW_REG_MTMP_TEE_NO_EVENT,
9354 	MLXSW_REG_MTMP_TEE_GENERATE_EVENT,
9355 	MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT,
9356 };
9357 
9358 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
9359 
9360 #define MLXSW_REG_MTMP_THRESH_HI 0x348	/* 105 Celsius */
9361 
9362 /* reg_mtmp_temperature_threshold_hi
9363  * High threshold for Temperature Warning Event. In 0.125 Celsius.
9364  * Access: RW
9365  */
9366 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
9367 
9368 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */
9369 /* reg_mtmp_temperature_threshold_lo
9370  * Low threshold for Temperature Warning Event. In 0.125 Celsius.
9371  * Access: RW
9372  */
9373 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
9374 
9375 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
9376 
9377 /* reg_mtmp_sensor_name
9378  * Sensor Name
9379  * Access: RO
9380  */
9381 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
9382 
mlxsw_reg_mtmp_pack(char * payload,u8 slot_index,u16 sensor_index,bool max_temp_enable,bool max_temp_reset)9383 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index,
9384 				       u16 sensor_index, bool max_temp_enable,
9385 				       bool max_temp_reset)
9386 {
9387 	MLXSW_REG_ZERO(mtmp, payload);
9388 	mlxsw_reg_mtmp_slot_index_set(payload, slot_index);
9389 	mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
9390 	mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
9391 	mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
9392 	mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
9393 						    MLXSW_REG_MTMP_THRESH_HI);
9394 }
9395 
mlxsw_reg_mtmp_unpack(char * payload,int * p_temp,int * p_max_temp,int * p_temp_hi,int * p_max_oper_temp,char * sensor_name)9396 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp,
9397 					 int *p_max_temp, int *p_temp_hi,
9398 					 int *p_max_oper_temp,
9399 					 char *sensor_name)
9400 {
9401 	s16 temp;
9402 
9403 	if (p_temp) {
9404 		temp = mlxsw_reg_mtmp_temperature_get(payload);
9405 		*p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9406 	}
9407 	if (p_max_temp) {
9408 		temp = mlxsw_reg_mtmp_max_temperature_get(payload);
9409 		*p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9410 	}
9411 	if (p_temp_hi) {
9412 		temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload);
9413 		*p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9414 	}
9415 	if (p_max_oper_temp) {
9416 		temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload);
9417 		*p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9418 	}
9419 	if (sensor_name)
9420 		mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
9421 }
9422 
9423 /* MTWE - Management Temperature Warning Event
9424  * -------------------------------------------
9425  * This register is used for over temperature warning.
9426  */
9427 #define MLXSW_REG_MTWE_ID 0x900B
9428 #define MLXSW_REG_MTWE_LEN 0x10
9429 
9430 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN);
9431 
9432 /* reg_mtwe_sensor_warning
9433  * Bit vector indicating which of the sensor reading is above threshold.
9434  * Address 00h bit31 is sensor_warning[127].
9435  * Address 0Ch bit0 is sensor_warning[0].
9436  * Access: RO
9437  */
9438 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1);
9439 
9440 /* MTBR - Management Temperature Bulk Register
9441  * -------------------------------------------
9442  * This register is used for bulk temperature reading.
9443  */
9444 #define MLXSW_REG_MTBR_ID 0x900F
9445 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */
9446 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */
9447 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */
9448 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN +	\
9449 			    MLXSW_REG_MTBR_REC_LEN *	\
9450 			    MLXSW_REG_MTBR_REC_MAX_COUNT)
9451 
9452 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);
9453 
9454 /* reg_mtbr_slot_index
9455  * Slot index (0: Main board).
9456  * Access: Index
9457  */
9458 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4);
9459 
9460 /* reg_mtbr_base_sensor_index
9461  * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors,
9462  * 64-127 are mapped to the SFP+/QSFP modules sequentially).
9463  * Access: Index
9464  */
9465 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
9466 
9467 /* reg_mtbr_num_rec
9468  * Request: Number of records to read
9469  * Response: Number of records read
9470  * See above description for more details.
9471  * Range 1..255
9472  * Access: RW
9473  */
9474 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
9475 
9476 /* reg_mtbr_rec_max_temp
9477  * The highest measured temperature from the sensor.
9478  * When the bit mte is cleared, the field max_temperature is reserved.
9479  * Access: RO
9480  */
9481 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
9482 		     16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
9483 
9484 /* reg_mtbr_rec_temp
9485  * Temperature reading from the sensor. Reading is in 0..125 Celsius
9486  * degrees units.
9487  * Access: RO
9488  */
9489 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
9490 		     MLXSW_REG_MTBR_REC_LEN, 0x00, false);
9491 
mlxsw_reg_mtbr_pack(char * payload,u8 slot_index,u16 base_sensor_index,u8 num_rec)9492 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index,
9493 				       u16 base_sensor_index, u8 num_rec)
9494 {
9495 	MLXSW_REG_ZERO(mtbr, payload);
9496 	mlxsw_reg_mtbr_slot_index_set(payload, slot_index);
9497 	mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);
9498 	mlxsw_reg_mtbr_num_rec_set(payload, num_rec);
9499 }
9500 
9501 /* Error codes from temperatute reading */
9502 enum mlxsw_reg_mtbr_temp_status {
9503 	MLXSW_REG_MTBR_NO_CONN		= 0x8000,
9504 	MLXSW_REG_MTBR_NO_TEMP_SENS	= 0x8001,
9505 	MLXSW_REG_MTBR_INDEX_NA		= 0x8002,
9506 	MLXSW_REG_MTBR_BAD_SENS_INFO	= 0x8003,
9507 };
9508 
9509 /* Base index for reading modules temperature */
9510 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64
9511 
mlxsw_reg_mtbr_temp_unpack(char * payload,int rec_ind,u16 * p_temp,u16 * p_max_temp)9512 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,
9513 					      u16 *p_temp, u16 *p_max_temp)
9514 {
9515 	if (p_temp)
9516 		*p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);
9517 	if (p_max_temp)
9518 		*p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);
9519 }
9520 
9521 /* MCIA - Management Cable Info Access
9522  * -----------------------------------
9523  * MCIA register is used to access the SFP+ and QSFP connector's EPROM.
9524  */
9525 
9526 #define MLXSW_REG_MCIA_ID 0x9014
9527 #define MLXSW_REG_MCIA_LEN 0x40
9528 
9529 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
9530 
9531 /* reg_mcia_l
9532  * Lock bit. Setting this bit will lock the access to the specific
9533  * cable. Used for updating a full page in a cable EPROM. Any access
9534  * other then subsequence writes will fail while the port is locked.
9535  * Access: RW
9536  */
9537 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
9538 
9539 /* reg_mcia_module
9540  * Module number.
9541  * Access: Index
9542  */
9543 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
9544 
9545 /* reg_mcia_slot_index
9546  * Slot index (0: Main board)
9547  * Access: Index
9548  */
9549 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4);
9550 
9551 enum {
9552 	MLXSW_REG_MCIA_STATUS_GOOD = 0,
9553 	/* No response from module's EEPROM. */
9554 	MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1,
9555 	/* Module type not supported by the device. */
9556 	MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2,
9557 	/* No module present indication. */
9558 	MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3,
9559 	/* Error occurred while trying to access module's EEPROM using I2C. */
9560 	MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9,
9561 	/* Module is disabled. */
9562 	MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16,
9563 };
9564 
9565 /* reg_mcia_status
9566  * Module status.
9567  * Access: RO
9568  */
9569 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
9570 
9571 /* reg_mcia_i2c_device_address
9572  * I2C device address.
9573  * Access: RW
9574  */
9575 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
9576 
9577 /* reg_mcia_page_number
9578  * Page number.
9579  * Access: RW
9580  */
9581 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
9582 
9583 /* reg_mcia_device_address
9584  * Device address.
9585  * Access: RW
9586  */
9587 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
9588 
9589 /* reg_mcia_bank_number
9590  * Bank number.
9591  * Access: Index
9592  */
9593 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8);
9594 
9595 /* reg_mcia_size
9596  * Number of bytes to read/write (up to 48 bytes).
9597  * Access: RW
9598  */
9599 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
9600 
9601 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH	256
9602 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH	128
9603 #define MLXSW_REG_MCIA_EEPROM_SIZE		48
9604 #define MLXSW_REG_MCIA_I2C_ADDR_LOW		0x50
9605 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH		0x51
9606 #define MLXSW_REG_MCIA_PAGE0_LO_OFF		0xa0
9607 #define MLXSW_REG_MCIA_TH_ITEM_SIZE		2
9608 #define MLXSW_REG_MCIA_TH_PAGE_NUM		3
9609 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM		2
9610 #define MLXSW_REG_MCIA_PAGE0_LO			0
9611 #define MLXSW_REG_MCIA_TH_PAGE_OFF		0x80
9612 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY	BIT(7)
9613 
9614 enum mlxsw_reg_mcia_eeprom_module_info_rev_id {
9615 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC	= 0x00,
9616 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436	= 0x01,
9617 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636	= 0x03,
9618 };
9619 
9620 enum mlxsw_reg_mcia_eeprom_module_info_id {
9621 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP	= 0x03,
9622 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP	= 0x0C,
9623 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS	= 0x0D,
9624 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28	= 0x11,
9625 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD	= 0x18,
9626 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP	= 0x19,
9627 };
9628 
9629 enum mlxsw_reg_mcia_eeprom_module_info {
9630 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,
9631 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,
9632 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID,
9633 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,
9634 };
9635 
9636 /* reg_mcia_eeprom
9637  * Bytes to read/write.
9638  * Access: RW
9639  */
9640 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE);
9641 
9642 /* This is used to access the optional upper pages (1-3) in the QSFP+
9643  * memory map. Page 1 is available on offset 256 through 383, page 2 -
9644  * on offset 384 through 511, page 3 - on offset 512 through 639.
9645  */
9646 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \
9647 				MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \
9648 				MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1)
9649 
mlxsw_reg_mcia_pack(char * payload,u8 slot_index,u8 module,u8 lock,u8 page_number,u16 device_addr,u8 size,u8 i2c_device_addr)9650 static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module,
9651 				       u8 lock, u8 page_number,
9652 				       u16 device_addr, u8 size,
9653 				       u8 i2c_device_addr)
9654 {
9655 	MLXSW_REG_ZERO(mcia, payload);
9656 	mlxsw_reg_mcia_slot_set(payload, slot_index);
9657 	mlxsw_reg_mcia_module_set(payload, module);
9658 	mlxsw_reg_mcia_l_set(payload, lock);
9659 	mlxsw_reg_mcia_page_number_set(payload, page_number);
9660 	mlxsw_reg_mcia_device_address_set(payload, device_addr);
9661 	mlxsw_reg_mcia_size_set(payload, size);
9662 	mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
9663 }
9664 
9665 /* MPAT - Monitoring Port Analyzer Table
9666  * -------------------------------------
9667  * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
9668  * For an enabled analyzer, all fields except e (enable) cannot be modified.
9669  */
9670 #define MLXSW_REG_MPAT_ID 0x901A
9671 #define MLXSW_REG_MPAT_LEN 0x78
9672 
9673 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
9674 
9675 /* reg_mpat_pa_id
9676  * Port Analyzer ID.
9677  * Access: Index
9678  */
9679 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
9680 
9681 /* reg_mpat_session_id
9682  * Mirror Session ID.
9683  * Used for MIRROR_SESSION<i> trap.
9684  * Access: RW
9685  */
9686 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4);
9687 
9688 /* reg_mpat_system_port
9689  * A unique port identifier for the final destination of the packet.
9690  * Access: RW
9691  */
9692 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
9693 
9694 /* reg_mpat_e
9695  * Enable. Indicating the Port Analyzer is enabled.
9696  * Access: RW
9697  */
9698 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
9699 
9700 /* reg_mpat_qos
9701  * Quality Of Service Mode.
9702  * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
9703  * PCP, DEI, DSCP or VL) are configured.
9704  * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
9705  * same as in the original packet that has triggered the mirroring. For
9706  * SPAN also the pcp,dei are maintained.
9707  * Access: RW
9708  */
9709 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
9710 
9711 /* reg_mpat_be
9712  * Best effort mode. Indicates mirroring traffic should not cause packet
9713  * drop or back pressure, but will discard the mirrored packets. Mirrored
9714  * packets will be forwarded on a best effort manner.
9715  * 0: Do not discard mirrored packets
9716  * 1: Discard mirrored packets if causing congestion
9717  * Access: RW
9718  */
9719 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
9720 
9721 enum mlxsw_reg_mpat_span_type {
9722 	/* Local SPAN Ethernet.
9723 	 * The original packet is not encapsulated.
9724 	 */
9725 	MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
9726 
9727 	/* Remote SPAN Ethernet VLAN.
9728 	 * The packet is forwarded to the monitoring port on the monitoring
9729 	 * VLAN.
9730 	 */
9731 	MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
9732 
9733 	/* Encapsulated Remote SPAN Ethernet L3 GRE.
9734 	 * The packet is encapsulated with GRE header.
9735 	 */
9736 	MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
9737 };
9738 
9739 /* reg_mpat_span_type
9740  * SPAN type.
9741  * Access: RW
9742  */
9743 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
9744 
9745 /* reg_mpat_pide
9746  * Policer enable.
9747  * Access: RW
9748  */
9749 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1);
9750 
9751 /* reg_mpat_pid
9752  * Policer ID.
9753  * Access: RW
9754  */
9755 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14);
9756 
9757 /* Remote SPAN - Ethernet VLAN
9758  * - - - - - - - - - - - - - -
9759  */
9760 
9761 /* reg_mpat_eth_rspan_vid
9762  * Encapsulation header VLAN ID.
9763  * Access: RW
9764  */
9765 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
9766 
9767 /* Encapsulated Remote SPAN - Ethernet L2
9768  * - - - - - - - - - - - - - - - - - - -
9769  */
9770 
9771 enum mlxsw_reg_mpat_eth_rspan_version {
9772 	MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
9773 };
9774 
9775 /* reg_mpat_eth_rspan_version
9776  * RSPAN mirror header version.
9777  * Access: RW
9778  */
9779 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
9780 
9781 /* reg_mpat_eth_rspan_mac
9782  * Destination MAC address.
9783  * Access: RW
9784  */
9785 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
9786 
9787 /* reg_mpat_eth_rspan_tp
9788  * Tag Packet. Indicates whether the mirroring header should be VLAN tagged.
9789  * Access: RW
9790  */
9791 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
9792 
9793 /* Encapsulated Remote SPAN - Ethernet L3
9794  * - - - - - - - - - - - - - - - - - - -
9795  */
9796 
9797 enum mlxsw_reg_mpat_eth_rspan_protocol {
9798 	MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
9799 	MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
9800 };
9801 
9802 /* reg_mpat_eth_rspan_protocol
9803  * SPAN encapsulation protocol.
9804  * Access: RW
9805  */
9806 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
9807 
9808 /* reg_mpat_eth_rspan_ttl
9809  * Encapsulation header Time-to-Live/HopLimit.
9810  * Access: RW
9811  */
9812 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
9813 
9814 /* reg_mpat_eth_rspan_smac
9815  * Source MAC address
9816  * Access: RW
9817  */
9818 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
9819 
9820 /* reg_mpat_eth_rspan_dip*
9821  * Destination IP address. The IP version is configured by protocol.
9822  * Access: RW
9823  */
9824 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
9825 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
9826 
9827 /* reg_mpat_eth_rspan_sip*
9828  * Source IP address. The IP version is configured by protocol.
9829  * Access: RW
9830  */
9831 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
9832 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
9833 
mlxsw_reg_mpat_pack(char * payload,u8 pa_id,u16 system_port,bool e,enum mlxsw_reg_mpat_span_type span_type)9834 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
9835 				       u16 system_port, bool e,
9836 				       enum mlxsw_reg_mpat_span_type span_type)
9837 {
9838 	MLXSW_REG_ZERO(mpat, payload);
9839 	mlxsw_reg_mpat_pa_id_set(payload, pa_id);
9840 	mlxsw_reg_mpat_system_port_set(payload, system_port);
9841 	mlxsw_reg_mpat_e_set(payload, e);
9842 	mlxsw_reg_mpat_qos_set(payload, 1);
9843 	mlxsw_reg_mpat_be_set(payload, 1);
9844 	mlxsw_reg_mpat_span_type_set(payload, span_type);
9845 }
9846 
mlxsw_reg_mpat_eth_rspan_pack(char * payload,u16 vid)9847 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
9848 {
9849 	mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
9850 }
9851 
9852 static inline void
mlxsw_reg_mpat_eth_rspan_l2_pack(char * payload,enum mlxsw_reg_mpat_eth_rspan_version version,const char * mac,bool tp)9853 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
9854 				 enum mlxsw_reg_mpat_eth_rspan_version version,
9855 				 const char *mac,
9856 				 bool tp)
9857 {
9858 	mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
9859 	mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
9860 	mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
9861 }
9862 
9863 static inline void
mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char * payload,u8 ttl,const char * smac,u32 sip,u32 dip)9864 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
9865 				      const char *smac,
9866 				      u32 sip, u32 dip)
9867 {
9868 	mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
9869 	mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
9870 	mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
9871 				    MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
9872 	mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
9873 	mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
9874 }
9875 
9876 static inline void
mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char * payload,u8 ttl,const char * smac,struct in6_addr sip,struct in6_addr dip)9877 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
9878 				      const char *smac,
9879 				      struct in6_addr sip, struct in6_addr dip)
9880 {
9881 	mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
9882 	mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
9883 	mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
9884 				    MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
9885 	mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
9886 	mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
9887 }
9888 
9889 /* MPAR - Monitoring Port Analyzer Register
9890  * ----------------------------------------
9891  * MPAR register is used to query and configure the port analyzer port mirroring
9892  * properties.
9893  */
9894 #define MLXSW_REG_MPAR_ID 0x901B
9895 #define MLXSW_REG_MPAR_LEN 0x0C
9896 
9897 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
9898 
9899 /* reg_mpar_local_port
9900  * The local port to mirror the packets from.
9901  * Access: Index
9902  */
9903 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4);
9904 
9905 enum mlxsw_reg_mpar_i_e {
9906 	MLXSW_REG_MPAR_TYPE_EGRESS,
9907 	MLXSW_REG_MPAR_TYPE_INGRESS,
9908 };
9909 
9910 /* reg_mpar_i_e
9911  * Ingress/Egress
9912  * Access: Index
9913  */
9914 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
9915 
9916 /* reg_mpar_enable
9917  * Enable mirroring
9918  * By default, port mirroring is disabled for all ports.
9919  * Access: RW
9920  */
9921 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
9922 
9923 /* reg_mpar_pa_id
9924  * Port Analyzer ID.
9925  * Access: RW
9926  */
9927 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
9928 
9929 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL
9930 
9931 /* reg_mpar_probability_rate
9932  * Sampling rate.
9933  * Valid values are: 1 to 3.5*10^9
9934  * Value of 1 means "sample all". Default is 1.
9935  * Reserved when Spectrum-1.
9936  * Access: RW
9937  */
9938 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32);
9939 
mlxsw_reg_mpar_pack(char * payload,u16 local_port,enum mlxsw_reg_mpar_i_e i_e,bool enable,u8 pa_id,u32 probability_rate)9940 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port,
9941 				       enum mlxsw_reg_mpar_i_e i_e,
9942 				       bool enable, u8 pa_id,
9943 				       u32 probability_rate)
9944 {
9945 	MLXSW_REG_ZERO(mpar, payload);
9946 	mlxsw_reg_mpar_local_port_set(payload, local_port);
9947 	mlxsw_reg_mpar_enable_set(payload, enable);
9948 	mlxsw_reg_mpar_i_e_set(payload, i_e);
9949 	mlxsw_reg_mpar_pa_id_set(payload, pa_id);
9950 	mlxsw_reg_mpar_probability_rate_set(payload, probability_rate);
9951 }
9952 
9953 /* MGIR - Management General Information Register
9954  * ----------------------------------------------
9955  * MGIR register allows software to query the hardware and firmware general
9956  * information.
9957  */
9958 #define MLXSW_REG_MGIR_ID 0x9020
9959 #define MLXSW_REG_MGIR_LEN 0x9C
9960 
9961 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);
9962 
9963 /* reg_mgir_hw_info_device_hw_revision
9964  * Access: RO
9965  */
9966 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
9967 
9968 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16
9969 
9970 /* reg_mgir_fw_info_psid
9971  * PSID (ASCII string).
9972  * Access: RO
9973  */
9974 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
9975 
9976 /* reg_mgir_fw_info_extended_major
9977  * Access: RO
9978  */
9979 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
9980 
9981 /* reg_mgir_fw_info_extended_minor
9982  * Access: RO
9983  */
9984 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
9985 
9986 /* reg_mgir_fw_info_extended_sub_minor
9987  * Access: RO
9988  */
9989 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
9990 
mlxsw_reg_mgir_pack(char * payload)9991 static inline void mlxsw_reg_mgir_pack(char *payload)
9992 {
9993 	MLXSW_REG_ZERO(mgir, payload);
9994 }
9995 
9996 static inline void
mlxsw_reg_mgir_unpack(char * payload,u32 * hw_rev,char * fw_info_psid,u32 * fw_major,u32 * fw_minor,u32 * fw_sub_minor)9997 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,
9998 		      u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor)
9999 {
10000 	*hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);
10001 	mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);
10002 	*fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);
10003 	*fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);
10004 	*fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);
10005 }
10006 
10007 /* MRSR - Management Reset and Shutdown Register
10008  * ---------------------------------------------
10009  * MRSR register is used to reset or shutdown the switch or
10010  * the entire system (when applicable).
10011  */
10012 #define MLXSW_REG_MRSR_ID 0x9023
10013 #define MLXSW_REG_MRSR_LEN 0x08
10014 
10015 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
10016 
10017 /* reg_mrsr_command
10018  * Reset/shutdown command
10019  * 0 - do nothing
10020  * 1 - software reset
10021  * Access: WO
10022  */
10023 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
10024 
mlxsw_reg_mrsr_pack(char * payload)10025 static inline void mlxsw_reg_mrsr_pack(char *payload)
10026 {
10027 	MLXSW_REG_ZERO(mrsr, payload);
10028 	mlxsw_reg_mrsr_command_set(payload, 1);
10029 }
10030 
10031 /* MLCR - Management LED Control Register
10032  * --------------------------------------
10033  * Controls the system LEDs.
10034  */
10035 #define MLXSW_REG_MLCR_ID 0x902B
10036 #define MLXSW_REG_MLCR_LEN 0x0C
10037 
10038 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
10039 
10040 /* reg_mlcr_local_port
10041  * Local port number.
10042  * Access: RW
10043  */
10044 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24);
10045 
10046 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
10047 
10048 /* reg_mlcr_beacon_duration
10049  * Duration of the beacon to be active, in seconds.
10050  * 0x0 - Will turn off the beacon.
10051  * 0xFFFF - Will turn on the beacon until explicitly turned off.
10052  * Access: RW
10053  */
10054 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
10055 
10056 /* reg_mlcr_beacon_remain
10057  * Remaining duration of the beacon, in seconds.
10058  * 0xFFFF indicates an infinite amount of time.
10059  * Access: RO
10060  */
10061 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
10062 
mlxsw_reg_mlcr_pack(char * payload,u16 local_port,bool active)10063 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port,
10064 				       bool active)
10065 {
10066 	MLXSW_REG_ZERO(mlcr, payload);
10067 	mlxsw_reg_mlcr_local_port_set(payload, local_port);
10068 	mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
10069 					   MLXSW_REG_MLCR_DURATION_MAX : 0);
10070 }
10071 
10072 /* MCION - Management Cable IO and Notifications Register
10073  * ------------------------------------------------------
10074  * The MCION register is used to query transceiver modules' IO pins and other
10075  * notifications.
10076  */
10077 #define MLXSW_REG_MCION_ID 0x9052
10078 #define MLXSW_REG_MCION_LEN 0x18
10079 
10080 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN);
10081 
10082 /* reg_mcion_module
10083  * Module number.
10084  * Access: Index
10085  */
10086 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8);
10087 
10088 /* reg_mcion_slot_index
10089  * Slot index.
10090  * Access: Index
10091  */
10092 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4);
10093 
10094 enum {
10095 	MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0),
10096 	MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8),
10097 };
10098 
10099 /* reg_mcion_module_status_bits
10100  * Module IO status as defined by SFF.
10101  * Access: RO
10102  */
10103 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16);
10104 
mlxsw_reg_mcion_pack(char * payload,u8 slot_index,u8 module)10105 static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module)
10106 {
10107 	MLXSW_REG_ZERO(mcion, payload);
10108 	mlxsw_reg_mcion_slot_index_set(payload, slot_index);
10109 	mlxsw_reg_mcion_module_set(payload, module);
10110 }
10111 
10112 /* MTPPS - Management Pulse Per Second Register
10113  * --------------------------------------------
10114  * This register provides the device PPS capabilities, configure the PPS in and
10115  * out modules and holds the PPS in time stamp.
10116  */
10117 #define MLXSW_REG_MTPPS_ID 0x9053
10118 #define MLXSW_REG_MTPPS_LEN 0x3C
10119 
10120 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
10121 
10122 /* reg_mtpps_enable
10123  * Enables the PPS functionality the specific pin.
10124  * A boolean variable.
10125  * Access: RW
10126  */
10127 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
10128 
10129 enum mlxsw_reg_mtpps_pin_mode {
10130 	MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
10131 };
10132 
10133 /* reg_mtpps_pin_mode
10134  * Pin mode to be used. The mode must comply with the supported modes of the
10135  * requested pin.
10136  * Access: RW
10137  */
10138 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
10139 
10140 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN	7
10141 
10142 /* reg_mtpps_pin
10143  * Pin to be configured or queried out of the supported pins.
10144  * Access: Index
10145  */
10146 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
10147 
10148 /* reg_mtpps_time_stamp
10149  * When pin_mode = pps_in, the latched device time when it was triggered from
10150  * the external GPIO pin.
10151  * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target
10152  * time to generate next output signal.
10153  * Time is in units of device clock.
10154  * Access: RW
10155  */
10156 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
10157 
10158 static inline void
mlxsw_reg_mtpps_vpin_pack(char * payload,u64 time_stamp)10159 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
10160 {
10161 	MLXSW_REG_ZERO(mtpps, payload);
10162 	mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
10163 	mlxsw_reg_mtpps_pin_mode_set(payload,
10164 				     MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
10165 	mlxsw_reg_mtpps_enable_set(payload, true);
10166 	mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
10167 }
10168 
10169 /* MTUTC - Management UTC Register
10170  * -------------------------------
10171  * Configures the HW UTC counter.
10172  */
10173 #define MLXSW_REG_MTUTC_ID 0x9055
10174 #define MLXSW_REG_MTUTC_LEN 0x1C
10175 
10176 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);
10177 
10178 enum mlxsw_reg_mtutc_operation {
10179 	MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
10180 	MLXSW_REG_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 1,
10181 	MLXSW_REG_MTUTC_OPERATION_ADJUST_TIME = 2,
10182 	MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
10183 };
10184 
10185 /* reg_mtutc_operation
10186  * Operation.
10187  * Access: OP
10188  */
10189 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
10190 
10191 /* reg_mtutc_freq_adjustment
10192  * Frequency adjustment: Every PPS the HW frequency will be
10193  * adjusted by this value. Units of HW clock, where HW counts
10194  * 10^9 HW clocks for 1 HW second. Range is from -50,000,000 to +50,000,000.
10195  * In Spectrum-2, the field is reversed, positive values mean to decrease the
10196  * frequency.
10197  * Access: RW
10198  */
10199 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
10200 
10201 #define MLXSW_REG_MTUTC_MAX_FREQ_ADJ (50 * 1000 * 1000)
10202 
10203 /* reg_mtutc_utc_sec
10204  * UTC seconds.
10205  * Access: WO
10206  */
10207 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
10208 
10209 /* reg_mtutc_utc_nsec
10210  * UTC nSecs.
10211  * Range 0..(10^9-1)
10212  * Updated when operation is SET_TIME_IMMEDIATE.
10213  * Reserved on Spectrum-1.
10214  * Access: WO
10215  */
10216 MLXSW_ITEM32(reg, mtutc, utc_nsec, 0x14, 0, 30);
10217 
10218 /* reg_mtutc_time_adjustment
10219  * Time adjustment.
10220  * Units of nSec.
10221  * Range is from -32768 to +32767.
10222  * Updated when operation is ADJUST_TIME.
10223  * Reserved on Spectrum-1.
10224  * Access: WO
10225  */
10226 MLXSW_ITEM32(reg, mtutc, time_adjustment, 0x18, 0, 32);
10227 
10228 static inline void
mlxsw_reg_mtutc_pack(char * payload,enum mlxsw_reg_mtutc_operation oper,u32 freq_adj,u32 utc_sec,u32 utc_nsec,u32 time_adj)10229 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
10230 		     u32 freq_adj, u32 utc_sec, u32 utc_nsec, u32 time_adj)
10231 {
10232 	MLXSW_REG_ZERO(mtutc, payload);
10233 	mlxsw_reg_mtutc_operation_set(payload, oper);
10234 	mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
10235 	mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
10236 	mlxsw_reg_mtutc_utc_nsec_set(payload, utc_nsec);
10237 	mlxsw_reg_mtutc_time_adjustment_set(payload, time_adj);
10238 }
10239 
10240 /* MCQI - Management Component Query Information
10241  * ---------------------------------------------
10242  * This register allows querying information about firmware components.
10243  */
10244 #define MLXSW_REG_MCQI_ID 0x9061
10245 #define MLXSW_REG_MCQI_BASE_LEN 0x18
10246 #define MLXSW_REG_MCQI_CAP_LEN 0x14
10247 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
10248 
10249 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
10250 
10251 /* reg_mcqi_component_index
10252  * Index of the accessed component.
10253  * Access: Index
10254  */
10255 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
10256 
10257 enum mlxfw_reg_mcqi_info_type {
10258 	MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
10259 };
10260 
10261 /* reg_mcqi_info_type
10262  * Component properties set.
10263  * Access: RW
10264  */
10265 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
10266 
10267 /* reg_mcqi_offset
10268  * The requested/returned data offset from the section start, given in bytes.
10269  * Must be DWORD aligned.
10270  * Access: RW
10271  */
10272 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
10273 
10274 /* reg_mcqi_data_size
10275  * The requested/returned data size, given in bytes. If data_size is not DWORD
10276  * aligned, the last bytes are zero padded.
10277  * Access: RW
10278  */
10279 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
10280 
10281 /* reg_mcqi_cap_max_component_size
10282  * Maximum size for this component, given in bytes.
10283  * Access: RO
10284  */
10285 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
10286 
10287 /* reg_mcqi_cap_log_mcda_word_size
10288  * Log 2 of the access word size in bytes. Read and write access must be aligned
10289  * to the word size. Write access must be done for an integer number of words.
10290  * Access: RO
10291  */
10292 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
10293 
10294 /* reg_mcqi_cap_mcda_max_write_size
10295  * Maximal write size for MCDA register
10296  * Access: RO
10297  */
10298 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
10299 
mlxsw_reg_mcqi_pack(char * payload,u16 component_index)10300 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
10301 {
10302 	MLXSW_REG_ZERO(mcqi, payload);
10303 	mlxsw_reg_mcqi_component_index_set(payload, component_index);
10304 	mlxsw_reg_mcqi_info_type_set(payload,
10305 				     MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
10306 	mlxsw_reg_mcqi_offset_set(payload, 0);
10307 	mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
10308 }
10309 
mlxsw_reg_mcqi_unpack(char * payload,u32 * p_cap_max_component_size,u8 * p_cap_log_mcda_word_size,u16 * p_cap_mcda_max_write_size)10310 static inline void mlxsw_reg_mcqi_unpack(char *payload,
10311 					 u32 *p_cap_max_component_size,
10312 					 u8 *p_cap_log_mcda_word_size,
10313 					 u16 *p_cap_mcda_max_write_size)
10314 {
10315 	*p_cap_max_component_size =
10316 		mlxsw_reg_mcqi_cap_max_component_size_get(payload);
10317 	*p_cap_log_mcda_word_size =
10318 		mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
10319 	*p_cap_mcda_max_write_size =
10320 		mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
10321 }
10322 
10323 /* MCC - Management Component Control
10324  * ----------------------------------
10325  * Controls the firmware component and updates the FSM.
10326  */
10327 #define MLXSW_REG_MCC_ID 0x9062
10328 #define MLXSW_REG_MCC_LEN 0x1C
10329 
10330 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
10331 
10332 enum mlxsw_reg_mcc_instruction {
10333 	MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
10334 	MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
10335 	MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
10336 	MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
10337 	MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
10338 	MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
10339 };
10340 
10341 /* reg_mcc_instruction
10342  * Command to be executed by the FSM.
10343  * Applicable for write operation only.
10344  * Access: RW
10345  */
10346 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
10347 
10348 /* reg_mcc_component_index
10349  * Index of the accessed component. Applicable only for commands that
10350  * refer to components. Otherwise, this field is reserved.
10351  * Access: Index
10352  */
10353 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
10354 
10355 /* reg_mcc_update_handle
10356  * Token representing the current flow executed by the FSM.
10357  * Access: WO
10358  */
10359 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
10360 
10361 /* reg_mcc_error_code
10362  * Indicates the successful completion of the instruction, or the reason it
10363  * failed
10364  * Access: RO
10365  */
10366 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
10367 
10368 /* reg_mcc_control_state
10369  * Current FSM state
10370  * Access: RO
10371  */
10372 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
10373 
10374 /* reg_mcc_component_size
10375  * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying
10376  * the size may shorten the update time. Value 0x0 means that size is
10377  * unspecified.
10378  * Access: WO
10379  */
10380 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
10381 
mlxsw_reg_mcc_pack(char * payload,enum mlxsw_reg_mcc_instruction instr,u16 component_index,u32 update_handle,u32 component_size)10382 static inline void mlxsw_reg_mcc_pack(char *payload,
10383 				      enum mlxsw_reg_mcc_instruction instr,
10384 				      u16 component_index, u32 update_handle,
10385 				      u32 component_size)
10386 {
10387 	MLXSW_REG_ZERO(mcc, payload);
10388 	mlxsw_reg_mcc_instruction_set(payload, instr);
10389 	mlxsw_reg_mcc_component_index_set(payload, component_index);
10390 	mlxsw_reg_mcc_update_handle_set(payload, update_handle);
10391 	mlxsw_reg_mcc_component_size_set(payload, component_size);
10392 }
10393 
mlxsw_reg_mcc_unpack(char * payload,u32 * p_update_handle,u8 * p_error_code,u8 * p_control_state)10394 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
10395 					u8 *p_error_code, u8 *p_control_state)
10396 {
10397 	if (p_update_handle)
10398 		*p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
10399 	if (p_error_code)
10400 		*p_error_code = mlxsw_reg_mcc_error_code_get(payload);
10401 	if (p_control_state)
10402 		*p_control_state = mlxsw_reg_mcc_control_state_get(payload);
10403 }
10404 
10405 /* MCDA - Management Component Data Access
10406  * ---------------------------------------
10407  * This register allows reading and writing a firmware component.
10408  */
10409 #define MLXSW_REG_MCDA_ID 0x9063
10410 #define MLXSW_REG_MCDA_BASE_LEN 0x10
10411 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
10412 #define MLXSW_REG_MCDA_LEN \
10413 		(MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
10414 
10415 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
10416 
10417 /* reg_mcda_update_handle
10418  * Token representing the current flow executed by the FSM.
10419  * Access: RW
10420  */
10421 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
10422 
10423 /* reg_mcda_offset
10424  * Offset of accessed address relative to component start. Accesses must be in
10425  * accordance to log_mcda_word_size in MCQI reg.
10426  * Access: RW
10427  */
10428 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
10429 
10430 /* reg_mcda_size
10431  * Size of the data accessed, given in bytes.
10432  * Access: RW
10433  */
10434 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
10435 
10436 /* reg_mcda_data
10437  * Data block accessed.
10438  * Access: RW
10439  */
10440 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
10441 
mlxsw_reg_mcda_pack(char * payload,u32 update_handle,u32 offset,u16 size,u8 * data)10442 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
10443 				       u32 offset, u16 size, u8 *data)
10444 {
10445 	int i;
10446 
10447 	MLXSW_REG_ZERO(mcda, payload);
10448 	mlxsw_reg_mcda_update_handle_set(payload, update_handle);
10449 	mlxsw_reg_mcda_offset_set(payload, offset);
10450 	mlxsw_reg_mcda_size_set(payload, size);
10451 
10452 	for (i = 0; i < size / 4; i++)
10453 		mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
10454 }
10455 
10456 /* MPSC - Monitoring Packet Sampling Configuration Register
10457  * --------------------------------------------------------
10458  * MPSC Register is used to configure the Packet Sampling mechanism.
10459  */
10460 #define MLXSW_REG_MPSC_ID 0x9080
10461 #define MLXSW_REG_MPSC_LEN 0x1C
10462 
10463 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
10464 
10465 /* reg_mpsc_local_port
10466  * Local port number
10467  * Not supported for CPU port
10468  * Access: Index
10469  */
10470 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12);
10471 
10472 /* reg_mpsc_e
10473  * Enable sampling on port local_port
10474  * Access: RW
10475  */
10476 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
10477 
10478 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
10479 
10480 /* reg_mpsc_rate
10481  * Sampling rate = 1 out of rate packets (with randomization around
10482  * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
10483  * Access: RW
10484  */
10485 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
10486 
mlxsw_reg_mpsc_pack(char * payload,u16 local_port,bool e,u32 rate)10487 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e,
10488 				       u32 rate)
10489 {
10490 	MLXSW_REG_ZERO(mpsc, payload);
10491 	mlxsw_reg_mpsc_local_port_set(payload, local_port);
10492 	mlxsw_reg_mpsc_e_set(payload, e);
10493 	mlxsw_reg_mpsc_rate_set(payload, rate);
10494 }
10495 
10496 /* MGPC - Monitoring General Purpose Counter Set Register
10497  * The MGPC register retrieves and sets the General Purpose Counter Set.
10498  */
10499 #define MLXSW_REG_MGPC_ID 0x9081
10500 #define MLXSW_REG_MGPC_LEN 0x18
10501 
10502 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
10503 
10504 /* reg_mgpc_counter_set_type
10505  * Counter set type.
10506  * Access: OP
10507  */
10508 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
10509 
10510 /* reg_mgpc_counter_index
10511  * Counter index.
10512  * Access: Index
10513  */
10514 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
10515 
10516 enum mlxsw_reg_mgpc_opcode {
10517 	/* Nop */
10518 	MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
10519 	/* Clear counters */
10520 	MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
10521 };
10522 
10523 /* reg_mgpc_opcode
10524  * Opcode.
10525  * Access: OP
10526  */
10527 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
10528 
10529 /* reg_mgpc_byte_counter
10530  * Byte counter value.
10531  * Access: RW
10532  */
10533 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
10534 
10535 /* reg_mgpc_packet_counter
10536  * Packet counter value.
10537  * Access: RW
10538  */
10539 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
10540 
mlxsw_reg_mgpc_pack(char * payload,u32 counter_index,enum mlxsw_reg_mgpc_opcode opcode,enum mlxsw_reg_flow_counter_set_type set_type)10541 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
10542 				       enum mlxsw_reg_mgpc_opcode opcode,
10543 				       enum mlxsw_reg_flow_counter_set_type set_type)
10544 {
10545 	MLXSW_REG_ZERO(mgpc, payload);
10546 	mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
10547 	mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
10548 	mlxsw_reg_mgpc_opcode_set(payload, opcode);
10549 }
10550 
10551 /* MPRS - Monitoring Parsing State Register
10552  * ----------------------------------------
10553  * The MPRS register is used for setting up the parsing for hash,
10554  * policy-engine and routing.
10555  */
10556 #define MLXSW_REG_MPRS_ID 0x9083
10557 #define MLXSW_REG_MPRS_LEN 0x14
10558 
10559 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
10560 
10561 /* reg_mprs_parsing_depth
10562  * Minimum parsing depth.
10563  * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL
10564  * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.
10565  * Access: RW
10566  */
10567 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
10568 
10569 /* reg_mprs_parsing_en
10570  * Parsing enable.
10571  * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and
10572  * NVGRE. Default is enabled. Reserved when SwitchX-2.
10573  * Access: RW
10574  */
10575 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
10576 
10577 /* reg_mprs_vxlan_udp_dport
10578  * VxLAN UDP destination port.
10579  * Used for identifying VxLAN packets and for dport field in
10580  * encapsulation. Default is 4789.
10581  * Access: RW
10582  */
10583 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
10584 
mlxsw_reg_mprs_pack(char * payload,u16 parsing_depth,u16 vxlan_udp_dport)10585 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
10586 				       u16 vxlan_udp_dport)
10587 {
10588 	MLXSW_REG_ZERO(mprs, payload);
10589 	mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
10590 	mlxsw_reg_mprs_parsing_en_set(payload, true);
10591 	mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
10592 }
10593 
10594 /* MOGCR - Monitoring Global Configuration Register
10595  * ------------------------------------------------
10596  */
10597 #define MLXSW_REG_MOGCR_ID 0x9086
10598 #define MLXSW_REG_MOGCR_LEN 0x20
10599 
10600 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
10601 
10602 /* reg_mogcr_ptp_iftc
10603  * PTP Ingress FIFO Trap Clear
10604  * The PTP_ING_FIFO trap provides MTPPTR with clr according
10605  * to this value. Default 0.
10606  * Reserved when IB switches and when SwitchX/-2, Spectrum-2
10607  * Access: RW
10608  */
10609 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
10610 
10611 /* reg_mogcr_ptp_eftc
10612  * PTP Egress FIFO Trap Clear
10613  * The PTP_EGR_FIFO trap provides MTPPTR with clr according
10614  * to this value. Default 0.
10615  * Reserved when IB switches and when SwitchX/-2, Spectrum-2
10616  * Access: RW
10617  */
10618 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
10619 
10620 /* reg_mogcr_mirroring_pid_base
10621  * Base policer id for mirroring policers.
10622  * Must have an even value (e.g. 1000, not 1001).
10623  * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum.
10624  * Access: RW
10625  */
10626 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14);
10627 
10628 /* MPAGR - Monitoring Port Analyzer Global Register
10629  * ------------------------------------------------
10630  * This register is used for global port analyzer configurations.
10631  * Note: This register is not supported by current FW versions for Spectrum-1.
10632  */
10633 #define MLXSW_REG_MPAGR_ID 0x9089
10634 #define MLXSW_REG_MPAGR_LEN 0x0C
10635 
10636 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN);
10637 
10638 enum mlxsw_reg_mpagr_trigger {
10639 	MLXSW_REG_MPAGR_TRIGGER_EGRESS,
10640 	MLXSW_REG_MPAGR_TRIGGER_INGRESS,
10641 	MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED,
10642 	MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER,
10643 	MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG,
10644 	MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG,
10645 	MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN,
10646 	MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY,
10647 };
10648 
10649 /* reg_mpagr_trigger
10650  * Mirror trigger.
10651  * Access: Index
10652  */
10653 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4);
10654 
10655 /* reg_mpagr_pa_id
10656  * Port analyzer ID.
10657  * Access: RW
10658  */
10659 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4);
10660 
10661 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL
10662 
10663 /* reg_mpagr_probability_rate
10664  * Sampling rate.
10665  * Valid values are: 1 to 3.5*10^9
10666  * Value of 1 means "sample all". Default is 1.
10667  * Access: RW
10668  */
10669 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32);
10670 
mlxsw_reg_mpagr_pack(char * payload,enum mlxsw_reg_mpagr_trigger trigger,u8 pa_id,u32 probability_rate)10671 static inline void mlxsw_reg_mpagr_pack(char *payload,
10672 					enum mlxsw_reg_mpagr_trigger trigger,
10673 					u8 pa_id, u32 probability_rate)
10674 {
10675 	MLXSW_REG_ZERO(mpagr, payload);
10676 	mlxsw_reg_mpagr_trigger_set(payload, trigger);
10677 	mlxsw_reg_mpagr_pa_id_set(payload, pa_id);
10678 	mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate);
10679 }
10680 
10681 /* MOMTE - Monitoring Mirror Trigger Enable Register
10682  * -------------------------------------------------
10683  * This register is used to configure the mirror enable for different mirror
10684  * reasons.
10685  */
10686 #define MLXSW_REG_MOMTE_ID 0x908D
10687 #define MLXSW_REG_MOMTE_LEN 0x10
10688 
10689 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN);
10690 
10691 /* reg_momte_local_port
10692  * Local port number.
10693  * Access: Index
10694  */
10695 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12);
10696 
10697 enum mlxsw_reg_momte_type {
10698 	MLXSW_REG_MOMTE_TYPE_WRED = 0x20,
10699 	MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31,
10700 	MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32,
10701 	MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33,
10702 	MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40,
10703 	MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50,
10704 	MLXSW_REG_MOMTE_TYPE_ECN = 0x60,
10705 	MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70,
10706 };
10707 
10708 /* reg_momte_type
10709  * Type of mirroring.
10710  * Access: Index
10711  */
10712 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8);
10713 
10714 /* reg_momte_tclass_en
10715  * TClass/PG mirror enable. Each bit represents corresponding tclass.
10716  * 0: disable (default)
10717  * 1: enable
10718  * Access: RW
10719  */
10720 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1);
10721 
mlxsw_reg_momte_pack(char * payload,u16 local_port,enum mlxsw_reg_momte_type type)10722 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port,
10723 					enum mlxsw_reg_momte_type type)
10724 {
10725 	MLXSW_REG_ZERO(momte, payload);
10726 	mlxsw_reg_momte_local_port_set(payload, local_port);
10727 	mlxsw_reg_momte_type_set(payload, type);
10728 }
10729 
10730 /* MTPPPC - Time Precision Packet Port Configuration
10731  * -------------------------------------------------
10732  * This register serves for configuration of which PTP messages should be
10733  * timestamped. This is a global configuration, despite the register name.
10734  *
10735  * Reserved when Spectrum-2.
10736  */
10737 #define MLXSW_REG_MTPPPC_ID 0x9090
10738 #define MLXSW_REG_MTPPPC_LEN 0x28
10739 
10740 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);
10741 
10742 /* reg_mtpppc_ing_timestamp_message_type
10743  * Bitwise vector of PTP message types to timestamp at ingress.
10744  * MessageType field as defined by IEEE 1588
10745  * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
10746  * Default all 0
10747  * Access: RW
10748  */
10749 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
10750 
10751 /* reg_mtpppc_egr_timestamp_message_type
10752  * Bitwise vector of PTP message types to timestamp at egress.
10753  * MessageType field as defined by IEEE 1588
10754  * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
10755  * Default all 0
10756  * Access: RW
10757  */
10758 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
10759 
mlxsw_reg_mtpppc_pack(char * payload,u16 ing,u16 egr)10760 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)
10761 {
10762 	MLXSW_REG_ZERO(mtpppc, payload);
10763 	mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);
10764 	mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);
10765 }
10766 
10767 /* MTPPTR - Time Precision Packet Timestamping Reading
10768  * ---------------------------------------------------
10769  * The MTPPTR is used for reading the per port PTP timestamp FIFO.
10770  * There is a trap for packets which are latched to the timestamp FIFO, thus the
10771  * SW knows which FIFO to read. Note that packets enter the FIFO before been
10772  * trapped. The sequence number is used to synchronize the timestamp FIFO
10773  * entries and the trapped packets.
10774  * Reserved when Spectrum-2.
10775  */
10776 
10777 #define MLXSW_REG_MTPPTR_ID 0x9091
10778 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */
10779 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */
10780 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4
10781 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN +		\
10782 		    MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
10783 
10784 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);
10785 
10786 /* reg_mtpptr_local_port
10787  * Not supported for CPU port.
10788  * Access: Index
10789  */
10790 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12);
10791 
10792 enum mlxsw_reg_mtpptr_dir {
10793 	MLXSW_REG_MTPPTR_DIR_INGRESS,
10794 	MLXSW_REG_MTPPTR_DIR_EGRESS,
10795 };
10796 
10797 /* reg_mtpptr_dir
10798  * Direction.
10799  * Access: Index
10800  */
10801 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
10802 
10803 /* reg_mtpptr_clr
10804  * Clear the records.
10805  * Access: OP
10806  */
10807 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
10808 
10809 /* reg_mtpptr_num_rec
10810  * Number of valid records in the response
10811  * Range 0.. cap_ptp_timestamp_fifo
10812  * Access: RO
10813  */
10814 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
10815 
10816 /* reg_mtpptr_rec_message_type
10817  * MessageType field as defined by IEEE 1588 Each bit corresponds to a value
10818  * (e.g. Bit0: Sync, Bit1: Delay_Req)
10819  * Access: RO
10820  */
10821 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
10822 		     MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
10823 		     MLXSW_REG_MTPPTR_REC_LEN, 0, false);
10824 
10825 /* reg_mtpptr_rec_domain_number
10826  * DomainNumber field as defined by IEEE 1588
10827  * Access: RO
10828  */
10829 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
10830 		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
10831 		     MLXSW_REG_MTPPTR_REC_LEN, 0, false);
10832 
10833 /* reg_mtpptr_rec_sequence_id
10834  * SequenceId field as defined by IEEE 1588
10835  * Access: RO
10836  */
10837 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
10838 		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
10839 		     MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
10840 
10841 /* reg_mtpptr_rec_timestamp_high
10842  * Timestamp of when the PTP packet has passed through the port Units of PLL
10843  * clock time.
10844  * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec.
10845  * Access: RO
10846  */
10847 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
10848 		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
10849 		     MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
10850 
10851 /* reg_mtpptr_rec_timestamp_low
10852  * See rec_timestamp_high.
10853  * Access: RO
10854  */
10855 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
10856 		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
10857 		     MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);
10858 
mlxsw_reg_mtpptr_unpack(const char * payload,unsigned int rec,u8 * p_message_type,u8 * p_domain_number,u16 * p_sequence_id,u64 * p_timestamp)10859 static inline void mlxsw_reg_mtpptr_unpack(const char *payload,
10860 					   unsigned int rec,
10861 					   u8 *p_message_type,
10862 					   u8 *p_domain_number,
10863 					   u16 *p_sequence_id,
10864 					   u64 *p_timestamp)
10865 {
10866 	u32 timestamp_high, timestamp_low;
10867 
10868 	*p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);
10869 	*p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);
10870 	*p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);
10871 	timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);
10872 	timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);
10873 	*p_timestamp = (u64)timestamp_high << 32 | timestamp_low;
10874 }
10875 
10876 /* MTPTPT - Monitoring Precision Time Protocol Trap Register
10877  * ---------------------------------------------------------
10878  * This register is used for configuring under which trap to deliver PTP
10879  * packets depending on type of the packet.
10880  */
10881 #define MLXSW_REG_MTPTPT_ID 0x9092
10882 #define MLXSW_REG_MTPTPT_LEN 0x08
10883 
10884 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);
10885 
10886 enum mlxsw_reg_mtptpt_trap_id {
10887 	MLXSW_REG_MTPTPT_TRAP_ID_PTP0,
10888 	MLXSW_REG_MTPTPT_TRAP_ID_PTP1,
10889 };
10890 
10891 /* reg_mtptpt_trap_id
10892  * Trap id.
10893  * Access: Index
10894  */
10895 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
10896 
10897 /* reg_mtptpt_message_type
10898  * Bitwise vector of PTP message types to trap. This is a necessary but
10899  * non-sufficient condition since need to enable also per port. See MTPPPC.
10900  * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g.
10901  * Bit0: Sync, Bit1: Delay_Req)
10902  */
10903 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
10904 
mlxsw_reg_mtptpt_pack(char * payload,enum mlxsw_reg_mtptpt_trap_id trap_id,u16 message_type)10905 static inline void mlxsw_reg_mtptpt_pack(char *payload,
10906 					 enum mlxsw_reg_mtptpt_trap_id trap_id,
10907 					 u16 message_type)
10908 {
10909 	MLXSW_REG_ZERO(mtptpt, payload);
10910 	mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);
10911 	mlxsw_reg_mtptpt_message_type_set(payload, message_type);
10912 }
10913 
10914 /* MTPCPC - Monitoring Time Precision Correction Port Configuration Register
10915  * -------------------------------------------------------------------------
10916  */
10917 #define MLXSW_REG_MTPCPC_ID 0x9093
10918 #define MLXSW_REG_MTPCPC_LEN 0x2C
10919 
10920 MLXSW_REG_DEFINE(mtpcpc, MLXSW_REG_MTPCPC_ID, MLXSW_REG_MTPCPC_LEN);
10921 
10922 /* reg_mtpcpc_pport
10923  * Per port:
10924  * 0: config is global. When reading - the local_port is 1.
10925  * 1: config is per port.
10926  * Access: Index
10927  */
10928 MLXSW_ITEM32(reg, mtpcpc, pport, 0x00, 31, 1);
10929 
10930 /* reg_mtpcpc_local_port
10931  * Local port number.
10932  * Supported to/from CPU port.
10933  * Reserved when pport = 0.
10934  * Access: Index
10935  */
10936 MLXSW_ITEM32_LP(reg, mtpcpc, 0x00, 16, 0x00, 12);
10937 
10938 /* reg_mtpcpc_ptp_trap_en
10939  * Enable PTP traps.
10940  * The trap_id is configured by MTPTPT.
10941  * Access: RW
10942  */
10943 MLXSW_ITEM32(reg, mtpcpc, ptp_trap_en, 0x04, 0, 1);
10944 
10945 /* reg_mtpcpc_ing_correction_message_type
10946  * Bitwise vector of PTP message types to update correction-field at ingress.
10947  * MessageType field as defined by IEEE 1588 Each bit corresponds to a value
10948  * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port.
10949  * Default all 0
10950  * Access: RW
10951  */
10952 MLXSW_ITEM32(reg, mtpcpc, ing_correction_message_type, 0x10, 0, 16);
10953 
10954 /* reg_mtpcpc_egr_correction_message_type
10955  * Bitwise vector of PTP message types to update correction-field at egress.
10956  * MessageType field as defined by IEEE 1588 Each bit corresponds to a value
10957  * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port.
10958  * Default all 0
10959  * Access: RW
10960  */
10961 MLXSW_ITEM32(reg, mtpcpc, egr_correction_message_type, 0x14, 0, 16);
10962 
mlxsw_reg_mtpcpc_pack(char * payload,bool pport,u16 local_port,bool ptp_trap_en,u16 ing,u16 egr)10963 static inline void mlxsw_reg_mtpcpc_pack(char *payload, bool pport,
10964 					 u16 local_port, bool ptp_trap_en,
10965 					 u16 ing, u16 egr)
10966 {
10967 	MLXSW_REG_ZERO(mtpcpc, payload);
10968 	mlxsw_reg_mtpcpc_pport_set(payload, pport);
10969 	mlxsw_reg_mtpcpc_local_port_set(payload, pport ? local_port : 0);
10970 	mlxsw_reg_mtpcpc_ptp_trap_en_set(payload, ptp_trap_en);
10971 	mlxsw_reg_mtpcpc_ing_correction_message_type_set(payload, ing);
10972 	mlxsw_reg_mtpcpc_egr_correction_message_type_set(payload, egr);
10973 }
10974 
10975 /* MFGD - Monitoring FW General Debug Register
10976  * -------------------------------------------
10977  */
10978 #define MLXSW_REG_MFGD_ID 0x90F0
10979 #define MLXSW_REG_MFGD_LEN 0x0C
10980 
10981 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN);
10982 
10983 /* reg_mfgd_fw_fatal_event_mode
10984  * 0 - don't check FW fatal (default)
10985  * 1 - check FW fatal - enable MFDE trap
10986  * Access: RW
10987  */
10988 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2);
10989 
10990 /* reg_mfgd_trigger_test
10991  * Access: WO
10992  */
10993 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1);
10994 
10995 /* MGPIR - Management General Peripheral Information Register
10996  * ----------------------------------------------------------
10997  * MGPIR register allows software to query the hardware and
10998  * firmware general information of peripheral entities.
10999  */
11000 #define MLXSW_REG_MGPIR_ID 0x9100
11001 #define MLXSW_REG_MGPIR_LEN 0xA0
11002 
11003 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN);
11004 
11005 enum mlxsw_reg_mgpir_device_type {
11006 	MLXSW_REG_MGPIR_DEVICE_TYPE_NONE,
11007 	MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE,
11008 };
11009 
11010 /* mgpir_slot_index
11011  * Slot index (0: Main board).
11012  * Access: Index
11013  */
11014 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4);
11015 
11016 /* mgpir_device_type
11017  * Access: RO
11018  */
11019 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);
11020 
11021 /* mgpir_devices_per_flash
11022  * Number of devices of device_type per flash (can be shared by few devices).
11023  * Access: RO
11024  */
11025 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
11026 
11027 /* mgpir_num_of_devices
11028  * Number of devices of device_type.
11029  * Access: RO
11030  */
11031 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
11032 
11033 /* max_modules_per_slot
11034  * Maximum number of modules that can be connected per slot.
11035  * Access: RO
11036  */
11037 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8);
11038 
11039 /* mgpir_num_of_slots
11040  * Number of slots in the system.
11041  * Access: RO
11042  */
11043 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8);
11044 
11045 /* mgpir_num_of_modules
11046  * Number of modules.
11047  * Access: RO
11048  */
11049 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8);
11050 
mlxsw_reg_mgpir_pack(char * payload,u8 slot_index)11051 static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index)
11052 {
11053 	MLXSW_REG_ZERO(mgpir, payload);
11054 	mlxsw_reg_mgpir_slot_index_set(payload, slot_index);
11055 }
11056 
11057 static inline void
mlxsw_reg_mgpir_unpack(char * payload,u8 * num_of_devices,enum mlxsw_reg_mgpir_device_type * device_type,u8 * devices_per_flash,u8 * num_of_modules,u8 * num_of_slots)11058 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
11059 		       enum mlxsw_reg_mgpir_device_type *device_type,
11060 		       u8 *devices_per_flash, u8 *num_of_modules,
11061 		       u8 *num_of_slots)
11062 {
11063 	if (num_of_devices)
11064 		*num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload);
11065 	if (device_type)
11066 		*device_type = mlxsw_reg_mgpir_device_type_get(payload);
11067 	if (devices_per_flash)
11068 		*devices_per_flash =
11069 				mlxsw_reg_mgpir_devices_per_flash_get(payload);
11070 	if (num_of_modules)
11071 		*num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload);
11072 	if (num_of_slots)
11073 		*num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload);
11074 }
11075 
11076 /* MBCT - Management Binary Code Transfer Register
11077  * -----------------------------------------------
11078  * This register allows to transfer binary codes from the host to
11079  * the management FW by transferring it by chunks of maximum 1KB.
11080  */
11081 #define MLXSW_REG_MBCT_ID 0x9120
11082 #define MLXSW_REG_MBCT_LEN 0x420
11083 
11084 MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN);
11085 
11086 /* reg_mbct_slot_index
11087  * Slot index. 0 is reserved.
11088  * Access: Index
11089  */
11090 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4);
11091 
11092 /* reg_mbct_data_size
11093  * Actual data field size in bytes for the current data transfer.
11094  * Access: WO
11095  */
11096 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11);
11097 
11098 enum mlxsw_reg_mbct_op {
11099 	MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1,
11100 	MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */
11101 	MLXSW_REG_MBCT_OP_ACTIVATE,
11102 	MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6,
11103 	MLXSW_REG_MBCT_OP_QUERY_STATUS,
11104 };
11105 
11106 /* reg_mbct_op
11107  * Access: WO
11108  */
11109 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4);
11110 
11111 /* reg_mbct_last
11112  * Indicates that the current data field is the last chunk of the INI.
11113  * Access: WO
11114  */
11115 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1);
11116 
11117 /* reg_mbct_oee
11118  * Opcode Event Enable. When set a BCTOE event will be sent once the opcode
11119  * was executed and the fsm_state has changed.
11120  * Access: WO
11121  */
11122 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1);
11123 
11124 enum mlxsw_reg_mbct_status {
11125 	/* Partial data transfer completed successfully and ready for next
11126 	 * data transfer.
11127 	 */
11128 	MLXSW_REG_MBCT_STATUS_PART_DATA = 2,
11129 	MLXSW_REG_MBCT_STATUS_LAST_DATA,
11130 	MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE,
11131 	/* Error - trying to erase INI while it being used. */
11132 	MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE,
11133 	/* Last data transfer completed, applying magic pattern. */
11134 	MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7,
11135 	MLXSW_REG_MBCT_STATUS_INI_ERROR,
11136 	MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED,
11137 	MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11,
11138 };
11139 
11140 /* reg_mbct_status
11141  * Status.
11142  * Access: RO
11143  */
11144 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5);
11145 
11146 enum mlxsw_reg_mbct_fsm_state {
11147 	MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5,
11148 	MLXSW_REG_MBCT_FSM_STATE_ERROR,
11149 };
11150 
11151 /* reg_mbct_fsm_state
11152  * FSM state.
11153  * Access: RO
11154  */
11155 MLXSW_ITEM32(reg, mbct, fsm_state,  0x0C, 16, 4);
11156 
11157 #define MLXSW_REG_MBCT_DATA_LEN 1024
11158 
11159 /* reg_mbct_data
11160  * Up to 1KB of data.
11161  * Access: WO
11162  */
11163 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN);
11164 
mlxsw_reg_mbct_pack(char * payload,u8 slot_index,enum mlxsw_reg_mbct_op op,bool oee)11165 static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index,
11166 				       enum mlxsw_reg_mbct_op op, bool oee)
11167 {
11168 	MLXSW_REG_ZERO(mbct, payload);
11169 	mlxsw_reg_mbct_slot_index_set(payload, slot_index);
11170 	mlxsw_reg_mbct_op_set(payload, op);
11171 	mlxsw_reg_mbct_oee_set(payload, oee);
11172 }
11173 
mlxsw_reg_mbct_dt_pack(char * payload,u16 data_size,bool last,const char * data)11174 static inline void mlxsw_reg_mbct_dt_pack(char *payload,
11175 					  u16 data_size, bool last,
11176 					  const char *data)
11177 {
11178 	if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN))
11179 		return;
11180 	mlxsw_reg_mbct_data_size_set(payload, data_size);
11181 	mlxsw_reg_mbct_last_set(payload, last);
11182 	mlxsw_reg_mbct_data_memcpy_to(payload, data);
11183 }
11184 
11185 static inline void
mlxsw_reg_mbct_unpack(const char * payload,u8 * p_slot_index,enum mlxsw_reg_mbct_status * p_status,enum mlxsw_reg_mbct_fsm_state * p_fsm_state)11186 mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index,
11187 		      enum mlxsw_reg_mbct_status *p_status,
11188 		      enum mlxsw_reg_mbct_fsm_state *p_fsm_state)
11189 {
11190 	if (p_slot_index)
11191 		*p_slot_index = mlxsw_reg_mbct_slot_index_get(payload);
11192 	*p_status = mlxsw_reg_mbct_status_get(payload);
11193 	if (p_fsm_state)
11194 		*p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload);
11195 }
11196 
11197 /* MDDT - Management DownStream Device Tunneling Register
11198  * ------------------------------------------------------
11199  * This register allows to deliver query and request messages (PRM registers,
11200  * commands) to a DownStream device.
11201  */
11202 #define MLXSW_REG_MDDT_ID 0x9160
11203 #define MLXSW_REG_MDDT_LEN 0x110
11204 
11205 MLXSW_REG_DEFINE(mddt, MLXSW_REG_MDDT_ID, MLXSW_REG_MDDT_LEN);
11206 
11207 /* reg_mddt_slot_index
11208  * Slot index.
11209  * Access: Index
11210  */
11211 MLXSW_ITEM32(reg, mddt, slot_index, 0x00, 8, 4);
11212 
11213 /* reg_mddt_device_index
11214  * Device index.
11215  * Access: Index
11216  */
11217 MLXSW_ITEM32(reg, mddt, device_index, 0x00, 0, 8);
11218 
11219 /* reg_mddt_read_size
11220  * Read size in D-Words.
11221  * Access: OP
11222  */
11223 MLXSW_ITEM32(reg, mddt, read_size, 0x04, 24, 8);
11224 
11225 /* reg_mddt_write_size
11226  * Write size in D-Words.
11227  * Access: OP
11228  */
11229 MLXSW_ITEM32(reg, mddt, write_size, 0x04, 16, 8);
11230 
11231 enum mlxsw_reg_mddt_status {
11232 	MLXSW_REG_MDDT_STATUS_OK,
11233 };
11234 
11235 /* reg_mddt_status
11236  * Return code of the Downstream Device to the register that was sent.
11237  * Access: RO
11238  */
11239 MLXSW_ITEM32(reg, mddt, status, 0x0C, 24, 8);
11240 
11241 enum mlxsw_reg_mddt_method {
11242 	MLXSW_REG_MDDT_METHOD_QUERY,
11243 	MLXSW_REG_MDDT_METHOD_WRITE,
11244 };
11245 
11246 /* reg_mddt_method
11247  * Access: OP
11248  */
11249 MLXSW_ITEM32(reg, mddt, method, 0x0C, 22, 2);
11250 
11251 /* reg_mddt_register_id
11252  * Access: Index
11253  */
11254 MLXSW_ITEM32(reg, mddt, register_id, 0x0C, 0, 16);
11255 
11256 #define MLXSW_REG_MDDT_PAYLOAD_OFFSET 0x0C
11257 #define MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN 4
11258 
mlxsw_reg_mddt_inner_payload(char * payload)11259 static inline char *mlxsw_reg_mddt_inner_payload(char *payload)
11260 {
11261 	return payload + MLXSW_REG_MDDT_PAYLOAD_OFFSET +
11262 	       MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN;
11263 }
11264 
mlxsw_reg_mddt_pack(char * payload,u8 slot_index,u8 device_index,enum mlxsw_reg_mddt_method method,const struct mlxsw_reg_info * reg,char ** inner_payload)11265 static inline void mlxsw_reg_mddt_pack(char *payload, u8 slot_index,
11266 				       u8 device_index,
11267 				       enum mlxsw_reg_mddt_method method,
11268 				       const struct mlxsw_reg_info *reg,
11269 				       char **inner_payload)
11270 {
11271 	int len = reg->len + MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN;
11272 
11273 	if (WARN_ON(len + MLXSW_REG_MDDT_PAYLOAD_OFFSET > MLXSW_REG_MDDT_LEN))
11274 		len = MLXSW_REG_MDDT_LEN - MLXSW_REG_MDDT_PAYLOAD_OFFSET;
11275 
11276 	MLXSW_REG_ZERO(mddt, payload);
11277 	mlxsw_reg_mddt_slot_index_set(payload, slot_index);
11278 	mlxsw_reg_mddt_device_index_set(payload, device_index);
11279 	mlxsw_reg_mddt_method_set(payload, method);
11280 	mlxsw_reg_mddt_register_id_set(payload, reg->id);
11281 	mlxsw_reg_mddt_read_size_set(payload, len / 4);
11282 	mlxsw_reg_mddt_write_size_set(payload, len / 4);
11283 	*inner_payload = mlxsw_reg_mddt_inner_payload(payload);
11284 }
11285 
11286 /* MDDQ - Management DownStream Device Query Register
11287  * --------------------------------------------------
11288  * This register allows to query the DownStream device properties. The desired
11289  * information is chosen upon the query_type field and is delivered by 32B
11290  * of data blocks.
11291  */
11292 #define MLXSW_REG_MDDQ_ID 0x9161
11293 #define MLXSW_REG_MDDQ_LEN 0x30
11294 
11295 MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN);
11296 
11297 /* reg_mddq_sie
11298  * Slot info event enable.
11299  * When set to '1', each change in the slot_info.provisioned / sr_valid /
11300  * active / ready will generate a DSDSC event.
11301  * Access: RW
11302  */
11303 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1);
11304 
11305 enum mlxsw_reg_mddq_query_type {
11306 	MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1,
11307 	MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO, /* If there are no devices
11308 						* on the slot, data_valid
11309 						* will be '0'.
11310 						*/
11311 	MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME,
11312 };
11313 
11314 /* reg_mddq_query_type
11315  * Access: Index
11316  */
11317 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8);
11318 
11319 /* reg_mddq_slot_index
11320  * Slot index. 0 is reserved.
11321  * Access: Index
11322  */
11323 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4);
11324 
11325 /* reg_mddq_response_msg_seq
11326  * Response message sequential number. For a specific request, the response
11327  * message sequential number is the following one. In addition, the last
11328  * message should be 0.
11329  * Access: RO
11330  */
11331 MLXSW_ITEM32(reg, mddq, response_msg_seq, 0x04, 16, 8);
11332 
11333 /* reg_mddq_request_msg_seq
11334  * Request message sequential number.
11335  * The first message number should be 0.
11336  * Access: Index
11337  */
11338 MLXSW_ITEM32(reg, mddq, request_msg_seq, 0x04, 0, 8);
11339 
11340 /* reg_mddq_data_valid
11341  * If set, the data in the data field is valid and contain the information
11342  * for the queried index.
11343  * Access: RO
11344  */
11345 MLXSW_ITEM32(reg, mddq, data_valid, 0x08, 31, 1);
11346 
11347 /* reg_mddq_slot_info_provisioned
11348  * If set, the INI file is applied and the card is provisioned.
11349  * Access: RO
11350  */
11351 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1);
11352 
11353 /* reg_mddq_slot_info_sr_valid
11354  * If set, Shift Register is valid (after being provisioned) and data
11355  * can be sent from the switch ASIC to the line-card CPLD over Shift-Register.
11356  * Access: RO
11357  */
11358 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1);
11359 
11360 enum mlxsw_reg_mddq_slot_info_ready {
11361 	MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY,
11362 	MLXSW_REG_MDDQ_SLOT_INFO_READY_READY,
11363 	MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR,
11364 };
11365 
11366 /* reg_mddq_slot_info_lc_ready
11367  * If set, the LC is powered on, matching the INI version and a new FW
11368  * version can be burnt (if necessary).
11369  * Access: RO
11370  */
11371 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2);
11372 
11373 /* reg_mddq_slot_info_active
11374  * If set, the FW has completed the MDDC.device_enable command.
11375  * Access: RO
11376  */
11377 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1);
11378 
11379 /* reg_mddq_slot_info_hw_revision
11380  * Major user-configured version number of the current INI file.
11381  * Valid only when active or ready are '1'.
11382  * Access: RO
11383  */
11384 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16);
11385 
11386 /* reg_mddq_slot_info_ini_file_version
11387  * User-configured version number of the current INI file.
11388  * Valid only when active or lc_ready are '1'.
11389  * Access: RO
11390  */
11391 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16);
11392 
11393 /* reg_mddq_slot_info_card_type
11394  * Access: RO
11395  */
11396 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8);
11397 
11398 static inline void
__mlxsw_reg_mddq_pack(char * payload,u8 slot_index,enum mlxsw_reg_mddq_query_type query_type)11399 __mlxsw_reg_mddq_pack(char *payload, u8 slot_index,
11400 		      enum mlxsw_reg_mddq_query_type query_type)
11401 {
11402 	MLXSW_REG_ZERO(mddq, payload);
11403 	mlxsw_reg_mddq_slot_index_set(payload, slot_index);
11404 	mlxsw_reg_mddq_query_type_set(payload, query_type);
11405 }
11406 
11407 static inline void
mlxsw_reg_mddq_slot_info_pack(char * payload,u8 slot_index,bool sie)11408 mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie)
11409 {
11410 	__mlxsw_reg_mddq_pack(payload, slot_index,
11411 			      MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO);
11412 	mlxsw_reg_mddq_sie_set(payload, sie);
11413 }
11414 
11415 static inline void
mlxsw_reg_mddq_slot_info_unpack(const char * payload,u8 * p_slot_index,bool * p_provisioned,bool * p_sr_valid,enum mlxsw_reg_mddq_slot_info_ready * p_lc_ready,bool * p_active,u16 * p_hw_revision,u16 * p_ini_file_version,u8 * p_card_type)11416 mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index,
11417 				bool *p_provisioned, bool *p_sr_valid,
11418 				enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready,
11419 				bool *p_active, u16 *p_hw_revision,
11420 				u16 *p_ini_file_version,
11421 				u8 *p_card_type)
11422 {
11423 	*p_slot_index = mlxsw_reg_mddq_slot_index_get(payload);
11424 	*p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload);
11425 	*p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload);
11426 	*p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload);
11427 	*p_active = mlxsw_reg_mddq_slot_info_active_get(payload);
11428 	*p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload);
11429 	*p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload);
11430 	*p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload);
11431 }
11432 
11433 /* reg_mddq_device_info_flash_owner
11434  * If set, the device is the flash owner. Otherwise, a shared flash
11435  * is used by this device (another device is the flash owner).
11436  * Access: RO
11437  */
11438 MLXSW_ITEM32(reg, mddq, device_info_flash_owner, 0x10, 30, 1);
11439 
11440 /* reg_mddq_device_info_device_index
11441  * Device index. The first device should number 0.
11442  * Access: RO
11443  */
11444 MLXSW_ITEM32(reg, mddq, device_info_device_index, 0x10, 0, 8);
11445 
11446 /* reg_mddq_device_info_fw_major
11447  * Major FW version number.
11448  * Access: RO
11449  */
11450 MLXSW_ITEM32(reg, mddq, device_info_fw_major, 0x14, 16, 16);
11451 
11452 /* reg_mddq_device_info_fw_minor
11453  * Minor FW version number.
11454  * Access: RO
11455  */
11456 MLXSW_ITEM32(reg, mddq, device_info_fw_minor, 0x18, 16, 16);
11457 
11458 /* reg_mddq_device_info_fw_sub_minor
11459  * Sub-minor FW version number.
11460  * Access: RO
11461  */
11462 MLXSW_ITEM32(reg, mddq, device_info_fw_sub_minor, 0x18, 0, 16);
11463 
11464 static inline void
mlxsw_reg_mddq_device_info_pack(char * payload,u8 slot_index,u8 request_msg_seq)11465 mlxsw_reg_mddq_device_info_pack(char *payload, u8 slot_index,
11466 				u8 request_msg_seq)
11467 {
11468 	__mlxsw_reg_mddq_pack(payload, slot_index,
11469 			      MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO);
11470 	mlxsw_reg_mddq_request_msg_seq_set(payload, request_msg_seq);
11471 }
11472 
11473 static inline void
mlxsw_reg_mddq_device_info_unpack(const char * payload,u8 * p_response_msg_seq,bool * p_data_valid,bool * p_flash_owner,u8 * p_device_index,u16 * p_fw_major,u16 * p_fw_minor,u16 * p_fw_sub_minor)11474 mlxsw_reg_mddq_device_info_unpack(const char *payload, u8 *p_response_msg_seq,
11475 				  bool *p_data_valid, bool *p_flash_owner,
11476 				  u8 *p_device_index, u16 *p_fw_major,
11477 				  u16 *p_fw_minor, u16 *p_fw_sub_minor)
11478 {
11479 	*p_response_msg_seq = mlxsw_reg_mddq_response_msg_seq_get(payload);
11480 	*p_data_valid = mlxsw_reg_mddq_data_valid_get(payload);
11481 	*p_flash_owner = mlxsw_reg_mddq_device_info_flash_owner_get(payload);
11482 	*p_device_index = mlxsw_reg_mddq_device_info_device_index_get(payload);
11483 	*p_fw_major = mlxsw_reg_mddq_device_info_fw_major_get(payload);
11484 	*p_fw_minor = mlxsw_reg_mddq_device_info_fw_minor_get(payload);
11485 	*p_fw_sub_minor = mlxsw_reg_mddq_device_info_fw_sub_minor_get(payload);
11486 }
11487 
11488 #define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 20
11489 
11490 /* reg_mddq_slot_ascii_name
11491  * Slot's ASCII name.
11492  * Access: RO
11493  */
11494 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10,
11495 	       MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN);
11496 
11497 static inline void
mlxsw_reg_mddq_slot_name_pack(char * payload,u8 slot_index)11498 mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index)
11499 {
11500 	__mlxsw_reg_mddq_pack(payload, slot_index,
11501 			      MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME);
11502 }
11503 
11504 static inline void
mlxsw_reg_mddq_slot_name_unpack(const char * payload,char * slot_ascii_name)11505 mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name)
11506 {
11507 	mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name);
11508 }
11509 
11510 /* MDDC - Management DownStream Device Control Register
11511  * ----------------------------------------------------
11512  * This register allows to control downstream devices and line cards.
11513  */
11514 #define MLXSW_REG_MDDC_ID 0x9163
11515 #define MLXSW_REG_MDDC_LEN 0x30
11516 
11517 MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN);
11518 
11519 /* reg_mddc_slot_index
11520  * Slot index. 0 is reserved.
11521  * Access: Index
11522  */
11523 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4);
11524 
11525 /* reg_mddc_rst
11526  * Reset request.
11527  * Access: OP
11528  */
11529 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1);
11530 
11531 /* reg_mddc_device_enable
11532  * When set, FW is the manager and allowed to program the downstream device.
11533  * Access: RW
11534  */
11535 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1);
11536 
mlxsw_reg_mddc_pack(char * payload,u8 slot_index,bool rst,bool device_enable)11537 static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst,
11538 				       bool device_enable)
11539 {
11540 	MLXSW_REG_ZERO(mddc, payload);
11541 	mlxsw_reg_mddc_slot_index_set(payload, slot_index);
11542 	mlxsw_reg_mddc_rst_set(payload, rst);
11543 	mlxsw_reg_mddc_device_enable_set(payload, device_enable);
11544 }
11545 
11546 /* MFDE - Monitoring FW Debug Register
11547  * -----------------------------------
11548  */
11549 #define MLXSW_REG_MFDE_ID 0x9200
11550 #define MLXSW_REG_MFDE_LEN 0x30
11551 
11552 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN);
11553 
11554 /* reg_mfde_irisc_id
11555  * Which irisc triggered the event
11556  * Access: RO
11557  */
11558 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8);
11559 
11560 enum mlxsw_reg_mfde_severity {
11561 	/* Unrecoverable switch behavior */
11562 	MLXSW_REG_MFDE_SEVERITY_FATL = 2,
11563 	/* Unexpected state with possible systemic failure */
11564 	MLXSW_REG_MFDE_SEVERITY_NRML = 3,
11565 	/* Unexpected state without systemic failure */
11566 	MLXSW_REG_MFDE_SEVERITY_INTR = 5,
11567 };
11568 
11569 /* reg_mfde_severity
11570  * The severity of the event.
11571  * Access: RO
11572  */
11573 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8);
11574 
11575 enum mlxsw_reg_mfde_event_id {
11576 	/* CRspace timeout */
11577 	MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1,
11578 	/* KVD insertion machine stopped */
11579 	MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP,
11580 	/* Triggered by MFGD.trigger_test */
11581 	MLXSW_REG_MFDE_EVENT_ID_TEST,
11582 	/* Triggered when firmware hits an assert */
11583 	MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT,
11584 	/* Fatal error interrupt from hardware */
11585 	MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE,
11586 };
11587 
11588 /* reg_mfde_event_id
11589  * Access: RO
11590  */
11591 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16);
11592 
11593 enum mlxsw_reg_mfde_method {
11594 	MLXSW_REG_MFDE_METHOD_QUERY,
11595 	MLXSW_REG_MFDE_METHOD_WRITE,
11596 };
11597 
11598 /* reg_mfde_method
11599  * Access: RO
11600  */
11601 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1);
11602 
11603 /* reg_mfde_long_process
11604  * Indicates if the command is in long_process mode.
11605  * Access: RO
11606  */
11607 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1);
11608 
11609 enum mlxsw_reg_mfde_command_type {
11610 	MLXSW_REG_MFDE_COMMAND_TYPE_MAD,
11611 	MLXSW_REG_MFDE_COMMAND_TYPE_EMAD,
11612 	MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF,
11613 };
11614 
11615 /* reg_mfde_command_type
11616  * Access: RO
11617  */
11618 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2);
11619 
11620 /* reg_mfde_reg_attr_id
11621  * EMAD - register id, MAD - attibute id
11622  * Access: RO
11623  */
11624 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16);
11625 
11626 /* reg_mfde_crspace_to_log_address
11627  * crspace address accessed, which resulted in timeout.
11628  * Access: RO
11629  */
11630 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32);
11631 
11632 /* reg_mfde_crspace_to_oe
11633  * 0 - New event
11634  * 1 - Old event, occurred before MFGD activation.
11635  * Access: RO
11636  */
11637 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1);
11638 
11639 /* reg_mfde_crspace_to_log_id
11640  * Which irisc triggered the timeout.
11641  * Access: RO
11642  */
11643 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4);
11644 
11645 /* reg_mfde_crspace_to_log_ip
11646  * IP (instruction pointer) that triggered the timeout.
11647  * Access: RO
11648  */
11649 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64);
11650 
11651 /* reg_mfde_kvd_im_stop_oe
11652  * 0 - New event
11653  * 1 - Old event, occurred before MFGD activation.
11654  * Access: RO
11655  */
11656 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1);
11657 
11658 /* reg_mfde_kvd_im_stop_pipes_mask
11659  * Bit per kvh pipe.
11660  * Access: RO
11661  */
11662 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16);
11663 
11664 /* reg_mfde_fw_assert_var0-4
11665  * Variables passed to assert.
11666  * Access: RO
11667  */
11668 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32);
11669 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32);
11670 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32);
11671 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32);
11672 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32);
11673 
11674 /* reg_mfde_fw_assert_existptr
11675  * The instruction pointer when assert was triggered.
11676  * Access: RO
11677  */
11678 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32);
11679 
11680 /* reg_mfde_fw_assert_callra
11681  * The return address after triggering assert.
11682  * Access: RO
11683  */
11684 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32);
11685 
11686 /* reg_mfde_fw_assert_oe
11687  * 0 - New event
11688  * 1 - Old event, occurred before MFGD activation.
11689  * Access: RO
11690  */
11691 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1);
11692 
11693 /* reg_mfde_fw_assert_tile_v
11694  * 0: The assert was from main
11695  * 1: The assert was from a tile
11696  * Access: RO
11697  */
11698 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1);
11699 
11700 /* reg_mfde_fw_assert_tile_index
11701  * When tile_v=1, the tile_index that caused the assert.
11702  * Access: RO
11703  */
11704 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6);
11705 
11706 /* reg_mfde_fw_assert_ext_synd
11707  * A generated one-to-one identifier which is specific per-assert.
11708  * Access: RO
11709  */
11710 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16);
11711 
11712 /* reg_mfde_fatal_cause_id
11713  * HW interrupt cause id.
11714  * Access: RO
11715  */
11716 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18);
11717 
11718 /* reg_mfde_fatal_cause_tile_v
11719  * 0: The assert was from main
11720  * 1: The assert was from a tile
11721  * Access: RO
11722  */
11723 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1);
11724 
11725 /* reg_mfde_fatal_cause_tile_index
11726  * When tile_v=1, the tile_index that caused the assert.
11727  * Access: RO
11728  */
11729 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6);
11730 
11731 /* TNGCR - Tunneling NVE General Configuration Register
11732  * ----------------------------------------------------
11733  * The TNGCR register is used for setting up the NVE Tunneling configuration.
11734  */
11735 #define MLXSW_REG_TNGCR_ID 0xA001
11736 #define MLXSW_REG_TNGCR_LEN 0x44
11737 
11738 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
11739 
11740 enum mlxsw_reg_tngcr_type {
11741 	MLXSW_REG_TNGCR_TYPE_VXLAN,
11742 	MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
11743 	MLXSW_REG_TNGCR_TYPE_GENEVE,
11744 	MLXSW_REG_TNGCR_TYPE_NVGRE,
11745 };
11746 
11747 /* reg_tngcr_type
11748  * Tunnel type for encapsulation and decapsulation. The types are mutually
11749  * exclusive.
11750  * Note: For Spectrum the NVE parsing must be enabled in MPRS.
11751  * Access: RW
11752  */
11753 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
11754 
11755 /* reg_tngcr_nve_valid
11756  * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation.
11757  * Access: RW
11758  */
11759 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
11760 
11761 /* reg_tngcr_nve_ttl_uc
11762  * The TTL for NVE tunnel encapsulation underlay unicast packets.
11763  * Access: RW
11764  */
11765 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
11766 
11767 /* reg_tngcr_nve_ttl_mc
11768  * The TTL for NVE tunnel encapsulation underlay multicast packets.
11769  * Access: RW
11770  */
11771 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
11772 
11773 enum {
11774 	/* Do not copy flow label. Calculate flow label using nve_flh. */
11775 	MLXSW_REG_TNGCR_FL_NO_COPY,
11776 	/* Copy flow label from inner packet if packet is IPv6 and
11777 	 * encapsulation is by IPv6. Otherwise, calculate flow label using
11778 	 * nve_flh.
11779 	 */
11780 	MLXSW_REG_TNGCR_FL_COPY,
11781 };
11782 
11783 /* reg_tngcr_nve_flc
11784  * For NVE tunnel encapsulation: Flow label copy from inner packet.
11785  * Access: RW
11786  */
11787 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
11788 
11789 enum {
11790 	/* Flow label is static. In Spectrum this means '0'. Spectrum-2
11791 	 * uses {nve_fl_prefix, nve_fl_suffix}.
11792 	 */
11793 	MLXSW_REG_TNGCR_FL_NO_HASH,
11794 	/* 8 LSBs of the flow label are calculated from ECMP hash of the
11795 	 * inner packet. 12 MSBs are configured by nve_fl_prefix.
11796 	 */
11797 	MLXSW_REG_TNGCR_FL_HASH,
11798 };
11799 
11800 /* reg_tngcr_nve_flh
11801  * NVE flow label hash.
11802  * Access: RW
11803  */
11804 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
11805 
11806 /* reg_tngcr_nve_fl_prefix
11807  * NVE flow label prefix. Constant 12 MSBs of the flow label.
11808  * Access: RW
11809  */
11810 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
11811 
11812 /* reg_tngcr_nve_fl_suffix
11813  * NVE flow label suffix. Constant 8 LSBs of the flow label.
11814  * Reserved when nve_flh=1 and for Spectrum.
11815  * Access: RW
11816  */
11817 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
11818 
11819 enum {
11820 	/* Source UDP port is fixed (default '0') */
11821 	MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
11822 	/* Source UDP port is calculated based on hash */
11823 	MLXSW_REG_TNGCR_UDP_SPORT_HASH,
11824 };
11825 
11826 /* reg_tngcr_nve_udp_sport_type
11827  * NVE UDP source port type.
11828  * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2).
11829  * When the source UDP port is calculated based on hash, then the 8 LSBs
11830  * are calculated from hash the 8 MSBs are configured by
11831  * nve_udp_sport_prefix.
11832  * Access: RW
11833  */
11834 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
11835 
11836 /* reg_tngcr_nve_udp_sport_prefix
11837  * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port.
11838  * Reserved when NVE type is NVGRE.
11839  * Access: RW
11840  */
11841 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
11842 
11843 /* reg_tngcr_nve_group_size_mc
11844  * The amount of sequential linked lists of MC entries. The first linked
11845  * list is configured by SFD.underlay_mc_ptr.
11846  * Valid values: 1, 2, 4, 8, 16, 32, 64
11847  * The linked list are configured by TNUMT.
11848  * The hash is set by LAG hash.
11849  * Access: RW
11850  */
11851 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
11852 
11853 /* reg_tngcr_nve_group_size_flood
11854  * The amount of sequential linked lists of flooding entries. The first
11855  * linked list is configured by SFMR.nve_tunnel_flood_ptr
11856  * Valid values: 1, 2, 4, 8, 16, 32, 64
11857  * The linked list are configured by TNUMT.
11858  * The hash is set by LAG hash.
11859  * Access: RW
11860  */
11861 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
11862 
11863 /* reg_tngcr_learn_enable
11864  * During decapsulation, whether to learn from NVE port.
11865  * Reserved when Spectrum-2. See TNPC.
11866  * Access: RW
11867  */
11868 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
11869 
11870 /* reg_tngcr_underlay_virtual_router
11871  * Underlay virtual router.
11872  * Reserved when Spectrum-2.
11873  * Access: RW
11874  */
11875 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
11876 
11877 /* reg_tngcr_underlay_rif
11878  * Underlay ingress router interface. RIF type should be loopback generic.
11879  * Reserved when Spectrum.
11880  * Access: RW
11881  */
11882 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
11883 
11884 /* reg_tngcr_usipv4
11885  * Underlay source IPv4 address of the NVE.
11886  * Access: RW
11887  */
11888 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
11889 
11890 /* reg_tngcr_usipv6
11891  * Underlay source IPv6 address of the NVE. For Spectrum, must not be
11892  * modified under traffic of NVE tunneling encapsulation.
11893  * Access: RW
11894  */
11895 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
11896 
mlxsw_reg_tngcr_pack(char * payload,enum mlxsw_reg_tngcr_type type,bool valid,u8 ttl)11897 static inline void mlxsw_reg_tngcr_pack(char *payload,
11898 					enum mlxsw_reg_tngcr_type type,
11899 					bool valid, u8 ttl)
11900 {
11901 	MLXSW_REG_ZERO(tngcr, payload);
11902 	mlxsw_reg_tngcr_type_set(payload, type);
11903 	mlxsw_reg_tngcr_nve_valid_set(payload, valid);
11904 	mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
11905 	mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
11906 	mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
11907 	mlxsw_reg_tngcr_nve_flh_set(payload, 0);
11908 	mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
11909 					       MLXSW_REG_TNGCR_UDP_SPORT_HASH);
11910 	mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
11911 	mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
11912 	mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
11913 }
11914 
11915 /* TNUMT - Tunneling NVE Underlay Multicast Table Register
11916  * -------------------------------------------------------
11917  * The TNUMT register is for building the underlay MC table. It is used
11918  * for MC, flooding and BC traffic into the NVE tunnel.
11919  */
11920 #define MLXSW_REG_TNUMT_ID 0xA003
11921 #define MLXSW_REG_TNUMT_LEN 0x20
11922 
11923 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
11924 
11925 enum mlxsw_reg_tnumt_record_type {
11926 	MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
11927 	MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
11928 	MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
11929 };
11930 
11931 /* reg_tnumt_record_type
11932  * Record type.
11933  * Access: RW
11934  */
11935 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
11936 
11937 /* reg_tnumt_tunnel_port
11938  * Tunnel port.
11939  * Access: RW
11940  */
11941 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
11942 
11943 /* reg_tnumt_underlay_mc_ptr
11944  * Index to the underlay multicast table.
11945  * For Spectrum the index is to the KVD linear.
11946  * Access: Index
11947  */
11948 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
11949 
11950 /* reg_tnumt_vnext
11951  * The next_underlay_mc_ptr is valid.
11952  * Access: RW
11953  */
11954 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
11955 
11956 /* reg_tnumt_next_underlay_mc_ptr
11957  * The next index to the underlay multicast table.
11958  * Access: RW
11959  */
11960 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
11961 
11962 /* reg_tnumt_record_size
11963  * Number of IP addresses in the record.
11964  * Range is 1..cap_max_nve_mc_entries_ipv{4,6}
11965  * Access: RW
11966  */
11967 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
11968 
11969 /* reg_tnumt_udip
11970  * The underlay IPv4 addresses. udip[i] is reserved if i >= size
11971  * Access: RW
11972  */
11973 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
11974 
11975 /* reg_tnumt_udip_ptr
11976  * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if
11977  * i >= size. The IPv6 addresses are configured by RIPS.
11978  * Access: RW
11979  */
11980 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
11981 
mlxsw_reg_tnumt_pack(char * payload,enum mlxsw_reg_tnumt_record_type type,enum mlxsw_reg_tunnel_port tport,u32 underlay_mc_ptr,bool vnext,u32 next_underlay_mc_ptr,u8 record_size)11982 static inline void mlxsw_reg_tnumt_pack(char *payload,
11983 					enum mlxsw_reg_tnumt_record_type type,
11984 					enum mlxsw_reg_tunnel_port tport,
11985 					u32 underlay_mc_ptr, bool vnext,
11986 					u32 next_underlay_mc_ptr,
11987 					u8 record_size)
11988 {
11989 	MLXSW_REG_ZERO(tnumt, payload);
11990 	mlxsw_reg_tnumt_record_type_set(payload, type);
11991 	mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
11992 	mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
11993 	mlxsw_reg_tnumt_vnext_set(payload, vnext);
11994 	mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
11995 	mlxsw_reg_tnumt_record_size_set(payload, record_size);
11996 }
11997 
11998 /* TNQCR - Tunneling NVE QoS Configuration Register
11999  * ------------------------------------------------
12000  * The TNQCR register configures how QoS is set in encapsulation into the
12001  * underlay network.
12002  */
12003 #define MLXSW_REG_TNQCR_ID 0xA010
12004 #define MLXSW_REG_TNQCR_LEN 0x0C
12005 
12006 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
12007 
12008 /* reg_tnqcr_enc_set_dscp
12009  * For encapsulation: How to set DSCP field:
12010  * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay
12011  * (outer) IP header. If there is no IP header, use TNQDR.dscp
12012  * 1 - Set the DSCP field as TNQDR.dscp
12013  * Access: RW
12014  */
12015 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
12016 
mlxsw_reg_tnqcr_pack(char * payload)12017 static inline void mlxsw_reg_tnqcr_pack(char *payload)
12018 {
12019 	MLXSW_REG_ZERO(tnqcr, payload);
12020 	mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
12021 }
12022 
12023 /* TNQDR - Tunneling NVE QoS Default Register
12024  * ------------------------------------------
12025  * The TNQDR register configures the default QoS settings for NVE
12026  * encapsulation.
12027  */
12028 #define MLXSW_REG_TNQDR_ID 0xA011
12029 #define MLXSW_REG_TNQDR_LEN 0x08
12030 
12031 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
12032 
12033 /* reg_tnqdr_local_port
12034  * Local port number (receive port). CPU port is supported.
12035  * Access: Index
12036  */
12037 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12);
12038 
12039 /* reg_tnqdr_dscp
12040  * For encapsulation, the default DSCP.
12041  * Access: RW
12042  */
12043 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
12044 
mlxsw_reg_tnqdr_pack(char * payload,u16 local_port)12045 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port)
12046 {
12047 	MLXSW_REG_ZERO(tnqdr, payload);
12048 	mlxsw_reg_tnqdr_local_port_set(payload, local_port);
12049 	mlxsw_reg_tnqdr_dscp_set(payload, 0);
12050 }
12051 
12052 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
12053  * --------------------------------------------------------
12054  * The TNEEM register maps ECN of the IP header at the ingress to the
12055  * encapsulation to the ECN of the underlay network.
12056  */
12057 #define MLXSW_REG_TNEEM_ID 0xA012
12058 #define MLXSW_REG_TNEEM_LEN 0x0C
12059 
12060 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
12061 
12062 /* reg_tneem_overlay_ecn
12063  * ECN of the IP header in the overlay network.
12064  * Access: Index
12065  */
12066 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
12067 
12068 /* reg_tneem_underlay_ecn
12069  * ECN of the IP header in the underlay network.
12070  * Access: RW
12071  */
12072 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
12073 
mlxsw_reg_tneem_pack(char * payload,u8 overlay_ecn,u8 underlay_ecn)12074 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
12075 					u8 underlay_ecn)
12076 {
12077 	MLXSW_REG_ZERO(tneem, payload);
12078 	mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
12079 	mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
12080 }
12081 
12082 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register
12083  * --------------------------------------------------------
12084  * The TNDEM register configures the actions that are done in the
12085  * decapsulation.
12086  */
12087 #define MLXSW_REG_TNDEM_ID 0xA013
12088 #define MLXSW_REG_TNDEM_LEN 0x0C
12089 
12090 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
12091 
12092 /* reg_tndem_underlay_ecn
12093  * ECN field of the IP header in the underlay network.
12094  * Access: Index
12095  */
12096 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
12097 
12098 /* reg_tndem_overlay_ecn
12099  * ECN field of the IP header in the overlay network.
12100  * Access: Index
12101  */
12102 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
12103 
12104 /* reg_tndem_eip_ecn
12105  * Egress IP ECN. ECN field of the IP header of the packet which goes out
12106  * from the decapsulation.
12107  * Access: RW
12108  */
12109 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
12110 
12111 /* reg_tndem_trap_en
12112  * Trap enable:
12113  * 0 - No trap due to decap ECN
12114  * 1 - Trap enable with trap_id
12115  * Access: RW
12116  */
12117 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
12118 
12119 /* reg_tndem_trap_id
12120  * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
12121  * Reserved when trap_en is '0'.
12122  * Access: RW
12123  */
12124 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
12125 
mlxsw_reg_tndem_pack(char * payload,u8 underlay_ecn,u8 overlay_ecn,u8 ecn,bool trap_en,u16 trap_id)12126 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
12127 					u8 overlay_ecn, u8 ecn, bool trap_en,
12128 					u16 trap_id)
12129 {
12130 	MLXSW_REG_ZERO(tndem, payload);
12131 	mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
12132 	mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
12133 	mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
12134 	mlxsw_reg_tndem_trap_en_set(payload, trap_en);
12135 	mlxsw_reg_tndem_trap_id_set(payload, trap_id);
12136 }
12137 
12138 /* TNPC - Tunnel Port Configuration Register
12139  * -----------------------------------------
12140  * The TNPC register is used for tunnel port configuration.
12141  * Reserved when Spectrum.
12142  */
12143 #define MLXSW_REG_TNPC_ID 0xA020
12144 #define MLXSW_REG_TNPC_LEN 0x18
12145 
12146 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
12147 
12148 /* reg_tnpc_tunnel_port
12149  * Tunnel port.
12150  * Access: Index
12151  */
12152 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
12153 
12154 /* reg_tnpc_learn_enable_v6
12155  * During IPv6 underlay decapsulation, whether to learn from tunnel port.
12156  * Access: RW
12157  */
12158 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
12159 
12160 /* reg_tnpc_learn_enable_v4
12161  * During IPv4 underlay decapsulation, whether to learn from tunnel port.
12162  * Access: RW
12163  */
12164 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
12165 
mlxsw_reg_tnpc_pack(char * payload,enum mlxsw_reg_tunnel_port tport,bool learn_enable)12166 static inline void mlxsw_reg_tnpc_pack(char *payload,
12167 				       enum mlxsw_reg_tunnel_port tport,
12168 				       bool learn_enable)
12169 {
12170 	MLXSW_REG_ZERO(tnpc, payload);
12171 	mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
12172 	mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
12173 	mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
12174 }
12175 
12176 /* TIGCR - Tunneling IPinIP General Configuration Register
12177  * -------------------------------------------------------
12178  * The TIGCR register is used for setting up the IPinIP Tunnel configuration.
12179  */
12180 #define MLXSW_REG_TIGCR_ID 0xA801
12181 #define MLXSW_REG_TIGCR_LEN 0x10
12182 
12183 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
12184 
12185 /* reg_tigcr_ipip_ttlc
12186  * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet
12187  * header.
12188  * Access: RW
12189  */
12190 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
12191 
12192 /* reg_tigcr_ipip_ttl_uc
12193  * The TTL for IPinIP Tunnel encapsulation of unicast packets if
12194  * reg_tigcr_ipip_ttlc is unset.
12195  * Access: RW
12196  */
12197 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
12198 
mlxsw_reg_tigcr_pack(char * payload,bool ttlc,u8 ttl_uc)12199 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
12200 {
12201 	MLXSW_REG_ZERO(tigcr, payload);
12202 	mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
12203 	mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
12204 }
12205 
12206 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register
12207  * -----------------------------------------------------------
12208  * The TIEEM register maps ECN of the IP header at the ingress to the
12209  * encapsulation to the ECN of the underlay network.
12210  */
12211 #define MLXSW_REG_TIEEM_ID 0xA812
12212 #define MLXSW_REG_TIEEM_LEN 0x0C
12213 
12214 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN);
12215 
12216 /* reg_tieem_overlay_ecn
12217  * ECN of the IP header in the overlay network.
12218  * Access: Index
12219  */
12220 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2);
12221 
12222 /* reg_tineem_underlay_ecn
12223  * ECN of the IP header in the underlay network.
12224  * Access: RW
12225  */
12226 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2);
12227 
mlxsw_reg_tieem_pack(char * payload,u8 overlay_ecn,u8 underlay_ecn)12228 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn,
12229 					u8 underlay_ecn)
12230 {
12231 	MLXSW_REG_ZERO(tieem, payload);
12232 	mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn);
12233 	mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn);
12234 }
12235 
12236 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register
12237  * -----------------------------------------------------------
12238  * The TIDEM register configures the actions that are done in the
12239  * decapsulation.
12240  */
12241 #define MLXSW_REG_TIDEM_ID 0xA813
12242 #define MLXSW_REG_TIDEM_LEN 0x0C
12243 
12244 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN);
12245 
12246 /* reg_tidem_underlay_ecn
12247  * ECN field of the IP header in the underlay network.
12248  * Access: Index
12249  */
12250 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2);
12251 
12252 /* reg_tidem_overlay_ecn
12253  * ECN field of the IP header in the overlay network.
12254  * Access: Index
12255  */
12256 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2);
12257 
12258 /* reg_tidem_eip_ecn
12259  * Egress IP ECN. ECN field of the IP header of the packet which goes out
12260  * from the decapsulation.
12261  * Access: RW
12262  */
12263 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2);
12264 
12265 /* reg_tidem_trap_en
12266  * Trap enable:
12267  * 0 - No trap due to decap ECN
12268  * 1 - Trap enable with trap_id
12269  * Access: RW
12270  */
12271 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4);
12272 
12273 /* reg_tidem_trap_id
12274  * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
12275  * Reserved when trap_en is '0'.
12276  * Access: RW
12277  */
12278 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9);
12279 
mlxsw_reg_tidem_pack(char * payload,u8 underlay_ecn,u8 overlay_ecn,u8 eip_ecn,bool trap_en,u16 trap_id)12280 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn,
12281 					u8 overlay_ecn, u8 eip_ecn,
12282 					bool trap_en, u16 trap_id)
12283 {
12284 	MLXSW_REG_ZERO(tidem, payload);
12285 	mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn);
12286 	mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn);
12287 	mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn);
12288 	mlxsw_reg_tidem_trap_en_set(payload, trap_en);
12289 	mlxsw_reg_tidem_trap_id_set(payload, trap_id);
12290 }
12291 
12292 /* SBPR - Shared Buffer Pools Register
12293  * -----------------------------------
12294  * The SBPR configures and retrieves the shared buffer pools and configuration.
12295  */
12296 #define MLXSW_REG_SBPR_ID 0xB001
12297 #define MLXSW_REG_SBPR_LEN 0x14
12298 
12299 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
12300 
12301 /* reg_sbpr_desc
12302  * When set, configures descriptor buffer.
12303  * Access: Index
12304  */
12305 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1);
12306 
12307 /* shared direstion enum for SBPR, SBCM, SBPM */
12308 enum mlxsw_reg_sbxx_dir {
12309 	MLXSW_REG_SBXX_DIR_INGRESS,
12310 	MLXSW_REG_SBXX_DIR_EGRESS,
12311 };
12312 
12313 /* reg_sbpr_dir
12314  * Direction.
12315  * Access: Index
12316  */
12317 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
12318 
12319 /* reg_sbpr_pool
12320  * Pool index.
12321  * Access: Index
12322  */
12323 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
12324 
12325 /* reg_sbpr_infi_size
12326  * Size is infinite.
12327  * Access: RW
12328  */
12329 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
12330 
12331 /* reg_sbpr_size
12332  * Pool size in buffer cells.
12333  * Reserved when infi_size = 1.
12334  * Access: RW
12335  */
12336 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
12337 
12338 enum mlxsw_reg_sbpr_mode {
12339 	MLXSW_REG_SBPR_MODE_STATIC,
12340 	MLXSW_REG_SBPR_MODE_DYNAMIC,
12341 };
12342 
12343 /* reg_sbpr_mode
12344  * Pool quota calculation mode.
12345  * Access: RW
12346  */
12347 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
12348 
mlxsw_reg_sbpr_pack(char * payload,u8 pool,enum mlxsw_reg_sbxx_dir dir,enum mlxsw_reg_sbpr_mode mode,u32 size,bool infi_size)12349 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
12350 				       enum mlxsw_reg_sbxx_dir dir,
12351 				       enum mlxsw_reg_sbpr_mode mode, u32 size,
12352 				       bool infi_size)
12353 {
12354 	MLXSW_REG_ZERO(sbpr, payload);
12355 	mlxsw_reg_sbpr_pool_set(payload, pool);
12356 	mlxsw_reg_sbpr_dir_set(payload, dir);
12357 	mlxsw_reg_sbpr_mode_set(payload, mode);
12358 	mlxsw_reg_sbpr_size_set(payload, size);
12359 	mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
12360 }
12361 
12362 /* SBCM - Shared Buffer Class Management Register
12363  * ----------------------------------------------
12364  * The SBCM register configures and retrieves the shared buffer allocation
12365  * and configuration according to Port-PG, including the binding to pool
12366  * and definition of the associated quota.
12367  */
12368 #define MLXSW_REG_SBCM_ID 0xB002
12369 #define MLXSW_REG_SBCM_LEN 0x28
12370 
12371 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
12372 
12373 /* reg_sbcm_local_port
12374  * Local port number.
12375  * For Ingress: excludes CPU port and Router port
12376  * For Egress: excludes IP Router
12377  * Access: Index
12378  */
12379 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4);
12380 
12381 /* reg_sbcm_pg_buff
12382  * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
12383  * For PG buffer: range is 0..cap_max_pg_buffers - 1
12384  * For traffic class: range is 0..cap_max_tclass - 1
12385  * Note that when traffic class is in MC aware mode then the traffic
12386  * classes which are MC aware cannot be configured.
12387  * Access: Index
12388  */
12389 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
12390 
12391 /* reg_sbcm_dir
12392  * Direction.
12393  * Access: Index
12394  */
12395 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
12396 
12397 /* reg_sbcm_min_buff
12398  * Minimum buffer size for the limiter, in cells.
12399  * Access: RW
12400  */
12401 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
12402 
12403 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
12404 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
12405 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
12406 
12407 /* reg_sbcm_infi_max
12408  * Max buffer is infinite.
12409  * Access: RW
12410  */
12411 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
12412 
12413 /* reg_sbcm_max_buff
12414  * When the pool associated to the port-pg/tclass is configured to
12415  * static, Maximum buffer size for the limiter configured in cells.
12416  * When the pool associated to the port-pg/tclass is configured to
12417  * dynamic, the max_buff holds the "alpha" parameter, supporting
12418  * the following values:
12419  * 0: 0
12420  * i: (1/128)*2^(i-1), for i=1..14
12421  * 0xFF: Infinity
12422  * Reserved when infi_max = 1.
12423  * Access: RW
12424  */
12425 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
12426 
12427 /* reg_sbcm_pool
12428  * Association of the port-priority to a pool.
12429  * Access: RW
12430  */
12431 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
12432 
mlxsw_reg_sbcm_pack(char * payload,u16 local_port,u8 pg_buff,enum mlxsw_reg_sbxx_dir dir,u32 min_buff,u32 max_buff,bool infi_max,u8 pool)12433 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff,
12434 				       enum mlxsw_reg_sbxx_dir dir,
12435 				       u32 min_buff, u32 max_buff,
12436 				       bool infi_max, u8 pool)
12437 {
12438 	MLXSW_REG_ZERO(sbcm, payload);
12439 	mlxsw_reg_sbcm_local_port_set(payload, local_port);
12440 	mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
12441 	mlxsw_reg_sbcm_dir_set(payload, dir);
12442 	mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
12443 	mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
12444 	mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
12445 	mlxsw_reg_sbcm_pool_set(payload, pool);
12446 }
12447 
12448 /* SBPM - Shared Buffer Port Management Register
12449  * ---------------------------------------------
12450  * The SBPM register configures and retrieves the shared buffer allocation
12451  * and configuration according to Port-Pool, including the definition
12452  * of the associated quota.
12453  */
12454 #define MLXSW_REG_SBPM_ID 0xB003
12455 #define MLXSW_REG_SBPM_LEN 0x28
12456 
12457 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
12458 
12459 /* reg_sbpm_local_port
12460  * Local port number.
12461  * For Ingress: excludes CPU port and Router port
12462  * For Egress: excludes IP Router
12463  * Access: Index
12464  */
12465 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12);
12466 
12467 /* reg_sbpm_pool
12468  * The pool associated to quota counting on the local_port.
12469  * Access: Index
12470  */
12471 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
12472 
12473 /* reg_sbpm_dir
12474  * Direction.
12475  * Access: Index
12476  */
12477 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
12478 
12479 /* reg_sbpm_buff_occupancy
12480  * Current buffer occupancy in cells.
12481  * Access: RO
12482  */
12483 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
12484 
12485 /* reg_sbpm_clr
12486  * Clear Max Buffer Occupancy
12487  * When this bit is set, max_buff_occupancy field is cleared (and a
12488  * new max value is tracked from the time the clear was performed).
12489  * Access: OP
12490  */
12491 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
12492 
12493 /* reg_sbpm_max_buff_occupancy
12494  * Maximum value of buffer occupancy in cells monitored. Cleared by
12495  * writing to the clr field.
12496  * Access: RO
12497  */
12498 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
12499 
12500 /* reg_sbpm_min_buff
12501  * Minimum buffer size for the limiter, in cells.
12502  * Access: RW
12503  */
12504 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
12505 
12506 /* reg_sbpm_max_buff
12507  * When the pool associated to the port-pg/tclass is configured to
12508  * static, Maximum buffer size for the limiter configured in cells.
12509  * When the pool associated to the port-pg/tclass is configured to
12510  * dynamic, the max_buff holds the "alpha" parameter, supporting
12511  * the following values:
12512  * 0: 0
12513  * i: (1/128)*2^(i-1), for i=1..14
12514  * 0xFF: Infinity
12515  * Access: RW
12516  */
12517 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
12518 
mlxsw_reg_sbpm_pack(char * payload,u16 local_port,u8 pool,enum mlxsw_reg_sbxx_dir dir,bool clr,u32 min_buff,u32 max_buff)12519 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool,
12520 				       enum mlxsw_reg_sbxx_dir dir, bool clr,
12521 				       u32 min_buff, u32 max_buff)
12522 {
12523 	MLXSW_REG_ZERO(sbpm, payload);
12524 	mlxsw_reg_sbpm_local_port_set(payload, local_port);
12525 	mlxsw_reg_sbpm_pool_set(payload, pool);
12526 	mlxsw_reg_sbpm_dir_set(payload, dir);
12527 	mlxsw_reg_sbpm_clr_set(payload, clr);
12528 	mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
12529 	mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
12530 }
12531 
mlxsw_reg_sbpm_unpack(char * payload,u32 * p_buff_occupancy,u32 * p_max_buff_occupancy)12532 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
12533 					 u32 *p_max_buff_occupancy)
12534 {
12535 	*p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
12536 	*p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
12537 }
12538 
12539 /* SBMM - Shared Buffer Multicast Management Register
12540  * --------------------------------------------------
12541  * The SBMM register configures and retrieves the shared buffer allocation
12542  * and configuration for MC packets according to Switch-Priority, including
12543  * the binding to pool and definition of the associated quota.
12544  */
12545 #define MLXSW_REG_SBMM_ID 0xB004
12546 #define MLXSW_REG_SBMM_LEN 0x28
12547 
12548 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
12549 
12550 /* reg_sbmm_prio
12551  * Switch Priority.
12552  * Access: Index
12553  */
12554 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
12555 
12556 /* reg_sbmm_min_buff
12557  * Minimum buffer size for the limiter, in cells.
12558  * Access: RW
12559  */
12560 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
12561 
12562 /* reg_sbmm_max_buff
12563  * When the pool associated to the port-pg/tclass is configured to
12564  * static, Maximum buffer size for the limiter configured in cells.
12565  * When the pool associated to the port-pg/tclass is configured to
12566  * dynamic, the max_buff holds the "alpha" parameter, supporting
12567  * the following values:
12568  * 0: 0
12569  * i: (1/128)*2^(i-1), for i=1..14
12570  * 0xFF: Infinity
12571  * Access: RW
12572  */
12573 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
12574 
12575 /* reg_sbmm_pool
12576  * Association of the port-priority to a pool.
12577  * Access: RW
12578  */
12579 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
12580 
mlxsw_reg_sbmm_pack(char * payload,u8 prio,u32 min_buff,u32 max_buff,u8 pool)12581 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
12582 				       u32 max_buff, u8 pool)
12583 {
12584 	MLXSW_REG_ZERO(sbmm, payload);
12585 	mlxsw_reg_sbmm_prio_set(payload, prio);
12586 	mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
12587 	mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
12588 	mlxsw_reg_sbmm_pool_set(payload, pool);
12589 }
12590 
12591 /* SBSR - Shared Buffer Status Register
12592  * ------------------------------------
12593  * The SBSR register retrieves the shared buffer occupancy according to
12594  * Port-Pool. Note that this register enables reading a large amount of data.
12595  * It is the user's responsibility to limit the amount of data to ensure the
12596  * response can match the maximum transfer unit. In case the response exceeds
12597  * the maximum transport unit, it will be truncated with no special notice.
12598  */
12599 #define MLXSW_REG_SBSR_ID 0xB005
12600 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
12601 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
12602 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
12603 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN +	\
12604 			    MLXSW_REG_SBSR_REC_LEN *	\
12605 			    MLXSW_REG_SBSR_REC_MAX_COUNT)
12606 
12607 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
12608 
12609 /* reg_sbsr_clr
12610  * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
12611  * field is cleared (and a new max value is tracked from the time the clear
12612  * was performed).
12613  * Access: OP
12614  */
12615 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
12616 
12617 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256
12618 
12619 /* reg_sbsr_port_page
12620  * Determines the range of the ports specified in the 'ingress_port_mask'
12621  * and 'egress_port_mask' bit masks.
12622  * {ingress,egress}_port_mask[x] is (256 * port_page) + x
12623  * Access: Index
12624  */
12625 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4);
12626 
12627 /* reg_sbsr_ingress_port_mask
12628  * Bit vector for all ingress network ports.
12629  * Indicates which of the ports (for which the relevant bit is set)
12630  * are affected by the set operation. Configuration of any other port
12631  * does not change.
12632  * Access: Index
12633  */
12634 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
12635 
12636 /* reg_sbsr_pg_buff_mask
12637  * Bit vector for all switch priority groups.
12638  * Indicates which of the priorities (for which the relevant bit is set)
12639  * are affected by the set operation. Configuration of any other priority
12640  * does not change.
12641  * Range is 0..cap_max_pg_buffers - 1
12642  * Access: Index
12643  */
12644 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
12645 
12646 /* reg_sbsr_egress_port_mask
12647  * Bit vector for all egress network ports.
12648  * Indicates which of the ports (for which the relevant bit is set)
12649  * are affected by the set operation. Configuration of any other port
12650  * does not change.
12651  * Access: Index
12652  */
12653 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
12654 
12655 /* reg_sbsr_tclass_mask
12656  * Bit vector for all traffic classes.
12657  * Indicates which of the traffic classes (for which the relevant bit is
12658  * set) are affected by the set operation. Configuration of any other
12659  * traffic class does not change.
12660  * Range is 0..cap_max_tclass - 1
12661  * Access: Index
12662  */
12663 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
12664 
mlxsw_reg_sbsr_pack(char * payload,bool clr)12665 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
12666 {
12667 	MLXSW_REG_ZERO(sbsr, payload);
12668 	mlxsw_reg_sbsr_clr_set(payload, clr);
12669 }
12670 
12671 /* reg_sbsr_rec_buff_occupancy
12672  * Current buffer occupancy in cells.
12673  * Access: RO
12674  */
12675 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
12676 		     0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
12677 
12678 /* reg_sbsr_rec_max_buff_occupancy
12679  * Maximum value of buffer occupancy in cells monitored. Cleared by
12680  * writing to the clr field.
12681  * Access: RO
12682  */
12683 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
12684 		     0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
12685 
mlxsw_reg_sbsr_rec_unpack(char * payload,int rec_index,u32 * p_buff_occupancy,u32 * p_max_buff_occupancy)12686 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
12687 					     u32 *p_buff_occupancy,
12688 					     u32 *p_max_buff_occupancy)
12689 {
12690 	*p_buff_occupancy =
12691 		mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
12692 	*p_max_buff_occupancy =
12693 		mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
12694 }
12695 
12696 /* SBIB - Shared Buffer Internal Buffer Register
12697  * ---------------------------------------------
12698  * The SBIB register configures per port buffers for internal use. The internal
12699  * buffers consume memory on the port buffers (note that the port buffers are
12700  * used also by PBMC).
12701  *
12702  * For Spectrum this is used for egress mirroring.
12703  */
12704 #define MLXSW_REG_SBIB_ID 0xB006
12705 #define MLXSW_REG_SBIB_LEN 0x10
12706 
12707 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
12708 
12709 /* reg_sbib_local_port
12710  * Local port number
12711  * Not supported for CPU port and router port
12712  * Access: Index
12713  */
12714 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12);
12715 
12716 /* reg_sbib_buff_size
12717  * Units represented in cells
12718  * Allowed range is 0 to (cap_max_headroom_size - 1)
12719  * Default is 0
12720  * Access: RW
12721  */
12722 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
12723 
mlxsw_reg_sbib_pack(char * payload,u16 local_port,u32 buff_size)12724 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port,
12725 				       u32 buff_size)
12726 {
12727 	MLXSW_REG_ZERO(sbib, payload);
12728 	mlxsw_reg_sbib_local_port_set(payload, local_port);
12729 	mlxsw_reg_sbib_buff_size_set(payload, buff_size);
12730 }
12731 
12732 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
12733 	MLXSW_REG(sgcr),
12734 	MLXSW_REG(spad),
12735 	MLXSW_REG(sspr),
12736 	MLXSW_REG(sfdat),
12737 	MLXSW_REG(sfd),
12738 	MLXSW_REG(sfn),
12739 	MLXSW_REG(spms),
12740 	MLXSW_REG(spvid),
12741 	MLXSW_REG(spvm),
12742 	MLXSW_REG(spaft),
12743 	MLXSW_REG(sfgc),
12744 	MLXSW_REG(sfdf),
12745 	MLXSW_REG(sldr),
12746 	MLXSW_REG(slcr),
12747 	MLXSW_REG(slcor),
12748 	MLXSW_REG(spmlr),
12749 	MLXSW_REG(svfa),
12750 	MLXSW_REG(spvtr),
12751 	MLXSW_REG(svpe),
12752 	MLXSW_REG(sfmr),
12753 	MLXSW_REG(spvmlr),
12754 	MLXSW_REG(spvc),
12755 	MLXSW_REG(spevet),
12756 	MLXSW_REG(smpe),
12757 	MLXSW_REG(smid2),
12758 	MLXSW_REG(cwtp),
12759 	MLXSW_REG(cwtpm),
12760 	MLXSW_REG(pgcr),
12761 	MLXSW_REG(ppbt),
12762 	MLXSW_REG(pacl),
12763 	MLXSW_REG(pagt),
12764 	MLXSW_REG(ptar),
12765 	MLXSW_REG(ppbs),
12766 	MLXSW_REG(prcr),
12767 	MLXSW_REG(pefa),
12768 	MLXSW_REG(pemrbt),
12769 	MLXSW_REG(ptce2),
12770 	MLXSW_REG(perpt),
12771 	MLXSW_REG(peabfe),
12772 	MLXSW_REG(perar),
12773 	MLXSW_REG(ptce3),
12774 	MLXSW_REG(percr),
12775 	MLXSW_REG(pererp),
12776 	MLXSW_REG(iedr),
12777 	MLXSW_REG(qpts),
12778 	MLXSW_REG(qpcr),
12779 	MLXSW_REG(qtct),
12780 	MLXSW_REG(qeec),
12781 	MLXSW_REG(qrwe),
12782 	MLXSW_REG(qpdsm),
12783 	MLXSW_REG(qpdp),
12784 	MLXSW_REG(qpdpm),
12785 	MLXSW_REG(qtctm),
12786 	MLXSW_REG(qpsc),
12787 	MLXSW_REG(pmlp),
12788 	MLXSW_REG(pmtu),
12789 	MLXSW_REG(ptys),
12790 	MLXSW_REG(ppad),
12791 	MLXSW_REG(paos),
12792 	MLXSW_REG(pfcc),
12793 	MLXSW_REG(ppcnt),
12794 	MLXSW_REG(pptb),
12795 	MLXSW_REG(pbmc),
12796 	MLXSW_REG(pspa),
12797 	MLXSW_REG(pmaos),
12798 	MLXSW_REG(pplr),
12799 	MLXSW_REG(pmtdb),
12800 	MLXSW_REG(pmecr),
12801 	MLXSW_REG(pmpe),
12802 	MLXSW_REG(pddr),
12803 	MLXSW_REG(pmmp),
12804 	MLXSW_REG(pllp),
12805 	MLXSW_REG(pmtm),
12806 	MLXSW_REG(htgt),
12807 	MLXSW_REG(hpkt),
12808 	MLXSW_REG(rgcr),
12809 	MLXSW_REG(ritr),
12810 	MLXSW_REG(rtar),
12811 	MLXSW_REG(ratr),
12812 	MLXSW_REG(rtdp),
12813 	MLXSW_REG(rips),
12814 	MLXSW_REG(ratrad),
12815 	MLXSW_REG(rdpm),
12816 	MLXSW_REG(ricnt),
12817 	MLXSW_REG(rrcr),
12818 	MLXSW_REG(ralta),
12819 	MLXSW_REG(ralst),
12820 	MLXSW_REG(raltb),
12821 	MLXSW_REG(ralue),
12822 	MLXSW_REG(rauht),
12823 	MLXSW_REG(raleu),
12824 	MLXSW_REG(rauhtd),
12825 	MLXSW_REG(rigr2),
12826 	MLXSW_REG(recr2),
12827 	MLXSW_REG(rmft2),
12828 	MLXSW_REG(reiv),
12829 	MLXSW_REG(mfcr),
12830 	MLXSW_REG(mfsc),
12831 	MLXSW_REG(mfsm),
12832 	MLXSW_REG(mfsl),
12833 	MLXSW_REG(fore),
12834 	MLXSW_REG(mtcap),
12835 	MLXSW_REG(mtmp),
12836 	MLXSW_REG(mtwe),
12837 	MLXSW_REG(mtbr),
12838 	MLXSW_REG(mcia),
12839 	MLXSW_REG(mpat),
12840 	MLXSW_REG(mpar),
12841 	MLXSW_REG(mgir),
12842 	MLXSW_REG(mrsr),
12843 	MLXSW_REG(mlcr),
12844 	MLXSW_REG(mcion),
12845 	MLXSW_REG(mtpps),
12846 	MLXSW_REG(mtutc),
12847 	MLXSW_REG(mpsc),
12848 	MLXSW_REG(mcqi),
12849 	MLXSW_REG(mcc),
12850 	MLXSW_REG(mcda),
12851 	MLXSW_REG(mgpc),
12852 	MLXSW_REG(mprs),
12853 	MLXSW_REG(mogcr),
12854 	MLXSW_REG(mpagr),
12855 	MLXSW_REG(momte),
12856 	MLXSW_REG(mtpppc),
12857 	MLXSW_REG(mtpptr),
12858 	MLXSW_REG(mtptpt),
12859 	MLXSW_REG(mtpcpc),
12860 	MLXSW_REG(mfgd),
12861 	MLXSW_REG(mgpir),
12862 	MLXSW_REG(mbct),
12863 	MLXSW_REG(mddt),
12864 	MLXSW_REG(mddq),
12865 	MLXSW_REG(mddc),
12866 	MLXSW_REG(mfde),
12867 	MLXSW_REG(tngcr),
12868 	MLXSW_REG(tnumt),
12869 	MLXSW_REG(tnqcr),
12870 	MLXSW_REG(tnqdr),
12871 	MLXSW_REG(tneem),
12872 	MLXSW_REG(tndem),
12873 	MLXSW_REG(tnpc),
12874 	MLXSW_REG(tigcr),
12875 	MLXSW_REG(tieem),
12876 	MLXSW_REG(tidem),
12877 	MLXSW_REG(sbpr),
12878 	MLXSW_REG(sbcm),
12879 	MLXSW_REG(sbpm),
12880 	MLXSW_REG(sbmm),
12881 	MLXSW_REG(sbsr),
12882 	MLXSW_REG(sbib),
12883 };
12884 
mlxsw_reg_id_str(u16 reg_id)12885 static inline const char *mlxsw_reg_id_str(u16 reg_id)
12886 {
12887 	const struct mlxsw_reg_info *reg_info;
12888 	int i;
12889 
12890 	for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
12891 		reg_info = mlxsw_reg_infos[i];
12892 		if (reg_info->id == reg_id)
12893 			return reg_info->name;
12894 	}
12895 	return "*UNKNOWN*";
12896 }
12897 
12898 /* PUDE - Port Up / Down Event
12899  * ---------------------------
12900  * Reports the operational state change of a port.
12901  */
12902 #define MLXSW_REG_PUDE_LEN 0x10
12903 
12904 /* reg_pude_swid
12905  * Switch partition ID with which to associate the port.
12906  * Access: Index
12907  */
12908 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
12909 
12910 /* reg_pude_local_port
12911  * Local port number.
12912  * Access: Index
12913  */
12914 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12);
12915 
12916 /* reg_pude_admin_status
12917  * Port administrative state (the desired state).
12918  * 1 - Up.
12919  * 2 - Down.
12920  * 3 - Up once. This means that in case of link failure, the port won't go
12921  *     into polling mode, but will wait to be re-enabled by software.
12922  * 4 - Disabled by system. Can only be set by hardware.
12923  * Access: RO
12924  */
12925 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
12926 
12927 /* reg_pude_oper_status
12928  * Port operatioanl state.
12929  * 1 - Up.
12930  * 2 - Down.
12931  * 3 - Down by port failure. This means that the device will not let the
12932  *     port up again until explicitly specified by software.
12933  * Access: RO
12934  */
12935 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
12936 
12937 #endif
12938