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Searched refs:mmBIOS_SCRATCH_6 (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega20_baco.c36 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
Dvega12_baco.c82 { CMD_WRITE, NBIF_HWID, 0, mmBIOS_SCRATCH_6_BASE_IDX, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
Dvega10_baco.c84 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
Dfiji_baco.c149 { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
Dci_baco.c157 { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
Dpolaris_baco.c147 { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
Dtonga_baco.c151 { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_3_0_d.h616 #define mmBIOS_SCRATCH_6 0x05CF macro
Dbif_4_1_d.h150 #define mmBIOS_SCRATCH_6 0x5cf macro
Dbif_5_0_d.h161 #define mmBIOS_SCRATCH_6 0x5cf macro
Dbif_5_1_d.h169 #define mmBIOS_SCRATCH_6 0x5cf macro
/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_resource.c82 #define mmBIOS_SCRATCH_6 0x05CF macro
371 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_resource.c81 #define mmBIOS_SCRATCH_6 0x05CF macro
389 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_resource.c84 #define mmBIOS_SCRATCH_6 0x05CF macro
369 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_resource.c83 #define mmBIOS_SCRATCH_6 0x05CF macro
372 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_resource.c87 #define mmBIOS_SCRATCH_6 0x05CF macro
381 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
/drivers/gpu/drm/amd/include/asic_reg/nbif/
Dnbif_6_1_offset.h597 #define mmBIOS_SCRATCH_6 macro
/drivers/gpu/drm/amd/amdgpu/
Datombios_encoders.c1827 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); in amdgpu_atombios_encoder_set_bios_scratch_regs()
1958 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch); in amdgpu_atombios_encoder_set_bios_scratch_regs()
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_resource.c494 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_6_1_offset.h2172 #define mmBIOS_SCRATCH_6 macro
Dnbio_7_0_offset.h4056 #define mmBIOS_SCRATCH_6 macro
Dnbio_7_4_offset.h2492 #define mmBIOS_SCRATCH_6 macro
Dnbio_2_3_offset.h70 #define mmBIOS_SCRATCH_6 macro