1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_CPU_IF_REGS_H_ 14 #define ASIC_REG_CPU_IF_REGS_H_ 15 16 /* 17 ***************************************** 18 * CPU_IF (Prototype: CPU_IF) 19 ***************************************** 20 */ 21 22 #define mmCPU_IF_ARUSER_OVR 0x442104 23 24 #define mmCPU_IF_ARUSER_OVR_EN 0x442108 25 26 #define mmCPU_IF_AWUSER_OVR 0x44210C 27 28 #define mmCPU_IF_AWUSER_OVR_EN 0x442110 29 30 #define mmCPU_IF_AXCACHE_OVR 0x442114 31 32 #define mmCPU_IF_LOCK_OVR 0x442118 33 34 #define mmCPU_IF_PROT_OVR 0x44211C 35 36 #define mmCPU_IF_MAX_OUTSTANDING 0x442120 37 38 #define mmCPU_IF_EARLY_BRESP_EN 0x442124 39 40 #define mmCPU_IF_FORCE_RSP_OK 0x442128 41 42 #define mmCPU_IF_CPU_MSB_ADDR 0x44212C 43 44 #define mmCPU_IF_AXI_SPLIT_INTR 0x442130 45 46 #define mmCPU_IF_TOTAL_WR_CNT 0x442140 47 48 #define mmCPU_IF_INFLIGHT_WR_CNT 0x442144 49 50 #define mmCPU_IF_TOTAL_RD_CNT 0x442150 51 52 #define mmCPU_IF_INFLIGHT_RD_CNT 0x442154 53 54 #define mmCPU_IF_PF_PQ_PI 0x442200 55 56 #define mmCPU_IF_PQ_BASE_ADDR_LOW 0x442204 57 58 #define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x442208 59 60 #define mmCPU_IF_PQ_LENGTH 0x44220C 61 62 #define mmCPU_IF_CQ_BASE_ADDR_LOW 0x442210 63 64 #define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x442214 65 66 #define mmCPU_IF_CQ_LENGTH 0x442218 67 68 #define mmCPU_IF_EQ_BASE_ADDR_LOW 0x442220 69 70 #define mmCPU_IF_EQ_BASE_ADDR_HIGH 0x442224 71 72 #define mmCPU_IF_EQ_LENGTH 0x442228 73 74 #define mmCPU_IF_EQ_RD_OFFS 0x44222C 75 76 #define mmCPU_IF_QUEUE_INIT 0x442230 77 78 #define mmCPU_IF_TPC_SERR_INTR_STS 0x442300 79 80 #define mmCPU_IF_TPC_SERR_INTR_CLR 0x442304 81 82 #define mmCPU_IF_TPC_SERR_INTR_MASK 0x442308 83 84 #define mmCPU_IF_TPC_DERR_INTR_STS 0x442310 85 86 #define mmCPU_IF_TPC_DERR_INTR_CLR 0x442314 87 88 #define mmCPU_IF_TPC_DERR_INTR_MASK 0x442318 89 90 #define mmCPU_IF_DMA_SERR_INTR_STS 0x442320 91 92 #define mmCPU_IF_DMA_SERR_INTR_CLR 0x442324 93 94 #define mmCPU_IF_DMA_SERR_INTR_MASK 0x442328 95 96 #define mmCPU_IF_DMA_DERR_INTR_STS 0x442330 97 98 #define mmCPU_IF_DMA_DERR_INTR_CLR 0x442334 99 100 #define mmCPU_IF_DMA_DERR_INTR_MASK 0x442338 101 102 #define mmCPU_IF_SRAM_SERR_INTR_STS 0x442340 103 104 #define mmCPU_IF_SRAM_SERR_INTR_CLR 0x442344 105 106 #define mmCPU_IF_SRAM_SERR_INTR_MASK 0x442348 107 108 #define mmCPU_IF_SRAM_DERR_INTR_STS 0x442350 109 110 #define mmCPU_IF_SRAM_DERR_INTR_CLR 0x442354 111 112 #define mmCPU_IF_SRAM_DERR_INTR_MASK 0x442358 113 114 #define mmCPU_IF_NIC_SERR_INTR_STS 0x442360 115 116 #define mmCPU_IF_NIC_SERR_INTR_CLR 0x442364 117 118 #define mmCPU_IF_NIC_SERR_INTR_MASK 0x442368 119 120 #define mmCPU_IF_NIC_DERR_INTR_STS 0x442370 121 122 #define mmCPU_IF_NIC_DERR_INTR_CLR 0x442374 123 124 #define mmCPU_IF_NIC_DERR_INTR_MASK 0x442378 125 126 #define mmCPU_IF_DMA_IF_SERR_INTR_STS 0x442380 127 128 #define mmCPU_IF_DMA_IF_SERR_INTR_CLR 0x442384 129 130 #define mmCPU_IF_DMA_IF_SERR_INTR_MASK 0x442388 131 132 #define mmCPU_IF_DMA_IF_DERR_INTR_STS 0x442390 133 134 #define mmCPU_IF_DMA_IF_DERR_INTR_CLR 0x442394 135 136 #define mmCPU_IF_DMA_IF_DERR_INTR_MASK 0x442398 137 138 #define mmCPU_IF_HBM_SERR_INTR_STS 0x4423A0 139 140 #define mmCPU_IF_HBM_SERR_INTR_CLR 0x4423A4 141 142 #define mmCPU_IF_HBM_SERR_INTR_MASK 0x4423A8 143 144 #define mmCPU_IF_HBM_DERR_INTR_STS 0x4423B0 145 146 #define mmCPU_IF_HBM_DERR_INTR_CLR 0x4423B4 147 148 #define mmCPU_IF_HBM_DERR_INTR_MASK 0x4423B8 149 150 #define mmCPU_IF_PLL_SEI_INTR_STS 0x442400 151 152 #define mmCPU_IF_PLL_SEI_INTR_CLR 0x442404 153 154 #define mmCPU_IF_PLL_SEI_INTR_MASK 0x442408 155 156 #define mmCPU_IF_NIC_SEI_INTR_STS 0x442410 157 158 #define mmCPU_IF_NIC_SEI_INTR_CLR 0x442414 159 160 #define mmCPU_IF_NIC_SEI_INTR_MASK 0x442418 161 162 #define mmCPU_IF_DMA_SEI_INTR_STS 0x442420 163 164 #define mmCPU_IF_DMA_SEI_INTR_CLR 0x442424 165 166 #define mmCPU_IF_DMA_SEI_INTR_MASK 0x442428 167 168 #define mmCPU_IF_DMA_IF_SEI_INTR_STS 0x442430 169 170 #define mmCPU_IF_DMA_IF_SEI_INTR_CLR 0x442434 171 172 #define mmCPU_IF_DMA_IF_SEI_INTR_MASK 0x442438 173 174 #endif /* ASIC_REG_CPU_IF_REGS_H_ */ 175