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Searched refs:mmDMA0_CORE_CFG_0 (Results 1 – 4 of 4) sorted by relevance

/drivers/misc/habanalabs/gaudi/
DgaudiP.h101 #define QMAN_LDMA_SRC_OFFSET (mmDMA0_CORE_SRC_BASE_LO - mmDMA0_CORE_CFG_0)
102 #define QMAN_LDMA_DST_OFFSET (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
103 #define QMAN_LDMA_SIZE_OFFSET (mmDMA0_CORE_DST_TSIZE_0 - mmDMA0_CORE_CFG_0)
105 #define QMAN_CPDMA_SRC_OFFSET (mmDMA0_QM_CQ_PTR_LO_4 - mmDMA0_CORE_CFG_0)
106 #define QMAN_CPDMA_DST_OFFSET (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
107 #define QMAN_CPDMA_SIZE_OFFSET (mmDMA0_QM_CQ_TSIZE_4 - mmDMA0_CORE_CFG_0)
Dgaudi_security.c4672 pb_addr = (mmDMA0_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; in gaudi_init_dma_protection_bits()
4673 word_offset = ((mmDMA0_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; in gaudi_init_dma_protection_bits()
4674 mask = 1U << ((mmDMA0_CORE_CFG_0 & 0x7F) >> 2); in gaudi_init_dma_protection_bits()
Dgaudi.c2731 WREG32(mmDMA0_CORE_CFG_0 + dma_offset, 1 << DMA0_CORE_CFG_0_EN_SHIFT); in gaudi_init_dma_core()
/drivers/misc/habanalabs/include/gaudi/asic_reg/
Ddma0_core_regs.h22 #define mmDMA0_CORE_CFG_0 0x500000 macro