Searched refs:mmIH_RB_WPTR_ADDR_HI (Results 1 – 16 of 16) sorted by relevance
| /drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_1_0_d.h | 234 #define mmIH_RB_WPTR_ADDR_HI 0x0F84 macro
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| D | osssys_4_0_offset.h | 130 #define mmIH_RB_WPTR_ADDR_HI … macro
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| D | osssys_4_0_1_offset.h | 130 #define mmIH_RB_WPTR_ADDR_HI … macro
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| D | osssys_5_0_0_offset.h | 130 #define mmIH_RB_WPTR_ADDR_HI … macro
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| D | osssys_4_2_0_offset.h | 132 #define mmIH_RB_WPTR_ADDR_HI … macro
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| D | oss_2_4_d.h | 47 #define mmIH_RB_WPTR_ADDR_HI 0xe34 macro
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| D | oss_3_0_1_d.h | 47 #define mmIH_RB_WPTR_ADDR_HI 0xe34 macro
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| D | oss_2_0_d.h | 47 #define mmIH_RB_WPTR_ADDR_HI 0xf84 macro
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| D | oss_3_0_d.h | 47 #define mmIH_RB_WPTR_ADDR_HI 0xe34 macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | cik_ih.c | 137 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cik_ih_irq_init()
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| D | cz_ih.c | 139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cz_ih_irq_init()
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| D | iceland_ih.c | 139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in iceland_ih_irq_init()
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| D | tonga_ih.c | 139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in tonga_ih_irq_init()
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| D | vega10_ih.c | 60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in vega10_ih_init_register_offset()
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| D | vega20_ih.c | 63 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in vega20_ih_init_register_offset()
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| D | navi10_ih.c | 62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in navi10_ih_init_register_offset()
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