1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_PMMU_HBW_STLB_REGS_H_ 14 #define ASIC_REG_PMMU_HBW_STLB_REGS_H_ 15 16 /* 17 ***************************************** 18 * PMMU_HBW_STLB 19 * (Prototype: STLB) 20 ***************************************** 21 */ 22 23 #define mmPMMU_HBW_STLB_BUSY 0x4D01000 24 25 #define mmPMMU_HBW_STLB_ASID 0x4D01004 26 27 #define mmPMMU_HBW_STLB_HOP0_PA43_12 0x4D01008 28 29 #define mmPMMU_HBW_STLB_HOP0_PA63_44 0x4D0100C 30 31 #define mmPMMU_HBW_STLB_CACHE_INV 0x4D01010 32 33 #define mmPMMU_HBW_STLB_CACHE_INV_BASE_39_8 0x4D01014 34 35 #define mmPMMU_HBW_STLB_CACHE_INV_BASE_63_40 0x4D01018 36 37 #define mmPMMU_HBW_STLB_STLB_FEATURE_EN 0x4D0101C 38 39 #define mmPMMU_HBW_STLB_STLB_AXI_CACHE 0x4D01020 40 41 #define mmPMMU_HBW_STLB_HOP_CONFIGURATION 0x4D01024 42 43 #define mmPMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32 0x4D01028 44 45 #define mmPMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0 0x4D0102C 46 47 #define mmPMMU_HBW_STLB_INV_ALL_START 0x4D01034 48 49 #define mmPMMU_HBW_STLB_INV_ALL_SET 0x4D01038 50 51 #define mmPMMU_HBW_STLB_INV_PS 0x4D0103C 52 53 #define mmPMMU_HBW_STLB_INV_CONSUMER_INDEX 0x4D01040 54 55 #define mmPMMU_HBW_STLB_INV_HIT_COUNT 0x4D01044 56 57 #define mmPMMU_HBW_STLB_INV_SET 0x4D01048 58 59 #define mmPMMU_HBW_STLB_SRAM_INIT 0x4D0104C 60 61 #define mmPMMU_HBW_STLB_MEM_CACHE_INVALIDATION 0x4D01050 62 63 #define mmPMMU_HBW_STLB_MEM_CACHE_INV_STATUS 0x4D01054 64 65 #define mmPMMU_HBW_STLB_MEM_CACHE_BASE_38_7 0x4D01058 66 67 #define mmPMMU_HBW_STLB_MEM_CACHE_BASE_63_39 0x4D0105C 68 69 #define mmPMMU_HBW_STLB_MEM_CACHE_CONFIG 0x4D01060 70 71 #define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP5 0x4D01064 72 73 #define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP4 0x4D01068 74 75 #define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP3 0x4D0106C 76 77 #define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP2 0x4D01070 78 79 #define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP1 0x4D01074 80 81 #define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP0 0x4D01078 82 83 #define mmPMMU_HBW_STLB_MULTI_HIT_INTERRUPT_CLR 0x4D0107C 84 85 #define mmPMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK 0x4D01080 86 87 #define mmPMMU_HBW_STLB_MEM_L0_CACHE_CFG 0x4D01084 88 89 #define mmPMMU_HBW_STLB_MEM_READ_ARPROT 0x4D01088 90 91 #define mmPMMU_HBW_STLB_RANGE_CACHE_INVALIDATION 0x4D0108C 92 93 #define mmPMMU_HBW_STLB_RANGE_INV_START_LSB 0x4D01090 94 95 #define mmPMMU_HBW_STLB_RANGE_INV_START_MSB 0x4D01094 96 97 #define mmPMMU_HBW_STLB_RANGE_INV_END_LSB 0x4D01098 98 99 #define mmPMMU_HBW_STLB_RANGE_INV_END_MSB 0x4D0109C 100 101 #define mmPMMU_HBW_STLB_ASID_SCRAMBLER_CTRL 0x4D01100 102 103 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0 0x4D01104 104 105 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1 0x4D01108 106 107 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2 0x4D0110C 108 109 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3 0x4D01110 110 111 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4 0x4D01114 112 113 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5 0x4D01118 114 115 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6 0x4D0111C 116 117 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7 0x4D01120 118 119 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8 0x4D01124 120 121 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9 0x4D01128 122 123 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10 0x4D0112C 124 125 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11 0x4D01130 126 127 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12 0x4D01134 128 129 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13 0x4D01138 130 131 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14 0x4D0113C 132 133 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15 0x4D01140 134 135 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16 0x4D01144 136 137 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17 0x4D01148 138 139 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18 0x4D0114C 140 141 #endif /* ASIC_REG_PMMU_HBW_STLB_REGS_H_ */ 142