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Searched refs:mmUVD_GP_SCRATCH9 (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_d.h131 #define mmUVD_GP_SCRATCH9 0x3c0b macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h176 #define mmUVD_GP_SCRATCH9 … macro
Dvcn_2_5_offset.h651 #define mmUVD_GP_SCRATCH9 … macro
Dvcn_2_0_0_offset.h874 #define mmUVD_GP_SCRATCH9 … macro
Dvcn_3_0_0_offset.h1001 #define mmUVD_GP_SCRATCH9 … macro
/drivers/gpu/drm/amd/amdgpu/
Duvd_v6_0.c1097 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0)); in uvd_v6_0_ring_emit_pipeline_sync()