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Searched refs:mmUVD_JRBC_ENC_RB_COND_RD_TIMER (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_offset.h189 #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER … macro
Dvcn_2_0_0_offset.h174 #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER … macro
Dvcn_3_0_0_offset.h387 #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER … macro