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Searched refs:mmUVD_PGFSM_CONFIG (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h62 #define mmUVD_PGFSM_CONFIG 0x38F8 macro
Duvd_4_2_d.h88 #define mmUVD_PGFSM_CONFIG 0x38f8 macro
Duvd_3_1_d.h90 #define mmUVD_PGFSM_CONFIG 0x38f8 macro
Duvd_5_0_d.h100 #define mmUVD_PGFSM_CONFIG 0x38c0 macro
Duvd_6_0_d.h116 #define mmUVD_PGFSM_CONFIG 0x38c0 macro
/drivers/gpu/drm/amd/amdgpu/
Djpeg_v3_0.c273 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); in jpeg_v3_0_disable_static_power_gating()
308 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); in jpeg_v3_0_enable_static_power_gating()
Duvd_v4_2.c730 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | in uvd_v4_2_set_powergating_state()
741 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | in uvd_v4_2_set_powergating_state()
Djpeg_v2_0.c213 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); in jpeg_v2_0_disable_power_gating()
244 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); in jpeg_v2_0_enable_power_gating()
Dvcn_v2_0.c720 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_disable_static_power_gating()
734 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_disable_static_power_gating()
776 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_enable_static_power_gating()
Dvcn_v1_0.c710 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_1_0_disable_static_power_gating()
724 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_1_0_disable_static_power_gating()
762 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_1_0_enable_static_power_gating()
Dvcn_v3_0.c611 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); in vcn_v3_0_disable_static_power_gating()
629 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); in vcn_v3_0_disable_static_power_gating()
667 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); in vcn_v3_0_enable_static_power_gating()
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h28 #define mmUVD_PGFSM_CONFIG … macro
Dvcn_2_5_offset.h395 #define mmUVD_PGFSM_CONFIG … macro
Dvcn_2_0_0_offset.h380 #define mmUVD_PGFSM_CONFIG … macro
Dvcn_3_0_0_offset.h663 #define mmUVD_PGFSM_CONFIG … macro