Searched refs:mmUVD_RB_SIZE2 (Results 1 – 12 of 12) sorted by relevance
| /drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_6_0_d.h | 41 #define mmUVD_RB_SIZE2 0x3c23 macro
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| D | uvd_7_0_offset.h | 88 #define mmUVD_RB_SIZE2 … macro
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| /drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 210 #define mmUVD_RB_SIZE2 … macro
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| D | vcn_2_5_offset.h | 565 #define mmUVD_RB_SIZE2 … macro
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| D | vcn_2_0_0_offset.h | 922 #define mmUVD_RB_SIZE2 … macro
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| D | vcn_3_0_0_offset.h | 895 #define mmUVD_RB_SIZE2 … macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v2_0.c | 1096 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_0_start()
1249 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_0_pause_dpg_mode()
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| D | vcn_v1_0.c | 953 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v1_0_start_spg_mode()
1253 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v1_0_pause_dpg_mode()
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| D | vcn_v2_5.c | 1103 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_5_start()
1453 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_5_pause_dpg_mode()
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| D | vcn_v3_0.c | 1273 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v3_0_start()
1648 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v3_0_pause_dpg_mode()
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| D | uvd_v6_0.c | 874 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4); in uvd_v6_0_start()
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| D | uvd_v7_0.c | 1123 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4); in uvd_v7_0_start()
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