| /drivers/gpu/drm/tests/ |
| D | drm_cmdline_parser_test.c | 16 struct drm_cmdline_mode mode = { }; in drm_test_cmdline_force_e_only() local
20 &no_connector, &mode)); in drm_test_cmdline_force_e_only()
21 KUNIT_EXPECT_FALSE(test, mode.specified); in drm_test_cmdline_force_e_only()
22 KUNIT_EXPECT_FALSE(test, mode.refresh_specified); in drm_test_cmdline_force_e_only()
23 KUNIT_EXPECT_FALSE(test, mode.bpp_specified); in drm_test_cmdline_force_e_only()
25 KUNIT_EXPECT_FALSE(test, mode.rb); in drm_test_cmdline_force_e_only()
26 KUNIT_EXPECT_FALSE(test, mode.cvt); in drm_test_cmdline_force_e_only()
27 KUNIT_EXPECT_FALSE(test, mode.interlace); in drm_test_cmdline_force_e_only()
28 KUNIT_EXPECT_FALSE(test, mode.margins); in drm_test_cmdline_force_e_only()
29 KUNIT_EXPECT_EQ(test, mode.force, DRM_FORCE_ON); in drm_test_cmdline_force_e_only()
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| /drivers/net/wireless/ath/ath5k/ |
| D | eeprom.c | 41 unsigned int mode) in ath5k_eeprom_bin2freq() argument
48 if (mode == AR5K_EEPROM_MODE_11A) { in ath5k_eeprom_bin2freq()
190 unsigned int mode) in ath5k_eeprom_read_ants() argument
198 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; in ath5k_eeprom_read_ants()
199 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f; in ath5k_eeprom_read_ants()
200 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; in ath5k_eeprom_read_ants()
203 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; in ath5k_eeprom_read_ants()
204 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; in ath5k_eeprom_read_ants()
205 ee->ee_ant_control[mode][i++] = val & 0x3f; in ath5k_eeprom_read_ants()
208 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; in ath5k_eeprom_read_ants()
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| /drivers/interconnect/imx/ |
| D | imx8mp.c | 25 .mode = IMX_NOC_MODE_FIXED,
30 .mode = IMX_NOC_MODE_FIXED,
35 .mode = IMX_NOC_MODE_FIXED,
40 .mode = IMX_NOC_MODE_FIXED,
45 .mode = IMX_NOC_MODE_FIXED,
50 .mode = IMX_NOC_MODE_FIXED,
55 .mode = IMX_NOC_MODE_FIXED,
60 .mode = IMX_NOC_MODE_FIXED,
65 .mode = IMX_NOC_MODE_FIXED,
70 .mode = IMX_NOC_MODE_FIXED,
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| /drivers/gpu/ipu-v3/ |
| D | ipu-di.c | 205 u32 h_total = sig->mode.hactive + sig->mode.hsync_len + in ipu_di_sync_config_interlaced()
206 sig->mode.hback_porch + sig->mode.hfront_porch; in ipu_di_sync_config_interlaced()
207 u32 v_total = sig->mode.vactive + sig->mode.vsync_len + in ipu_di_sync_config_interlaced()
208 sig->mode.vback_porch + sig->mode.vfront_porch; in ipu_di_sync_config_interlaced()
220 .cnt_down = sig->mode.hsync_len * 2, in ipu_di_sync_config_interlaced()
227 .cnt_down = sig->mode.vsync_len * 2, in ipu_di_sync_config_interlaced()
240 .offset_count = (sig->mode.vsync_len + in ipu_di_sync_config_interlaced()
241 sig->mode.vback_porch) / 2, in ipu_di_sync_config_interlaced()
243 .repeat_count = sig->mode.vactive / 2, in ipu_di_sync_config_interlaced()
248 .offset_count = sig->mode.hsync_len + in ipu_di_sync_config_interlaced()
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| /drivers/gpu/drm/ |
| D | drm_modes.c | 57 void drm_mode_debug_printmodeline(const struct drm_display_mode *mode) in drm_mode_debug_printmodeline() argument
59 DRM_DEBUG_KMS("Modeline " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); in drm_mode_debug_printmodeline()
92 void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode) in drm_mode_destroy() argument
94 if (!mode) in drm_mode_destroy()
97 kfree(mode); in drm_mode_destroy()
111 struct drm_display_mode *mode) in drm_mode_probed_add() argument
115 list_add_tail(&mode->head, &connector->probed_modes); in drm_mode_probed_add()
791 void drm_mode_set_name(struct drm_display_mode *mode) in drm_mode_set_name() argument
793 bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); in drm_mode_set_name()
795 snprintf(mode->name, DRM_DISPLAY_MODE_LEN, "%dx%d%s", in drm_mode_set_name()
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| D | drm_probe_helper.c | 71 drm_mode_validate_flag(const struct drm_display_mode *mode, in drm_mode_validate_flag() argument
74 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) && in drm_mode_validate_flag()
78 if ((mode->flags & DRM_MODE_FLAG_DBLSCAN) && in drm_mode_validate_flag()
82 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) && in drm_mode_validate_flag()
90 drm_mode_validate_pipeline(struct drm_display_mode *mode, in drm_mode_validate_pipeline() argument
100 ret = drm_connector_mode_valid(connector, mode, ctx, status); in drm_mode_validate_pipeline()
109 *status = drm_encoder_mode_valid(encoder, mode); in drm_mode_validate_pipeline()
121 mode); in drm_mode_validate_pipeline()
132 *status = drm_crtc_mode_valid(crtc, mode); in drm_mode_validate_pipeline()
148 struct drm_display_mode *mode; in drm_helper_probe_add_cmdline_mode() local
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| /drivers/gpu/drm/nouveau/nvkm/subdev/pci/ |
| D | agp.c | 31 int mode; member
59 u32 mode = nvkm_pci_rd32(pci, 0x004c); in nvkm_agp_preinit() local
66 if ((mode | pci->agp.mode) & PCI_AGP_COMMAND_FW) { in nvkm_agp_preinit()
67 mode = pci->agp.mode & ~PCI_AGP_COMMAND_FW; in nvkm_agp_preinit()
68 agp_enable(pci->agp.bridge, mode); in nvkm_agp_preinit()
92 agp_enable(pci->agp.bridge, pci->agp.mode); in nvkm_agp_init()
110 int mode = -1; in nvkm_agp_ctor() local
120 mode = 0; in nvkm_agp_ctor()
122 mode = nvkm_longopt(device->cfgopt, "NvAGP", mode); in nvkm_agp_ctor()
132 pci->agp.mode = info.mode; in nvkm_agp_ctor()
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| /drivers/video/fbdev/core/ |
| D | modedb.c | 548 const struct fb_videomode *mode, unsigned int bpp) in fb_try_mode() argument
553 mode->name ? mode->name : "noname", in fb_try_mode()
554 mode->xres, mode->yres, bpp, mode->refresh); in fb_try_mode()
555 var->xres = mode->xres; in fb_try_mode()
556 var->yres = mode->yres; in fb_try_mode()
557 var->xres_virtual = mode->xres; in fb_try_mode()
558 var->yres_virtual = mode->yres; in fb_try_mode()
563 var->pixclock = mode->pixclock; in fb_try_mode()
564 var->left_margin = mode->left_margin; in fb_try_mode()
565 var->right_margin = mode->right_margin; in fb_try_mode()
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| D | fbmon.c | 382 struct fb_videomode *mode) in calc_mode_timings() argument
393 mode->xres = xres; in calc_mode_timings()
394 mode->yres = yres; in calc_mode_timings()
395 mode->pixclock = var->pixclock; in calc_mode_timings()
396 mode->refresh = refresh; in calc_mode_timings()
397 mode->left_margin = var->left_margin; in calc_mode_timings()
398 mode->right_margin = var->right_margin; in calc_mode_timings()
399 mode->upper_margin = var->upper_margin; in calc_mode_timings()
400 mode->lower_margin = var->lower_margin; in calc_mode_timings()
401 mode->hsync_len = var->hsync_len; in calc_mode_timings()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/i2c/ |
| D | pad.c | 27 nvkm_i2c_pad_mode_locked(struct nvkm_i2c_pad *pad, enum nvkm_i2c_pad_mode mode) in nvkm_i2c_pad_mode_locked() argument
29 PAD_TRACE(pad, "-> %s", (mode == NVKM_I2C_PAD_AUX) ? "aux" : in nvkm_i2c_pad_mode_locked()
30 (mode == NVKM_I2C_PAD_I2C) ? "i2c" : "off"); in nvkm_i2c_pad_mode_locked()
31 if (pad->func->mode) in nvkm_i2c_pad_mode_locked()
32 pad->func->mode(pad, mode); in nvkm_i2c_pad_mode_locked()
36 nvkm_i2c_pad_mode(struct nvkm_i2c_pad *pad, enum nvkm_i2c_pad_mode mode) in nvkm_i2c_pad_mode() argument
38 PAD_TRACE(pad, "mode %d", mode); in nvkm_i2c_pad_mode()
40 nvkm_i2c_pad_mode_locked(pad, mode); in nvkm_i2c_pad_mode()
41 pad->mode = mode; in nvkm_i2c_pad_mode()
49 if (pad->mode == NVKM_I2C_PAD_OFF) in nvkm_i2c_pad_release()
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| /drivers/phy/hisilicon/ |
| D | phy-histb-combphy.c | 49 struct histb_combphy_mode mode; member
73 static int is_mode_fixed(struct histb_combphy_mode *mode) in is_mode_fixed() argument
75 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
80 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode() local
84 if (is_mode_fixed(mode)) in histb_combphy_set_mode()
87 switch (mode->select) { in histb_combphy_set_mode()
101 return regmap_update_bits(syscon, mode->reg, mode->mask, in histb_combphy_set_mode()
102 hw_sel << mode->shift); in histb_combphy_set_mode()
168 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_xlate() local
175 mode->select = args->args[0]; in histb_combphy_xlate()
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| /drivers/video/fbdev/ |
| D | macmodes.c | 142 const struct fb_videomode *mode; member
223 const struct fb_videomode *mode = NULL; in mac_vmode_to_var() local
228 mode = map->mode; in mac_vmode_to_var()
231 if (!mode) in mac_vmode_to_var()
271 var->xres = mode->xres; in mac_vmode_to_var()
272 var->yres = mode->yres; in mac_vmode_to_var()
273 var->xres_virtual = mode->xres; in mac_vmode_to_var()
274 var->yres_virtual = mode->yres; in mac_vmode_to_var()
277 var->pixclock = mode->pixclock; in mac_vmode_to_var()
278 var->left_margin = mode->left_margin; in mac_vmode_to_var()
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| /drivers/gpu/drm/shmobile/ |
| D | shmob_drm_crtc.c | 66 const struct drm_display_mode *mode = &crtc->mode; in shmob_drm_crtc_setup_geometry() local
70 | ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : LDMT1R_VPOL) in shmob_drm_crtc_setup_geometry()
71 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : LDMT1R_HPOL) in shmob_drm_crtc_setup_geometry()
97 value = ((mode->hdisplay / 8) << 16) /* HDCN */ in shmob_drm_crtc_setup_geometry()
98 | (mode->htotal / 8); /* HTCN */ in shmob_drm_crtc_setup_geometry()
101 value = (((mode->hsync_end - mode->hsync_start) / 8) << 16) /* HSYNW */ in shmob_drm_crtc_setup_geometry()
102 | (mode->hsync_start / 8); /* HSYNP */ in shmob_drm_crtc_setup_geometry()
105 value = ((mode->hdisplay & 7) << 24) | ((mode->htotal & 7) << 16) in shmob_drm_crtc_setup_geometry()
106 | (((mode->hsync_end - mode->hsync_start) & 7) << 8) in shmob_drm_crtc_setup_geometry()
107 | (mode->hsync_start & 7); in shmob_drm_crtc_setup_geometry()
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| /drivers/gpu/drm/msm/disp/mdp4/ |
| D | mdp4_dsi_encoder.c | 42 struct drm_display_mode *mode, in mdp4_dsi_encoder_mode_set() argument
50 mode = adjusted_mode; in mdp4_dsi_encoder_mode_set()
52 DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode)); in mdp4_dsi_encoder_mode_set()
55 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in mdp4_dsi_encoder_mode_set()
57 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in mdp4_dsi_encoder_mode_set()
63 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_dsi_encoder_mode_set()
64 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dsi_encoder_mode_set()
66 vsync_period = mode->vtotal * mode->htotal; in mdp4_dsi_encoder_mode_set()
67 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp4_dsi_encoder_mode_set()
68 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dsi_hsync_skew; in mdp4_dsi_encoder_mode_set()
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| D | mdp4_dtv_encoder.c | 40 struct drm_display_mode *mode, in mdp4_dtv_encoder_mode_set() argument
49 mode = adjusted_mode; in mdp4_dtv_encoder_mode_set()
51 DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode)); in mdp4_dtv_encoder_mode_set()
53 mdp4_dtv_encoder->pixclock = mode->clock * 1000; in mdp4_dtv_encoder_mode_set()
58 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in mdp4_dtv_encoder_mode_set()
60 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in mdp4_dtv_encoder_mode_set()
66 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp4_dtv_encoder_mode_set()
67 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dtv_encoder_mode_set()
69 vsync_period = mode->vtotal * mode->htotal; in mdp4_dtv_encoder_mode_set()
70 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp4_dtv_encoder_mode_set()
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| /drivers/net/ethernet/ibm/emac/ |
| D | zmii.c | 45 static inline int zmii_valid_mode(int mode) in zmii_valid_mode() argument
47 return mode == PHY_INTERFACE_MODE_MII || in zmii_valid_mode()
48 mode == PHY_INTERFACE_MODE_RMII || in zmii_valid_mode()
49 mode == PHY_INTERFACE_MODE_SMII || in zmii_valid_mode()
50 mode == PHY_INTERFACE_MODE_NA; in zmii_valid_mode()
53 static inline const char *zmii_mode_name(int mode) in zmii_mode_name() argument
55 switch (mode) { in zmii_mode_name()
67 static inline u32 zmii_mode_mask(int mode, int input) in zmii_mode_mask() argument
69 switch (mode) { in zmii_mode_mask()
82 phy_interface_t *mode) in zmii_attach() argument
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| /drivers/hid/ |
| D | hid-saitek.c | 33 int mode; member
50 ssc->mode = -1; in saitek_probe()
100 int mode = -1; in saitek_raw_event() local
102 mode = 0; in saitek_raw_event()
104 mode = 1; in saitek_raw_event()
106 mode = 2; in saitek_raw_event()
111 if (mode != ssc->mode) { in saitek_raw_event()
112 hid_dbg(hdev, "entered mode %d\n", mode); in saitek_raw_event()
113 if (ssc->mode != -1) { in saitek_raw_event()
117 ssc->mode = mode; in saitek_raw_event()
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| /drivers/gpu/drm/radeon/ |
| D | radeon_agp.c | 187 static int radeon_agp_head_enable(struct radeon_device *rdev, struct radeon_agp_mode mode) in radeon_agp_head_enable() argument
192 rdev->agp->mode = mode.mode; in radeon_agp_head_enable()
193 agp_enable(rdev->agp->bridge, mode.mode); in radeon_agp_head_enable()
208 info->mode = kern->mode; in radeon_agp_head_info()
224 struct radeon_agp_mode mode; in radeon_agp_init() local
253 mode.mode = info.mode; in radeon_agp_init()
258 agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode; in radeon_agp_init()
260 agp_status = mode.mode; in radeon_agp_init()
303 mode.mode &= ~RADEON_AGP_MODE_MASK; in radeon_agp_init()
307 mode.mode |= RADEON_AGPv3_8X_MODE; in radeon_agp_init()
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| /drivers/gpu/drm/sti/ |
| D | sti_vtg.c | 160 const struct drm_display_mode *mode) in vtg_set_output_window() argument
166 u32 xstart = sti_vtg_get_pixel_number(*mode, 0); in vtg_set_output_window()
167 u32 ystart = sti_vtg_get_line_number(*mode, 0); in vtg_set_output_window()
168 u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); in vtg_set_output_window()
169 u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); in vtg_set_output_window()
187 const struct drm_display_mode *mode) in vtg_set_hsync_vsync_pos() argument
193 clocksperline = mode->htotal; in vtg_set_hsync_vsync_pos()
197 stop = mode->hsync_end - mode->hsync_start; in vtg_set_hsync_vsync_pos()
218 fallsync_top += mode->vsync_end - mode->vsync_start; in vtg_set_hsync_vsync_pos()
223 risesync_top = mode->vtotal; in vtg_set_hsync_vsync_pos()
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| /drivers/gpu/drm/gma500/ |
| D | oaktrail_lvds.c | 68 static void oaktrail_lvds_dpms(struct drm_encoder *encoder, int mode) in oaktrail_lvds_dpms() argument
73 if (mode == DRM_MODE_DPMS_ON) in oaktrail_lvds_dpms()
82 struct drm_display_mode *mode, in oaktrail_lvds_mode_set() argument
135 if ((mode->vdisplay != adjusted_mode->crtc_vdisplay) || in oaktrail_lvds_mode_set()
136 (mode->hdisplay != adjusted_mode->crtc_hdisplay)) { in oaktrail_lvds_mode_set()
137 if ((adjusted_mode->crtc_hdisplay * mode->vdisplay) == in oaktrail_lvds_mode_set()
138 (mode->hdisplay * adjusted_mode->crtc_vdisplay)) in oaktrail_lvds_mode_set()
141 mode->vdisplay) > (mode->hdisplay * in oaktrail_lvds_mode_set()
218 struct drm_display_mode *mode = NULL; in oaktrail_lvds_get_configuration_mode() local
226 mode = kzalloc(sizeof(*mode), GFP_KERNEL); in oaktrail_lvds_get_configuration_mode()
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| /drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_encoder.c | 31 struct drm_display_mode *mode, in mdp5_vid_encoder_mode_set() argument
45 mode = adjusted_mode; in mdp5_vid_encoder_mode_set()
47 DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode)); in mdp5_vid_encoder_mode_set()
53 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in mdp5_vid_encoder_mode_set()
55 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in mdp5_vid_encoder_mode_set()
84 hsync_start_x = (mode->htotal - mode->hsync_start); in mdp5_vid_encoder_mode_set()
85 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp5_vid_encoder_mode_set()
87 vsync_period = mode->vtotal * mode->htotal; in mdp5_vid_encoder_mode_set()
88 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; in mdp5_vid_encoder_mode_set()
89 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; in mdp5_vid_encoder_mode_set()
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| /drivers/net/ethernet/marvell/prestera/ |
| D | prestera_ethtool.c | 325 u32 type, mode; in prestera_port_type_set() local
342 for (mode = 0; mode < PRESTERA_LINK_MODE_MAX; mode++) { in prestera_port_type_set()
343 if ((port_link_modes[mode].pr_mask & in prestera_port_type_set()
345 type == port_link_modes[mode].port_type) { in prestera_port_type_set()
346 new_mode = mode; in prestera_port_type_set()
362 u32 mode; in prestera_modes_to_eth() local
364 for (mode = 0; mode < PRESTERA_LINK_MODE_MAX; mode++) { in prestera_modes_to_eth()
365 if ((port_link_modes[mode].pr_mask & link_modes) == 0) in prestera_modes_to_eth()
369 port_link_modes[mode].port_type != type) in prestera_modes_to_eth()
372 __set_bit(port_link_modes[mode].eth_mode, eth_modes); in prestera_modes_to_eth()
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| /drivers/parport/ |
| D | ieee1284.c | 220 switch (port->ieee1284.mode) { in parport_ieee1284_terminate()
295 port->ieee1284.mode = IEEE1284_MODE_COMPAT; in parport_ieee1284_terminate()
317 int parport_negotiate (struct parport *port, int mode) in parport_negotiate() argument
320 if (mode == IEEE1284_MODE_COMPAT) in parport_negotiate()
325 int m = mode & ~IEEE1284_ADDR; in parport_negotiate()
332 if (port->ieee1284.mode == mode) in parport_negotiate()
336 if ((port->ieee1284.mode & ~IEEE1284_ADDR) == (mode & ~IEEE1284_ADDR)){ in parport_negotiate()
337 port->ieee1284.mode = mode; in parport_negotiate()
342 if (port->ieee1284.mode != IEEE1284_MODE_COMPAT) in parport_negotiate()
345 if (mode == IEEE1284_MODE_COMPAT) in parport_negotiate()
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| /drivers/firmware/efi/libstub/ |
| D | gop.c | 29 u32 mode; member
49 cmdline.mode = m; in parse_modenum()
138 efi_graphics_output_protocol_mode_t *mode; in choose_mode_modenum() local
145 mode = efi_table_attr(gop, mode); in choose_mode_modenum()
147 cur_mode = efi_table_attr(mode, mode); in choose_mode_modenum()
148 if (cmdline.mode == cur_mode) in choose_mode_modenum()
151 max_mode = efi_table_attr(mode, max_mode); in choose_mode_modenum()
152 if (cmdline.mode >= max_mode) { in choose_mode_modenum()
157 status = efi_call_proto(gop, query_mode, cmdline.mode, in choose_mode_modenum()
173 return cmdline.mode; in choose_mode_modenum()
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_encoder_phys_vid.c | 42 const struct drm_display_mode *mode, in drm_mode_to_intf_timing_params() argument
47 if ((mode->htotal < mode->hsync_end) in drm_mode_to_intf_timing_params()
48 || (mode->hsync_start < mode->hdisplay) in drm_mode_to_intf_timing_params()
49 || (mode->vtotal < mode->vsync_end) in drm_mode_to_intf_timing_params()
50 || (mode->vsync_start < mode->vdisplay) in drm_mode_to_intf_timing_params()
51 || (mode->hsync_end < mode->hsync_start) in drm_mode_to_intf_timing_params()
52 || (mode->vsync_end < mode->vsync_start)) { in drm_mode_to_intf_timing_params()
55 mode->hsync_start, mode->hsync_end, in drm_mode_to_intf_timing_params()
56 mode->htotal, mode->hdisplay); in drm_mode_to_intf_timing_params()
58 mode->vsync_start, mode->vsync_end, in drm_mode_to_intf_timing_params()
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