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Searched refs:mode_reg (Results 1 – 25 of 54) sorted by relevance

123

/drivers/clk/qcom/
Dclk-pll.c31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
71 regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_disable()
76 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); in clk_pll_disable()
153 regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); in clk_pll_set_rate()
250 qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8); in clk_pll_configure_sr()
259 qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0); in clk_pll_configure_sr_hpm_lp()
269 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); in clk_pll_sr2_enable()
[all …]
Dclk-hfpll.c63 regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL); in __clk_hfpll_enable()
72 regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); in __clk_hfpll_enable()
87 regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); in __clk_hfpll_enable()
100 regmap_read(regmap, hd->mode_reg, &mode); in clk_hfpll_enable()
117 regmap_update_bits(regmap, hd->mode_reg, in __clk_hfpll_disable()
209 regmap_read(regmap, hd->mode_reg, &mode); in clk_hfpll_init()
235 regmap_read(regmap, hd->mode_reg, &mode); in hfpll_is_enabled()
Dclk-hfpll.h11 u32 mode_reg; member
Dclk-pll.h44 u32 mode_reg; member
Dhfpll.c17 .mode_reg = 0x00,
Dgcc-ipq806x.c37 .mode_reg = 0x30c0,
66 .mode_reg = 0x3160,
95 .mode_reg = 0x3140,
120 .mode_reg = 0x3200,
146 .mode_reg = 0x3240,
172 .mode_reg = 0x3300,
202 .mode_reg = 0x31c0,
247 .mode_reg = 0x31a0,
266 .mode_reg = 0x3180,
/drivers/regulator/
Dsy8824x.c22 unsigned int mode_reg; member
45 regmap_update_bits(rdev->regmap, cfg->mode_reg, in sy8824_set_mode()
49 regmap_update_bits(rdev->regmap, cfg->mode_reg, in sy8824_set_mode()
65 ret = regmap_read(rdev->regmap, cfg->mode_reg, &val); in sy8824_get_mode()
168 .mode_reg = 0x00,
178 .mode_reg = 0x00,
188 .mode_reg = 0x01,
198 .mode_reg = 0x01,
Dfan53555.c127 unsigned int mode_reg; member
182 regmap_update_bits(rdev->regmap, di->mode_reg, in fan53555_set_mode()
200 ret = regmap_read(rdev->regmap, di->mode_reg, &val); in fan53555_get_mode()
420 di->mode_reg = FAN53555_CONTROL; in fan53555_device_setup()
433 di->mode_reg = di->vol_reg; in fan53555_device_setup()
437 di->mode_reg = TCS4525_COMMAND; in fan53555_device_setup()
Drtq2134-regulator.c66 unsigned int mode_reg; member
91 return regmap_update_bits(rdev->regmap, desc->mode_reg, desc->mode_mask, in rtq2134_buck_set_mode()
102 ret = regmap_read(rdev->regmap, desc->mode_reg, &mode); in rtq2134_buck_get_mode()
296 .mode_reg = RTQ2134_REG_BUCK##_id##_DVS0CFG0, \
Dmt6360-regulator.c37 unsigned int mode_reg; member
243 ret = regmap_update_bits(regmap, rdesc->mode_reg, rdesc->mode_mask, val << shift); in mt6360_regulator_set_mode()
260 ret = regmap_read(regmap, rdesc->mode_reg, &val); in mt6360_regulator_get_mode()
345 .mode_reg = mreg, \
Dpv88080-regulator.c38 unsigned int mode_reg; member
215 ret = regmap_read(rdev->regmap, info->mode_reg, &data); in pv88080_buck_get_mode()
256 return regmap_update_bits(rdev->regmap, info->mode_reg, in pv88080_buck_set_mode()
477 pv88080_regulator_info[i].mode_reg in pv88080_i2c_probe()
Dab8500.c190 u8 mode_reg; member
414 reg = info->mode_reg; in ab8500_regulator_set_mode()
512 info->mode_bank, info->mode_reg, &val); in ab8500_regulator_get_mode()
1077 .mode_reg = 0x54,
1098 .mode_reg = 0x54,
/drivers/net/can/ctucanfd/
Dctucanfd_base.c328 u32 mode_reg = ctucan_read32(priv, CTUCANFD_MODE); in ctucan_set_mode() local
330 mode_reg = (mode->flags & CAN_CTRLMODE_LOOPBACK) ? in ctucan_set_mode()
331 (mode_reg | REG_MODE_ILBP) : in ctucan_set_mode()
332 (mode_reg & ~REG_MODE_ILBP); in ctucan_set_mode()
334 mode_reg = (mode->flags & CAN_CTRLMODE_LISTENONLY) ? in ctucan_set_mode()
335 (mode_reg | REG_MODE_BMM) : in ctucan_set_mode()
336 (mode_reg & ~REG_MODE_BMM); in ctucan_set_mode()
338 mode_reg = (mode->flags & CAN_CTRLMODE_FD) ? in ctucan_set_mode()
339 (mode_reg | REG_MODE_FDE) : in ctucan_set_mode()
340 (mode_reg & ~REG_MODE_FDE); in ctucan_set_mode()
[all …]
/drivers/clk/spear/
Dclk-vco-pll.c199 mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK; in clk_vco_recalc_rate()
241 val = readl_relaxed(vco->mode_reg); in clk_vco_set_rate()
244 writel_relaxed(val, vco->mode_reg); in clk_vco_set_rate()
274 unsigned long flags, void __iomem *mode_reg, void __iomem in clk_register_vco_pll() argument
285 if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg || in clk_register_vco_pll()
300 vco->mode_reg = mode_reg; in clk_register_vco_pll()
312 parent_name, 0, mode_reg, PLL_ENABLE, 0, lock); in clk_register_vco_pll()
Dclk.h92 void __iomem *mode_reg; member
122 unsigned long flags, void __iomem *mode_reg, void __iomem
/drivers/gpu/drm/nouveau/dispnv04/
Ddfp.c95 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_disable()
122 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()
137 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()
207 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv04_dfp_prepare_sel_clk()
251 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_prepare()
288 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_dfp_mode_set()
464 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control = in nv04_dfp_commit()
556 nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); in nv04_lvds_dpms()
557 nv04_display(dev)->mode_reg.sel_clk &= ~0xf0; in nv04_lvds_dpms()
559 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); in nv04_lvds_dpms()
Dtvnv04.c79 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv04_tv_dpms()
107 struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head]; in nv04_tv_bind()
146 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_tv_mode_set()
Dcrtc.c67 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_digital_vibrance()
82 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_image_sharpening()
124 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv_crtc_calc_state_ext()
241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_vga()
466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_regs()
659 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); in nv_crtc_mode_set()
669 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv_crtc_save()
731 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); in nv_crtc_commit()
777 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; in nv_crtc_gamma_load()
788 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); in nv_crtc_gamma_load()
[all …]
Dcursor.c42 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_cursor_set_offset()
/drivers/media/i2c/
Dlm3646.c74 u8 mode_reg; member
87 REG_ENABLE, flash->mode_reg | MODE_SHDN); in lm3646_mode_ctrl()
90 REG_ENABLE, flash->mode_reg | MODE_TORCH); in lm3646_mode_ctrl()
93 REG_ENABLE, flash->mode_reg | MODE_FLASH); in lm3646_mode_ctrl()
303 flash->mode_reg = reg_val & 0xfc; in lm3646_init_device()
/drivers/net/ethernet/
Ddnet.c175 u32 mode_reg, ctl_reg; in dnet_handle_link_change() local
181 mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG); in dnet_handle_link_change()
201 mode_reg |= DNET_INTERNAL_MODE_GBITEN; in dnet_handle_link_change()
205 mode_reg &= ~DNET_INTERNAL_MODE_GBITEN; in dnet_handle_link_change()
220 mode_reg |= in dnet_handle_link_change()
223 mode_reg &= in dnet_handle_link_change()
236 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg); in dnet_handle_link_change()
/drivers/mfd/
Dmenelaus.c441 u8 mode_reg; member
470 ret = menelaus_write_reg(vtg->mode_reg, mode); in menelaus_set_voltage()
564 .mode_reg = MENELAUS_LDO_CTRL3,
593 .mode_reg = MENELAUS_LDO_CTRL4,
633 .mode_reg = MENELAUS_DCDC_CTRL2,
641 .mode_reg = MENELAUS_DCDC_CTRL3,
678 .mode_reg = MENELAUS_LDO_CTRL7,
708 .mode_reg = MENELAUS_LDO_CTRL6,
/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-stm32.c93 u32 mode_reg; /* MAC glue-logic mode register */ member
172 u32 reg = dwmac->mode_reg, clk_rate; in stm32mp1_set_mode()
233 u32 reg = dwmac->mode_reg; in stm32mcu_set_mode()
295 err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg); in stm32_dwmac_parse_data()
/drivers/tty/serial/
Dxilinx_uartps.c686 unsigned int ctrl_reg, mode_reg; in cdns_uart_set_termios() local
749 mode_reg = readl(port->membase + CDNS_UART_MR); in cdns_uart_set_termios()
789 cval |= mode_reg & 1; in cdns_uart_set_termios()
1024 u32 mode_reg; in cdns_uart_set_mctrl() local
1031 mode_reg = readl(port->membase + CDNS_UART_MR); in cdns_uart_set_mctrl()
1034 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK; in cdns_uart_set_mctrl()
1041 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP; in cdns_uart_set_mctrl()
1043 mode_reg |= CDNS_UART_MR_CHMODE_NORM; in cdns_uart_set_mctrl()
1046 writel(mode_reg, port->membase + CDNS_UART_MR); in cdns_uart_set_mctrl()
/drivers/mmc/host/
Datmel-mci.c340 u32 mode_reg; member
872 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE); in atmci_pdc_set_single_buf()
1056 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE); in atmci_prepare_data_pdc()
1257 atmci_writel(host, ATMCI_MR, host->mode_reg); in atmci_start_request()
1401 if (!host->mode_reg) { in atmci_set_ios()
1433 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) in atmci_set_ios()
1443 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); in atmci_set_ios()
1452 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); in atmci_set_ios()
1463 atmci_writel(host, ATMCI_MR, host->mode_reg); in atmci_set_ios()
1484 if (host->mode_reg) { in atmci_set_ios()
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