Searched refs:msm_readl (Results 1 – 11 of 11) sorted by relevance
96 return msm_readl(gmu->mmio + (offset << 2)); in gmu_read()124 val = (u64) msm_readl(gmu->mmio + (lo << 2)); in gmu_read64()125 val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32); in gmu_read64()136 return msm_readl(gmu->rscc + (offset << 2)); in gmu_read_rscc()
187 msm_readl((ptr) + ((offset) << 2))
126 return msm_readl(hdmi->mmio + reg); in hdmi_read()131 return msm_readl(hdmi->qfprom_mmio + reg); in hdmi_qfprom_read()177 return msm_readl(phy->mmio + reg); in hdmi_phy_read()
244 return msm_readl(pll->mmio + reg); in pll_read()
94 return msm_readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
553 return msm_readl(gpu->mmio + (reg << 2)); in gpu_read()579 val = (u64) msm_readl(gpu->mmio + (reg << 2)); in gpu_read64()580 val |= ((u64) msm_readl(gpu->mmio + ((reg + 1) << 2)) << 32); in gpu_read64()
478 #define msm_readl(addr) readl((addr)) macro482 u32 val = msm_readl(addr); in msm_rmw()
15 #define dsi_phy_read(offset) msm_readl((offset))
52 return msm_readl(mdp4_kms->mmio + reg); in mdp4_read()
181 return msm_readl(mdp5_kms->mmio + reg); in mdp5_read()
57 ver = msm_readl(base + REG_DSI_VERSION); in dsi_get_version()75 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); in dsi_get_version()80 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); in dsi_get_version()201 return msm_readl(msm_host->ctrl_base + reg); in dsi_read()