| /drivers/gpu/drm/radeon/ |
| D | radeon_object.c | 618 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; in radeon_bo_set_tiling_flags() local
622 …mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TIL… in radeon_bo_set_tiling_flags()
645 switch (mtaspect) { in radeon_bo_set_tiling_flags()
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| D | evergreen_cs.c | 1182 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local
1185 &bankw, &bankh, &mtaspect, in evergreen_cs_handle_reg()
1191 DB_MACRO_TILE_ASPECT(mtaspect); in evergreen_cs_handle_reg()
1446 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local
1449 &bankw, &bankh, &mtaspect, in evergreen_cs_handle_reg()
1455 CB_MACRO_TILE_ASPECT(mtaspect); in evergreen_cs_handle_reg()
1474 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local
1477 &bankw, &bankh, &mtaspect, in evergreen_cs_handle_reg()
1483 CB_MACRO_TILE_ASPECT(mtaspect); in evergreen_cs_handle_reg()
2363 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_packet3_check() local
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| D | evergreen.c | 1111 unsigned *bankh, unsigned *mtaspect, in evergreen_tiling_fields() argument
1116 …*mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TI… in evergreen_tiling_fields()
1132 switch (*mtaspect) { in evergreen_tiling_fields()
1134 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break; in evergreen_tiling_fields()
1135 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break; in evergreen_tiling_fields()
1136 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break; in evergreen_tiling_fields()
1137 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break; in evergreen_tiling_fields()
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| D | atombios_crtc.c | 1147 unsigned bankw, bankh, mtaspect, tile_split; in dce4_crtc_do_set_base() local
1267 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1335 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); in dce4_crtc_do_set_base()
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| D | radeon.h | 356 unsigned *bankh, unsigned *mtaspect,
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_plane.c | 171 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; in fill_gfx8_tiling_info_from_flags() local
175 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in fill_gfx8_tiling_info_from_flags()
186 tiling_info->gfx8.tile_aspect = mtaspect; in fill_gfx8_tiling_info_from_flags()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | dce_v8_0.c | 1910 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v8_0_crtc_do_set_base() local
1914 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
1923 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); in dce_v8_0_crtc_do_set_base()
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| D | dce_v6_0.c | 1937 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v6_0_crtc_do_set_base() local
1941 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base()
1950 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect); in dce_v6_0_crtc_do_set_base()
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| D | dce_v10_0.c | 1989 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v10_0_crtc_do_set_base() local
1993 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
2005 mtaspect); in dce_v10_0_crtc_do_set_base()
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| D | dce_v11_0.c | 2031 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v11_0_crtc_do_set_base() local
2035 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
2047 mtaspect); in dce_v11_0_crtc_do_set_base()
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