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Searched refs:num_heads (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/qxl/
Dqxl_drv.c64 MODULE_PARM_DESC(num_heads, "Number of virtual crtcs to expose (default 4)");
65 module_param_named(num_heads, qxl_num_crtc, int, 0400);
/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c504 u32 num_heads; /* number of active crtcs */ member
697 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v6_0_latency_watermark()
698 (wm->num_heads * cursor_line_pair_return_time); in dce_v6_0_latency_watermark()
704 if (wm->num_heads == 0) in dce_v6_0_latency_watermark()
718 b.full = dfixed_const(wm->num_heads); in dce_v6_0_latency_watermark()
753 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display()
773 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_available_bandwidth()
827 u32 lb_size, u32 num_heads) in dce_v6_0_program_watermarks() argument
841 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v6_0_program_watermarks()
877 wm_high.num_heads = num_heads; in dce_v6_0_program_watermarks()
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Ddce_v8_0.c641 u32 num_heads; /* number of active crtcs */ member
834 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v8_0_latency_watermark()
835 (wm->num_heads * cursor_line_pair_return_time); in dce_v8_0_latency_watermark()
841 if (wm->num_heads == 0) in dce_v8_0_latency_watermark()
855 b.full = dfixed_const(wm->num_heads); in dce_v8_0_latency_watermark()
890 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display()
910 (dce_v8_0_available_bandwidth(wm) / wm->num_heads)) in dce_v8_0_average_bandwidth_vs_available_bandwidth()
964 u32 lb_size, u32 num_heads) in dce_v8_0_program_watermarks() argument
973 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v8_0_program_watermarks()
1005 wm_high.num_heads = num_heads; in dce_v8_0_program_watermarks()
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Ddce_v10_0.c706 u32 num_heads; /* number of active crtcs */ member
899 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v10_0_latency_watermark()
900 (wm->num_heads * cursor_line_pair_return_time); in dce_v10_0_latency_watermark()
906 if (wm->num_heads == 0) in dce_v10_0_latency_watermark()
920 b.full = dfixed_const(wm->num_heads); in dce_v10_0_latency_watermark()
955 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display()
975 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_available_bandwidth()
1029 u32 lb_size, u32 num_heads) in dce_v10_0_program_watermarks() argument
1038 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v10_0_program_watermarks()
1070 wm_high.num_heads = num_heads; in dce_v10_0_program_watermarks()
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Ddce_v11_0.c732 u32 num_heads; /* number of active crtcs */ member
925 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v11_0_latency_watermark()
926 (wm->num_heads * cursor_line_pair_return_time); in dce_v11_0_latency_watermark()
932 if (wm->num_heads == 0) in dce_v11_0_latency_watermark()
946 b.full = dfixed_const(wm->num_heads); in dce_v11_0_latency_watermark()
981 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display()
1001 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_available_bandwidth()
1055 u32 lb_size, u32 num_heads) in dce_v11_0_program_watermarks() argument
1064 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v11_0_program_watermarks()
1096 wm_high.num_heads = num_heads; in dce_v11_0_program_watermarks()
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/drivers/gpu/drm/tegra/
Dhub.h48 unsigned int num_heads; member
Dhub.c973 unsigned int i = hub->num_heads; in tegra_display_hub_runtime_suspend()
1017 for (i = 0; i < hub->num_heads; i++) { in tegra_display_hub_runtime_resume()
1120 hub->num_heads = of_get_child_count(pdev->dev.of_node); in tegra_display_hub_probe()
1122 hub->clk_heads = devm_kcalloc(&pdev->dev, hub->num_heads, sizeof(clk), in tegra_display_hub_probe()
1127 for (i = 0; i < hub->num_heads; i++) { in tegra_display_hub_probe()
/drivers/gpu/drm/radeon/
Devergreen.c1943 u32 num_heads; /* number of active crtcs */ member
2071 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in evergreen_latency_watermark()
2072 (wm->num_heads * cursor_line_pair_return_time); in evergreen_latency_watermark()
2077 if (wm->num_heads == 0) in evergreen_latency_watermark()
2091 b.full = dfixed_const(wm->num_heads); in evergreen_latency_watermark()
2113 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads)) in evergreen_average_bandwidth_vs_dram_bandwidth_for_display()
2122 (evergreen_available_bandwidth(wm) / wm->num_heads)) in evergreen_average_bandwidth_vs_available_bandwidth()
2156 u32 lb_size, u32 num_heads) in evergreen_program_watermarks() argument
2171 if (radeon_crtc->base.enabled && num_heads && mode) { in evergreen_program_watermarks()
2206 wm_high.num_heads = num_heads; in evergreen_program_watermarks()
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Dsi.c2062 u32 num_heads; /* number of active crtcs */ member
2207 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce6_latency_watermark()
2208 (wm->num_heads * cursor_line_pair_return_time); in dce6_latency_watermark()
2214 if (wm->num_heads == 0) in dce6_latency_watermark()
2228 b.full = dfixed_const(wm->num_heads); in dce6_latency_watermark()
2252 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce6_average_bandwidth_vs_dram_bandwidth_for_display()
2261 (dce6_available_bandwidth(wm) / wm->num_heads)) in dce6_average_bandwidth_vs_available_bandwidth()
2295 u32 lb_size, u32 num_heads) in dce6_program_watermarks() argument
2309 if (radeon_crtc->base.enabled && num_heads && mode) { in dce6_program_watermarks()
2348 wm_high.num_heads = num_heads; in dce6_program_watermarks()
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Dcik.c8908 u32 num_heads; /* number of active crtcs */ member
9101 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce8_latency_watermark()
9102 (wm->num_heads * cursor_line_pair_return_time); in dce8_latency_watermark()
9108 if (wm->num_heads == 0) in dce8_latency_watermark()
9122 b.full = dfixed_const(wm->num_heads); in dce8_latency_watermark()
9157 (dce8_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce8_average_bandwidth_vs_dram_bandwidth_for_display()
9177 (dce8_available_bandwidth(wm) / wm->num_heads)) in dce8_average_bandwidth_vs_available_bandwidth()
9231 u32 lb_size, u32 num_heads) in dce8_program_watermarks() argument
9240 if (radeon_crtc->base.enabled && num_heads && mode) { in dce8_program_watermarks()
9273 wm_high.num_heads = num_heads; in dce8_program_watermarks()
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