| /drivers/gpu/drm/panel/ |
| D | panel-seiko-43wvf1g.c | 27 unsigned int num_timings; member
67 for (i = 0; i < panel->desc->num_timings; i++) { in seiko_panel_get_fixed_modes()
83 if (panel->desc->num_timings == 1) in seiko_panel_get_fixed_modes()
208 unsigned int num_timings, in seiko_panel_get_timings() argument
214 if (p->desc->num_timings < num_timings) in seiko_panel_get_timings()
215 num_timings = p->desc->num_timings; in seiko_panel_get_timings()
218 for (i = 0; i < num_timings; i++) in seiko_panel_get_timings()
221 return p->desc->num_timings; in seiko_panel_get_timings()
301 .num_timings = 1,
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| D | panel-simple.c | 69 unsigned int num_timings; member
172 for (i = 0; i < panel->desc->num_timings; i++) { in panel_simple_get_timings_modes()
188 if (panel->desc->num_timings == 1) in panel_simple_get_timings_modes()
251 if (num == 0 && panel->desc->num_timings) in panel_simple_get_non_edid_modes()
260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); in panel_simple_get_non_edid_modes()
427 unsigned int num_timings, in panel_simple_get_timings() argument
433 if (p->desc->num_timings < num_timings) in panel_simple_get_timings()
434 num_timings = p->desc->num_timings; in panel_simple_get_timings()
437 for (i = 0; i < num_timings; i++) in panel_simple_get_timings()
440 return p->desc->num_timings; in panel_simple_get_timings()
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| D | panel-edp.c | 172 unsigned int num_timings; member
250 for (i = 0; i < panel->desc->num_timings; i++) { in panel_edp_get_timings_modes()
266 if (panel->desc->num_timings == 1) in panel_edp_get_timings_modes()
347 if (num == 0 && panel->desc->num_timings) in panel_edp_get_non_edid_modes()
356 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); in panel_edp_get_non_edid_modes()
624 if (p->desc->num_timings || p->desc->num_modes) in panel_edp_get_modes()
639 unsigned int num_timings, in panel_edp_get_timings() argument
645 if (p->desc->num_timings < num_timings) in panel_edp_get_timings()
646 num_timings = p->desc->num_timings; in panel_edp_get_timings()
649 for (i = 0; i < num_timings; i++) in panel_edp_get_timings()
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| /drivers/video/ |
| D | of_display_timing.c | 180 disp->num_timings = of_get_child_count(timings_np); in of_get_display_timings()
181 if (disp->num_timings == 0) { in of_get_display_timings()
187 disp->timings = kcalloc(disp->num_timings, in of_get_display_timings()
195 disp->num_timings = 0; in of_get_display_timings()
216 np, disp->num_timings + 1); in of_get_display_timings()
222 disp->native_mode = disp->num_timings; in of_get_display_timings()
224 disp->timings[disp->num_timings] = dt; in of_get_display_timings()
225 disp->num_timings++; in of_get_display_timings()
235 np, disp->num_timings, in of_get_display_timings()
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| D | display_timing.c | 17 for (i = 0; i < disp->num_timings; i++) in display_timings_release()
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| /drivers/clk/tegra/ |
| D | clk-tegra124-emc.c | 81 int num_timings; member
125 for (k = 0; k < tegra->num_timings; k++) { in emc_determine_rate()
130 for (t = k; t < tegra->num_timings; t++) { in emc_determine_rate()
296 for (i = timing_index+1; i < tegra->num_timings; i++) { in get_backup_timing()
342 for (i = 0; i < tegra->num_timings; i++) { in emc_set_rate()
452 size = (tegra->num_timings + child_count) * sizeof(struct emc_timing); in load_timings_from_dt()
458 timings_ptr = tegra->timings + tegra->num_timings; in load_timings_from_dt()
459 tegra->num_timings += child_count; in load_timings_from_dt()
504 tegra->num_timings = 0; in tegra124_clk_register_emc()
524 if (tegra->num_timings == 0) in tegra124_clk_register_emc()
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| /drivers/memory/tegra/ |
| D | tegra30-emc.c | 367 unsigned int num_timings; member
443 for (i = 0; i < emc->num_timings; i++) { in emc_find_timing()
508 for (i = 0; i < mc->num_timings; i++) { in emc_prepare_mc_clk_cfg()
961 if (emc->num_timings != mc->num_timings) { in emc_check_mc_timings()
963 emc->num_timings, mc->num_timings); in emc_check_mc_timings()
967 for (i = 0; i < mc->num_timings; i++) { in emc_check_mc_timings()
998 emc->num_timings = child_count; in emc_load_timings_from_dt()
1009 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in emc_load_timings_from_dt()
1018 emc->num_timings, in emc_load_timings_from_dt()
1021 emc->timings[emc->num_timings - 1].rate / 1000000); in emc_load_timings_from_dt()
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| D | tegra210-emc-table.c | 41 if (count != emc->num_timings) { in tegra210_emc_table_device_init()
43 count, emc->num_timings); in tegra210_emc_table_device_init()
50 emc->num_timings = count; in tegra210_emc_table_device_init()
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| D | tegra20-emc.c | 207 unsigned int num_timings; member
262 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
441 emc->num_timings++; in tegra_emc_load_timings_from_dt()
444 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in tegra_emc_load_timings_from_dt()
449 emc->num_timings, in tegra_emc_load_timings_from_dt()
452 emc->timings[emc->num_timings - 1].rate / 1000000); in tegra_emc_load_timings_from_dt()
684 if (!emc->num_timings) in emc_round_rate()
687 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); in emc_round_rate()
689 for (i = 0; i < emc->num_timings; i++) { in emc_round_rate()
690 if (emc->timings[i].rate < rate && i != emc->num_timings - 1) in emc_round_rate()
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| D | tegra210-emc-core.c | 860 for (i = 0; i < emc->num_timings; i++) in tegra210_emc_find_timing()
1541 for (i = 0; i < emc->num_timings; i++) { in tegra210_emc_set_rate()
1601 for (i = 0; i < emc->num_timings; i++) in tegra210_emc_validate_rate()
1615 for (i = 0; i < emc->num_timings; i++) { in tegra210_emc_debug_available_rates_show()
1739 for (i = 0; i < emc->num_timings; i++) { in tegra210_emc_debugfs_init()
1747 if (!emc->num_timings) { in tegra210_emc_debugfs_init()
1801 unsigned int num_timings) in tegra210_emc_validate_timings() argument
1805 for (i = 0; i < num_timings; i++) { in tegra210_emc_validate_timings()
1878 emc->num_timings); in tegra210_emc_probe()
1885 emc->num_timings); in tegra210_emc_probe()
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| D | tegra124-emc.c | 496 unsigned int num_timings; member
580 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
1005 emc->num_timings = child_count; in tegra_emc_load_timings_from_dt()
1017 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in tegra_emc_load_timings_from_dt()
1155 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
1169 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
1249 for (i = 0; i < emc->num_timings; i++) { in emc_debugfs_init()
1257 if (!emc->num_timings) { in emc_debugfs_init()
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| D | mc.c | 323 for (i = 0; i < mc->num_timings; i++) { in tegra_mc_write_emem_configuration()
437 mc->num_timings = child_count; in load_timings()
460 mc->num_timings = 0; in tegra_mc_setup_timings()
475 if (mc->num_timings == 0) in tegra_mc_setup_timings()
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| D | tegra210-emc.h | 898 unsigned int num_timings; member
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| /drivers/phy/rockchip/ |
| D | phy-rockchip-inno-dsidphy.c | 201 const unsigned int num_timings; member
461 for (i = 0; i < inno->pdata->num_timings; i++) in inno_dsidphy_mipi_mode_enable()
465 if (i == inno->pdata->num_timings) in inno_dsidphy_mipi_mode_enable()
686 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz),
692 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz),
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| /drivers/gpu/drm/tilcdc/ |
| D | tilcdc_panel.c | 142 for (i = 0; i < timings->num_timings; i++) { in panel_connector_get_modes()
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| /drivers/video/fbdev/ |
| D | pxafb.c | 2127 info->modes = devm_kcalloc(dev, timings->num_timings, in of_get_pxafb_display()
2132 info->num_modes = timings->num_timings; in of_get_pxafb_display()
2134 for (i = 0; i < timings->num_timings; i++) { in of_get_pxafb_display()
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| /drivers/gpu/drm/ |
| D | drm_edid.c | 6322 int num_timings; in add_displayid_detailed_1_modes() local
6330 num_timings = block->num_bytes / 20; in add_displayid_detailed_1_modes()
6331 for (i = 0; i < num_timings; i++) { in add_displayid_detailed_1_modes()
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