/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
D | vmap.c | 36 vmap = nvbios_rd32(bios, bit_P.offset + 0x20); in nvbios_vmap_table() 101 info->min = nvbios_rd32(bios, vmap + 0x00); in nvbios_vmap_entry_parse() 102 info->max = nvbios_rd32(bios, vmap + 0x04); in nvbios_vmap_entry_parse() 103 info->arg[0] = nvbios_rd32(bios, vmap + 0x08); in nvbios_vmap_entry_parse() 104 info->arg[1] = nvbios_rd32(bios, vmap + 0x0c); in nvbios_vmap_entry_parse() 105 info->arg[2] = nvbios_rd32(bios, vmap + 0x10); in nvbios_vmap_entry_parse() 110 info->min = nvbios_rd32(bios, vmap + 0x02); in nvbios_vmap_entry_parse() 111 info->max = nvbios_rd32(bios, vmap + 0x06); in nvbios_vmap_entry_parse() 112 info->arg[0] = nvbios_rd32(bios, vmap + 0x0a); in nvbios_vmap_entry_parse() 113 info->arg[1] = nvbios_rd32(bios, vmap + 0x0e); in nvbios_vmap_entry_parse() [all …]
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D | pmu.c | 37 data = nvbios_rd32(bios, bit_p.offset + 0x00); in nvbios_pmuTe() 69 info->data = nvbios_rd32(bios, data + 0x02); in nvbios_pmuEp() 83 info->init_addr_pmu = nvbios_rd32(bios, data + 0x08); in nvbios_pmuRm() 84 info->args_addr_pmu = nvbios_rd32(bios, data + 0x0c); in nvbios_pmuRm() 86 info->boot_addr_pmu = nvbios_rd32(bios, data + 0x10) + in nvbios_pmuRm() 87 nvbios_rd32(bios, data + 0x18); in nvbios_pmuRm() 88 info->boot_size = nvbios_rd32(bios, data + 0x1c) - in nvbios_pmuRm() 89 nvbios_rd32(bios, data + 0x18); in nvbios_pmuRm() 93 info->code_size = nvbios_rd32(bios, data + 0x20); in nvbios_pmuRm() 95 nvbios_rd32(bios, data + 0x24); in nvbios_pmuRm() [all …]
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D | volt.c | 36 volt = nvbios_rd32(bios, bit_P.offset + 0x0c); in nvbios_volt_table() 39 volt = nvbios_rd32(bios, bit_P.offset + 0x10); in nvbios_volt_table() 92 info->base = nvbios_rd32(bios, volt + 0x04); in nvbios_volt_parse() 98 info->max = nvbios_rd32(bios, volt + 0x0e); in nvbios_volt_parse() 103 info->min = nvbios_rd32(bios, volt + 0x0a); in nvbios_volt_parse() 104 info->max = nvbios_rd32(bios, volt + 0x0e); in nvbios_volt_parse() 105 info->base = nvbios_rd32(bios, volt + 0x12) & 0x00ffffff; in nvbios_volt_parse() 108 if (nvbios_rd32(bios, volt + 0x4) & 1) { in nvbios_volt_parse() 110 info->pwm_freq = nvbios_rd32(bios, volt + 0x5) / 1000; in nvbios_volt_parse() 111 info->pwm_range = nvbios_rd32(bios, volt + 0x16); in nvbios_volt_parse() [all …]
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D | timing.c | 37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe() 40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe() 140 p->timing[0] = nvbios_rd32(bios, data + 0x00); in nvbios_timingEp() 141 p->timing[1] = nvbios_rd32(bios, data + 0x04); in nvbios_timingEp() 142 p->timing[2] = nvbios_rd32(bios, data + 0x08); in nvbios_timingEp() 143 p->timing[3] = nvbios_rd32(bios, data + 0x0c); in nvbios_timingEp() 144 p->timing[4] = nvbios_rd32(bios, data + 0x10); in nvbios_timingEp() 145 p->timing[5] = nvbios_rd32(bios, data + 0x14); in nvbios_timingEp() 146 p->timing[6] = nvbios_rd32(bios, data + 0x18); in nvbios_timingEp() 147 p->timing[7] = nvbios_rd32(bios, data + 0x1c); in nvbios_timingEp() [all …]
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D | init.c | 484 u32 reg = nvbios_rd32(bios, table + (cond * 12) + 0); in init_condition_met() 485 u32 msk = nvbios_rd32(bios, table + (cond * 12) + 4); in init_condition_met() 486 u32 val = nvbios_rd32(bios, table + (cond * 12) + 8); in init_condition_met() 629 u32 reg = nvbios_rd32(bios, init->offset + 7); in init_io_restrict_prog() 639 u32 data = nvbios_rd32(bios, init->offset); in init_io_restrict_prog() 693 u32 reg = nvbios_rd32(bios, init->offset + 8); in init_io_restrict_pll() 743 u32 reg = nvbios_rd32(bios, init->offset + 1); in init_copy() 889 u32 reg = nvbios_rd32(bios, init->offset + 1); in init_andn_reg() 890 u32 mask = nvbios_rd32(bios, init->offset + 5); in init_andn_reg() 906 u32 reg = nvbios_rd32(bios, init->offset + 1); in init_or_reg() [all …]
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D | pll.c | 90 data = nvbios_rd32(bios, bit_C.offset + 0); in pll_limits_table() 153 if (nvbios_rd32(bios, data + 3) == reg) { in pll_map_reg() 168 if (nvbios_rd32(bios, data) == map->reg) in pll_map_reg() 197 *reg = nvbios_rd32(bios, data + 3); in pll_map_type() 213 if (nvbios_rd32(bios, data) == map->reg) in pll_map_type() 257 info->vco1.min_freq = nvbios_rd32(bios, data + 0); in nvbios_pll_parse() 258 info->vco1.max_freq = nvbios_rd32(bios, data + 4); in nvbios_pll_parse() 259 info->vco2.min_freq = nvbios_rd32(bios, data + 8); in nvbios_pll_parse() 260 info->vco2.max_freq = nvbios_rd32(bios, data + 12); in nvbios_pll_parse() 261 info->vco1.min_inputfreq = nvbios_rd32(bios, data + 16); in nvbios_pll_parse() [all …]
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D | power_budget.c | 39 power_budget = nvbios_rd32(bios, bit_P.offset + 0x2c); in nvbios_power_budget_table() 116 entry->min_w = nvbios_rd32(bios, entry_offset + 0x2); in nvbios_power_budget_entry() 117 entry->avg_w = nvbios_rd32(bios, entry_offset + 0x6); in nvbios_power_budget_entry() 118 entry->max_w = nvbios_rd32(bios, entry_offset + 0xa); in nvbios_power_budget_entry() 121 entry->max_w = nvbios_rd32(bios, entry_offset + 0x2); in nvbios_power_budget_entry()
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D | dcb.c | 48 if (nvbios_rd32(bios, dcb + 6) == 0x4edcbdcb) { in dcb_table() 56 if (nvbios_rd32(bios, dcb + 4) == 0x4edcbdcb) { in dcb_table() 128 u32 conn = nvbios_rd32(bios, dcb + 0x00); in dcb_outp_parse() 142 u32 conf = nvbios_rd32(bios, dcb + 0x04); in dcb_outp_parse() 219 if (nvbios_rd32(bios, outp) == 0x00000000) in dcb_outp_foreach() 221 if (nvbios_rd32(bios, outp) == 0xffffffff) in dcb_outp_foreach()
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D | P0260.c | 37 data = nvbios_rd32(bios, bit_P.offset + 0x60); in nvbios_P0260Te() 75 info->data = nvbios_rd32(bios, data); in nvbios_P0260Ep() 101 info->data = nvbios_rd32(bios, data); in nvbios_P0260Xp()
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D | npde.c | 35 switch (nvbios_rd32(bios, data + 0x00)) { in nvbios_npdeTe() 41 data, nvbios_rd32(bios, data + 0x00)); in nvbios_npdeTe()
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D | gpio.c | 94 u32 info = nvbios_rd32(bios, data); in dcb_gpio_parse() 103 u32 info = nvbios_rd32(bios, data + 0); in dcb_gpio_parse() 104 u8 info1 = nvbios_rd32(bios, data + 4); in dcb_gpio_parse()
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D | pcir.c | 33 switch (nvbios_rd32(bios, data + 0x00)) { in nvbios_pcirTe() 43 data, nvbios_rd32(bios, data + 0x00)); in nvbios_pcirTe()
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D | fan.c | 36 fan = nvbios_rd32(bios, bit_P.offset + 0x58); in nvbios_fan_table() 90 fan->pwm_freq = nvbios_rd32(bios, data + 0x0b) & 0xffffff; in nvbios_fan_parse()
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D | perf.c | 38 perf = nvbios_rd32(bios, bit_P.offset + 0); in nvbios_perf_table() 105 info->core = nvbios_rd32(bios, perf + 0x01) * 10; in nvbios_perfEp() 106 info->memory = nvbios_rd32(bios, perf + 0x05) * 20; in nvbios_perfEp()
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D | M0209.c | 37 data = nvbios_rd32(bios, bit_M.offset + 0x09); in nvbios_M0209Te() 125 info->data[i] = nvbios_rd32(bios, data + off); in nvbios_M0209Sp()
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D | therm.c | 36 therm = nvbios_rd32(bios, bit_P.offset + 12); in therm_table() 38 therm = nvbios_rd32(bios, bit_P.offset + 16); in therm_table()
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D | vpstate.c | 35 return nvbios_rd32(b, bit_P.offset + 0x38); in nvbios_vpstate_offset()
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D | rammap.c | 37 rammap = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_rammapTe() 111 temp = nvbios_rd32(bios, data + 0x09); in nvbios_rammapEp()
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D | iccsense.c | 40 iccsense = nvbios_rd32(bios, bit_P.offset + 0x28); in nvbios_iccsense_table()
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/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
D | ramgp100.c | 56 data = nvbios_rd32(bios, data + 0x10); /* guess u32... */ in gp100_ram_init() 62 nvbios_init(subdev, nvbios_rd32(bios, data)); in gp100_ram_init()
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/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
D | gm200.c | 42 nvkm_wr32(device, 0x10a184, nvbios_rd32(bios, img + i)); in pmu_code() 60 nvkm_wr32(device, 0x10a1c4, nvbios_rd32(bios, img + i)); in pmu_data()
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D | nv05.c | 83 u32 scramble = nvbios_rd32(bios, data); in nv05_devinit_meminit()
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/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
D | gm107.c | 317 u32 data = nvbios_rd32(bios, bit_P.offset + 0x28); in gm107_gr_init_bios_2() 322 data = nvbios_rd32(bios, data + 0x04); in gm107_gr_init_bios_2()
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/drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
D | bios.h | 31 u32 nvbios_rd32(struct nvkm_bios *, u32 addr);
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/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ |
D | gf119.c | 36 u32 data = nvbios_rd32(bios, entry); in gf119_gpio_reset()
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